JPH08241302A - Vector processor and multiplier - Google Patents

Abstract

PURPOSE: To provide the vector processor which makes it possible to perform vector addition processing fast and the multiplier which is suitably used for vector multiplication processing performed by using the vector addition processing of the vector processor. CONSTITUTION: The vector processor which is equipped with at least a vector register 12, a mask register 13, and an adder 14 and performs vector processing employs constitution wherein data of the mask register 13 are inputted to the adder 14 in addition to the addend and augend of a vector operand and carry- out data calculated by the adder 14 are outputted to the mask register 13. Further, the multiplier 15 has a function for calculating 2m-bit data as the multipication value of two (m)-bit input data and is so constituted as to have a selector which selects and outputs one of the high-order (m) bit data and low-order (m)-bit data of the multiplication value in response to an instruction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector processing device capable of executing a vector addition process at high speed, and a multiplication suitable for use in a vector multiplication process executed by using the vector addition process of the vector processing device. Related to vessels.

A vector processing device executes vector addition processing and vector multiplication processing. It is necessary to enable such vector calculation processing to be executed at high speed.

[0003]

2. Description of the Related Art In a conventional vector processing device, when a vector addition process is executed, a vector addition command is executed while a vector shift command is executed in consideration of the occurrence of a carry. .

Next, this conventional technique will be described in detail by taking the addition processing of the 160-bit addend and the 160-bit addend as an example. When the adder executes an addition process of 64 bits, conventionally, as shown in FIG.
A register for an addend consisting of three registers (vr00, vr01, vr02) of bits and a register for addend consisting of three registers of 64 bits (vr03, vr04, vr05) are prepared. According to the format shown in FIG. 14, that is, the format shown in FIG. 15, the augend of 160 bits is stored in the register for the augend, and
The 160-bit addend is stored in the addend register.

By issuing the vector instruction sequence shown in FIG. 16, the addition process of the 160-bit augend and the 160-bit augend is executed. Here, “VA vr1, vr2, vr3” is the vector register vr1 and the vector register vr2.
Is a vector addition instruction to store the addition result with the vector register vr3, and "VSR vr1, SC, vr3" is a vector shift instruction to store the data of the vector register vr1 right SC bits and store it in the vector register vr3. And "VSL vr1, SC, vr3" is a vector shift instruction to shift the data in the vector register vr1 left by SC bits and store it in the vector register vr3.

That is, according to the vector instruction sequence shown in FIG. 16, first, according to the vector addition instruction VA of (1), the augend part of the vector register vr02 and the addend part of the vector register vr05 are added. Store in vector register vr10. At this time, a carry may occur, so the vector shift instruction VS of (2) is continued.
According to R, the data stored in the vector register 10 is right-shifted by 60 bits to take out the carry value (carry-out data) and store it in the vector register 15.

Then, in accordance with the vector addition instruction VA of (3), the augend of the vector register vr01 and the augend of the vector register vr04 are added and stored in the vector register vr20.

Then, in accordance with the vector addition instruction VA of (4), the carry-out data stored in the vector register vr15 and the vector register vr20 are added in order to add the carry-out data generated by the addition processing of the lower part.
The stored data is added and stored in the vector register vr20. At this time, a carry may occur. Then, according to the vector shift instruction VSR in (5), the stored data in the vector register 20 is right-shifted by 60 bits to take out the carry-out data, Is stored in the vector register vr25.

Then, according to the vector addition instruction VA of (6), the augend part of the vector register vr00 and the addend part of the vector register vr03 are added and stored in the vector register vr30.

Then, in accordance with the vector addition instruction VA of (7), the carry-out data stored in the vector register vr25 and the vector register vr30 are added in order to add the carry-out data generated by the addition processing of the lower part.
And the stored data are stored in the vector register vr6.

Then, in order to take out the 60-bit effective data stored in the vector register vr10, the vector register 10 according to the vector shift instruction VSL of (8)
The stored data of is shifted left by 4 bits and stored in the vector register vr10, and the vector shift instruction V of (9)
According to SR, the data stored in the vector register vr10 is right-shifted by 4 bits and stored in the vector register vr8, so that the 60-bit effective data having a zero value in the upper 4 bits is stored in the vector register vr8.

Then, in order to take out the 60-bit effective data stored in the vector register vr20, the vector register 20 according to the vector shift instruction VSL in (10)
The stored data of 4 is left-shifted by 4 bits and stored in the vector register vr20, and the vector shift instruction V of (11)
According to SR, the data stored in the vector register vr20 is right-shifted by 4 bits and stored in the vector register vr7, so that the 60-bit effective data having a zero value in the upper 4 bits is stored in the vector register vr7.

As described above, in the conventional vector processing device, when the vector addition process is executed, the vector addition command is executed while the vector shift command is executed in consideration of the occurrence of carry. It was.

On the other hand, in the multiplier provided in the conventional vector processing device, even if it has an input specification of 64 bits × 64 bits, in order to reduce the amount of hardware, the multiplier of 64 bits × 16 bits is used. It adopted a configuration with a multiplication function with such a small number of bits.

Then, in order to realize the multiplication process of 64 bits of the input specifications, the multiplier is divided into 4 in 16-bit units, and the 16-bit multiplier part and 64 A partial product is obtained by multiplying by the multiplicand of bits, the partial products are added while being shifted by 16 bits, and the 64-bit part indicated by the addition result is output as the multiplication result.

For example, when the upper 64 bits of the multiplication process of 64 bits are required, according to the instruction,
As shown in FIG. 17, the multipliers divided into four are sequentially selected from the lower side to obtain partial products, and the partial products are added while being left shifted by 16 bits.
I got a bit and output it. If the lower 64 bits of the 64-bit multiplication process are required, the four-divided multipliers are sequentially selected from the upper side in accordance with the instruction, and partial products are obtained. The lower 64 bits of the multiplication process are obtained and output by adding while shifting.

[0017]

However, as in the prior art, when the vector addition processing is executed, the vector addition instruction is executed while the vector shift instruction is executed in consideration of the occurrence of a carry. If such a configuration is adopted, there is a problem that the vector addition processing cannot be executed at high speed because the number of instructions increases.

Further, in the prior art multiplier, the number of multiplications to be executed internally increases, and it is necessary to internally have a function of shifting and adding partial products (using a loop structure). There was a problem.

The present invention has been made in view of the above circumstances, and provides a vector processing device capable of executing a vector addition process at high speed and a vector executed by using the vector addition process of the vector processing device. An object of the present invention is to provide a multiplier suitable for use in multiplication processing.

[0020]

FIG. 1 shows the principle configuration of the present invention. In the figure, reference numeral 1 is a vector processing device equipped with the present invention, which includes a CPU 10 and a vector instruction control mechanism 1.
1, vector register 12, mask register 13
And an adder 14 and a multiplier 15.

The CPU 10 issues a vector instruction. The vector instruction control mechanism 11 controls the execution of vector instructions. The vector register 12 stores vector data. The mask register 13 stores mask data used in vector processing. The adder 14 executes a vector addition instruction. The multiplier 15 executes a vector multiplication instruction.

To implement the invention, the adder 14 is
In addition to the addend and the augend of the vector operand, carry-out data stored in the mask register 13 is input, and the carry-out data of the calculation result is output to the mask register 13. At this time, if the number of registers specified by the instruction increases due to the increase of the mask operand, in order to suppress the number of registers specified by the instruction,
It is preferable to use the same mask register for input and the same mask register for output.

On the other hand, in order to realize the present invention, the multiplier 1
5 has a function of calculating 2m-bit data which is a multiplication value of two pieces of input m-bit data, and in response to an instruction, outputs either the upper m-bit data or the lower m-bit data of the multiplication value. It adopts a configuration that has a selector for selecting and outputting.

Furthermore, in the vector processing device 1 of the present invention,
When the register number designated by the instruction for inputting from the register points to the specific vector register 12 or the specific mask register 13, the data from that register is treated as a zero value to execute the input processing, and The register number specified by the instruction that directs output is
When designating a specific vector register 12 or a specific mask register 13, the data output process to that register is not executed.

By adopting this configuration, if a specific register is designated, various instructions can be executed even with the same instruction, so that the number of instructions can be suppressed. In addition, the need for register initialization is eliminated and the number of registers used can be suppressed.

[0026]

The adder 14 of the present invention receives carry-out data written in the mask register 13 as input, in addition to the augend and addend of the vector operand, executes the addition process, and carries out the carry-out resulting from the addition result. Data is written in the mask register 13.

Since the carry-out data is stored in the mask register 13 as described above, the vector addition instruction is executed while the vector shift instruction is executed as in the prior art. It is not necessary, and the vector addition instruction can be executed at high speed with a small number of instructions.

Further, the multiplier 15 of the present invention has a function of calculating 2m-bit data which is a multiplication value of two input m-bit data. That is, in the conventional multiplier, m is obtained as a multiplication value of two input m-bit data by obtaining partial products and adding them while shifting them.
In contrast to the configuration that calculates bit data,
The multiplier 15 of the present invention has a configuration that directly calculates 2m-bit data as a multiplication value without obtaining a partial product. For example, 64-bit data and 64-bit data are multiplied to calculate 128-bit multiplication result data.

From the above, the conventional multiplier has a problem that the number of multiplications to be executed internally increases and the internal multiplier must have a function of shifting and adding partial products. The multiplier 15 can solve this.

However, when the data input to the multiplier 15 has an m-bit structure, the data input to the adder 14 also has an m-bit structure, so that the multiplier 15 outputs 2 m.
Consistency cannot be maintained by outputting bit data. The multiplier 15 of the present invention copes with this by adopting a configuration having a selector that selects and outputs either the upper m-bit data or the lower m-bit data of the multiplication value in response to the instruction. are doing.

[0031]

EXAMPLES The present invention will be described in detail below with reference to examples. As described with reference to FIG. 1, the adder 14 of the present invention executes an addition process by using the carry-out data written in the mask register 13 as an input, in addition to the augend and the addend of the vector operand, and performs the addition. The carry-out data generated as a result is written in the mask register 13.

That is, as shown in FIG. 2, the augend read from the vector register 12 and the vector register 1
The addend to be read from 2 and the carry-out data to be read from the mask register 13 are input, the addition processing is executed, the addition value is written to the vector register 12, and the carry-out data generated by the addition processing is written to the mask register. That is, the configuration of writing in 13 is adopted.

Since the carry-out data read from the mask register 13 is 1-bit data, this addition processing can be realized by a simple hardware configuration.

On the other hand, as described with reference to FIG. 1, the multiplier 15 of the present invention has a function of calculating 2m-bit data which is a multiplication value of two input m-bit data, and responds to an instruction. , And a configuration having a selector for selecting and outputting either the upper m-bit data or the lower m-bit data of the multiplication value.

That is, as shown in FIG. 3, the m-bit multiplicand read from the vector register 12 and the m-bit multiplier read from the vector register 12 are used as inputs to execute the multiplication process, and the multiplication value of 2 m bits is calculated. The configuration is such that it has a selector that latches data and, in response to an instruction, selects and outputs either the upper m-bit data or the lower m-bit data of the multiplication value.

Next, the vector addition processing executed using the adder 14 of the present invention will be described by taking the addition processing of the 160-bit augend and the 160-bit addend as an example. When the adder 14 executes addition processing of 64 bits, as shown in FIG. 10, a register for the augend, which is composed of three registers of 64 bits (vr00, vr01, vr02), and a 64-bit Three registers (vr03,
and a register for addend consisting of vr04, vr05), and stores the 160-bit addend in the register for addend according to the format shown in FIG. 4, that is, the format illustrated in FIG. At the same time, the 160-bit addend is stored in the addend register.

By issuing the vector instruction sequence shown in FIG. 6, the addition process of the 160-bit augend and the 160-bit augend is executed. Here, "VAC vr1, vr2, mr1, vr3, mr
2 ”is the vector register vr1 and the vector register vr2
Is a vector addition instruction to store the addition result of the mask register mr1 in the vector register vr3 and the carry-out data generated at that time in the mask register mr2.

That is, according to the vector instruction sequence shown in FIG. 6, first, according to the vector addition instruction VAC of (1), the augend part of the vector register vr02, the addend part of the vector register vr05, and the initial value are set as initial values. The data stored in the mask register mr00 that stores a zero value is added and stored in the vector register vr08, and the carry-out data of the carry value generated at this time is stored in the mask register mr01.

Then, according to the vector addition instruction VAC of (2), the augend part of the vector register vr01, the addend part of the vector register vr04, and the mask register mr.
The carry-out data stored in 01 is added and stored in the vector register vr07, and the carry-out data of the carry value generated at this time is stored in the mask register mr02.

Finally, according to the vector addition instruction VAC of (3), the augend part of the vector register vr00, the addend part of the vector register vr03, and the mask register mr.
The carry-out data stored in 02 is added and stored in the vector register vr06, and the carry-out data of the carry value generated at this time is stored in the mask register mr00.

As described above, in the vector processing device 1 using the adder 14 of the present invention, as shown in FIG. 7, while using the mask registers mr00, 01, 02, three vector addition instructions are issued. , 160-bit addend and 160-bit addend can be calculated. On the other hand, according to the conventional technique, 11 vector addition instructions / vector shift instructions must be issued as described with reference to FIG.

Next, the vector multiplication processing executed by using the multiplier 15 of the present invention will be described. As shown in FIG. 8, quadruple precision data has a 112-bit mantissa. Therefore, in the quadruple precision multiplication process, it is necessary to execute the operand multiplication process shown in FIG. 9 in order to obtain the mantissa of the multiplication result.

Now, the vector multiplication processing executed by using the multiplier 15 of the present invention will be described by taking the multiplication processing of the 128-bit multiplicand and the 128-bit multiplier as an example.

When the multiplier 15 executes a multiplication process of 64 bits, as shown in FIG. 10, a 128-bit multiplicand register (the upper 64-bit portion is "0").
1 ", the lower 64 bits are represented by" 02 ")
And a 128-bit multiplier register (the upper 64-bit part is represented by “03” and the lower 64-bit part is represented by “04”), and the multiplicand register of the 128-bit multiplicand (upper 64 bits) is prepared. The part stores A1 and the lower 64 bit part is represented by A2), and a multiplier of 128 bits is stored in the multiplier register (the upper 64 bit part is represented by B1 and the lower 64 bit part is represented by B2).
To store.

By issuing the vector instruction sequence shown in FIG. 11, the multiplication process of the 128-bit multiplicand and the 128-bit multiplier is executed according to the multiplication process illustrated in FIG. Here, “VML vr1, vr2, vr3” is the vector register vr1 and the vector register vr2.
The lower 64 bits of the multiplication result with and are vector register vr
3 is a vector multiplication instruction to store in "3", and "VMU vr1, vr2, vr3" are vector registers vr1 and vr2.
The upper 64 bits of the multiplication result with and are vector register vr
3 is a vector multiplication instruction to store the data in “VAC vr1, vr2, mr1, vr3, mr.
2 ”is the vector register vr1 and the vector register vr2
Is a vector addition instruction to store the addition result of the mask register mr1 in the vector register vr3 and the carry-out data generated at that time in the mask register mr2.

That is, according to the vector instruction sequence shown in FIG. 11, first, according to the vector multiplication instruction VML of (1), the multiplicand portion A2 of the vector register vr02 and the multiplier portion B2 of the vector register vr04 are multiplied, The lower 64-bit A2B2L of the multiplication result output by controlling the selector of the multiplier 15 is stored in the vector register vr23.

Then, according to the vector multiplication instruction VMU of (2), the multiplicand part A2 of the vector register vr02 and
Multiplying with the multiplier part B2 of the vector register vr04,
The upper 64-bit A2B2U of the multiplication result output by controlling the selector of the multiplier 15 is stored in the vector register vr05.

Then, according to the vector multiplication instruction VML of (3), the multiplicand part A1 of the vector register vr01 and
Multiplying with the multiplier part B2 of the vector register vr04,
The lower 64-bit A1B2L of the multiplication result output by controlling the selector of the multiplier 15 is stored in the vector register vr06.

Then, according to the vector addition instruction VAC of (4), A2B2 stored in the vector register vr05.
U and A1B2L stored in the vector register vr06
And a mask register mr that stores a zero value as an initial value
The stored data of 00 is added and stored in the vector register vr07, and the carry-out data of the carry value generated at this time is stored in the mask register mr01.

Then, according to the vector multiplication instruction VML in (5), the multiplicand part A2 of the vector register vr02 and
Multiply by the multiplier part B1 of the vector register vr03,
The lower 64-bit A2B1L of the multiplication result output by controlling the selector of the multiplier 15 is stored in the vector register vr08.

Then, according to the vector addition instruction VAC of (6), the storage data of the vector register vr07, A2B1L stored in the vector register vr08, and the storage data of the mask register mr00 storing a zero value as an initial value are stored. The carry value is added and stored in the vector register vr22, and the carry-out data of the carry value generated at this time is stored in the mask register mr02.

Subsequently, according to the vector multiplication instruction VMU of (7), the multiplicand part A1 of the vector register vr01 and
Multiplying with the multiplier part B2 of the vector register vr04,
The upper 64-bit A1B2U of the multiplication result output by controlling the selector of the multiplier 15 is stored in the vector register vr10.

Subsequently, according to the vector multiplication instruction VMU of (8), the multiplicand part A2 of the vector register vr02 and
Multiply by the multiplier part B1 of the vector register vr03,
The upper 64-bit A2B1U of the multiplication result output by controlling the selector of the multiplier 15 is stored in the vector register vr11.

Then, according to the vector addition instruction VAC of (9), A1B2 stored in the vector register vr10.
U and A2B1U stored in the vector register vr11
And carry-out data stored in the mask register mr01 are added and stored in the vector register vr12, and carry-out data of the carry value generated at this time is stored in the mask register mr00.

Then, according to the vector multiplication instruction VML in (10), the multiplicand part A1 of the vector register vr01 and
Multiply by the multiplier part B1 of the vector register vr03,
The lower 64-bit A1B1L of the multiplication result output by controlling the selector of the multiplier 15 is stored in the vector register vr13.

Then, according to the vector addition instruction VAC of (11), the data stored in the vector register vr12, the A1B1L stored in the vector register vr13, and the carry-out data stored in the mask register mr02 are added to obtain the vector. Stored in register vr21,
The carry-out data of the carry value generated at this time is stored in the mask register mr03.

Then, according to the vector multiplication instruction VMU of (12), the multiplicand part A1 of the vector register vr01 and
Multiply by the multiplier part B1 of the vector register vr03,
The upper 64-bit A1B1U of the multiplication result output by controlling the selector of the multiplier 15 is stored in the vector register vr15.

Finally, according to the vector addition instruction VAC of (13), the data stored in the mask register vr00 that stores a zero value as the initial value, A1B1U stored in the vector register vr15, and the carry stored in the mask register mr03. The out data is added and stored in the vector register vr20, and the carry out data of the carry value generated at this time is stored in the mask register mr00.

As described above, in the vector processing device 1 using the multiplier 15 of the present invention, the high-order 64 bits or the low-order 64 bits of the 128-bit multiplication result obtained by the 64-bit multiplication process are taken out while Using the adder 14 of the invention, the 128-bit multiplicand and 128
The multiplication value with the bit multiplier is calculated.

With this configuration, it is not necessary to store a zero value in the mask register mr00 or the vector register vr00, and when such a register number is designated, a zero value is designated for input. You may take the structure that you consider to be. Further, the carry-out data written to mr00 is not actually used later.
From this, when such a register number is designated, a configuration may be adopted in which the original data is not destroyed by not performing the actual writing process. Further, in the vector addition instruction VAC, five registers must be designated, but if the mask register is shared by the input and the output, the designation of four registers will suffice.

[0061]

As described above, according to the vector processing device of the present invention, since the carry-out data is stored in the mask register, the vector shift instruction is executed as in the prior art. However, there is no need to adopt the configuration of executing vector addition instructions,
The vector addition instruction can be executed at high speed with a small number of instructions.

In the multiplier of the present invention, the input 2
A selector that has a function of calculating 2m-bit data that is a multiplication value of two m-bit data and that selects and outputs either the upper m-bit data or the lower m-bit data of the multiplication value in response to an instruction. By adopting the configuration having the above, it becomes possible to solve the problems of the conventional technology, and the m-bit register of the vector processing device,
It is possible to maintain the consistency with the adder having the m-bit input specification.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is an embodiment of the adder of the present invention.

FIG. 3 is an example of a multiplier of the present invention.

FIG. 4 is an explanatory diagram of a storage process of an augend and an addend.

FIG. 5 is an explanatory diagram of a storage process of an augend and an addend.

FIG. 6 is an explanatory diagram of a vector addition instruction issued by the present invention.

FIG. 7 is an explanatory diagram of addition processing according to the present invention.

FIG. 8 is an explanatory diagram of a data format of quad precision data.

FIG. 9 is an explanatory diagram of operands of quadruple precision multiplication processing.

FIG. 10 is an explanatory diagram of a storage process of a multiplicand and a multiplier.

FIG. 11 is an explanatory diagram of a vector multiplication instruction issued by the present invention.

FIG. 12 is an explanatory diagram of a multiplication process of the present invention.

FIG. 13 is an explanatory diagram of a conventional technique.

FIG. 14 is an explanatory diagram of a conventional technique.

FIG. 15 is an explanatory diagram of a conventional technique.

FIG. 16 is an explanatory diagram of a conventional technique.

FIG. 17 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 1 Vector Processor 10 CPU 11 Vector Instruction Control Mechanism 12 Vector Register 13 Mask Register 14 Adder 15 Multiplier

Claims (7)

[Claims] 1. A vector processing device for performing vector processing, comprising at least a vector register, a mask register and an adder, wherein a mask is provided to the adder in addition to the addend and the augend of the vector operand. A vector processing device characterized by adopting a configuration for inputting register data. 2. A vector processing device, which comprises at least a vector register, a mask register, and an adder, and which executes vector processing, has a configuration in which carry-out data calculated by the adder is output to the mask register. A characteristic vector processing device. 3. A vector processing device for performing vector processing, comprising at least a vector register, a mask register, and an adder, wherein the adder has a mask in addition to the addend and the augend of the vector operand. The register data is input and the carry-out data calculated by the adder is output to the mask register. Furthermore, the same mask register for the adder input and the mask register for the adder output are used. A vector processing device characterized by adopting a configuration to be used. 4. A multiplier for calculating 2m-bit data, which is a multiplication value of two input m-bit data, wherein the upper m-bit data or the lower m-bit data of the multiplication value is generated in response to an instruction.
A multiplier characterized by having a selector that selects and outputs one of bit data. 5. In a vector processing device that includes at least a vector register, a mask register, an adder, and a multiplier and executes vector processing, as a multiplier, a multiplication value of two m-bit data to be input is obtained. In addition to calculating 2m-bit data, use one that has a selector that selects and outputs either the upper m-bit data or the lower m-bit data of the multiplication value in response to the instruction. The data output by the secreter is input as the addend and the augend, and in addition, the data of the mask register is input and the carry-out data calculated by the adder is output to the mask register. A vector processing device characterized by the above. 6. The vector processing device according to claim 5, wherein the same mask register is used as an adder input mask register and an adder output mask register. . 7. In a vector processing device comprising a vector register, a mask register, and a vector arithmetic unit for executing vector processing, a register number specified by an instruction instructing an input from the register is a specific vector register or a specific vector register. When specifying the mask register of, the register number specified by the instruction that performs input processing by treating the data from the register as a zero value and outputs to the register indicates a specific vector register or a specific mask register. In some cases, the vector processing device is characterized in that the data output process to the register is not executed.