JPH08241248A - Cache memory consistency holding method and information processor - Google Patents

Abstract

PURPOSE: To perform the write of contents held in a cache into a main storage and the update processing of the cache in parallel. CONSTITUTION: In the information processor which intermittently performs the synchronous processing to synchronize contents of the cache and those of the main storage, the cache is provided with plural cache areas 8 for data storage, and each cache area 8 is provided with a cache memory 10, where data is stored in item units based on item state data indicating the state of each item, and a controller 9 which controls the cache memory 10 by items. One cache area 8 is used to write the change contents in the main storage, and the other cache areas are used for the change of contents of the cache which is executed during the processing of write of change contents to the main storage, thus performing the synchronous processing and the update processing of the cache in parallel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a cache, which performs a process of writing the contents of a changed cache to a main memory only under a certain condition.

[0002]

2. Description of the Related Art Conventionally, in an information processing apparatus having a cache, as a method of synchronizing the contents stored in the cache and the main memory, firstly, normally, only the cache is updated, and a certain condition is satisfied. A control method for intermittently synchronizing the contents of the cache and the main memory only below;
There is a control method for always synchronizing the contents of the cache and the main memory.

In the first control method, the conditions for intermittently synchronizing the contents of the cache and the main memory are that there is a request to hold data in the cache beyond the capacity that can be held in the cache, It is provided to restart the processing when a request to change the cache content for the same area is made by another data processing unit in the processor configuration or when a failure occurs in the information processing apparatus that requires high reliability. Under the control of holding the state of the data processing unit at the time point in the main memory including the cache,
Examples include a request for synchronizing the contents of the cache and the main memory.

The first control method reduces the number of times of writing to the main memory when there is an item that is frequently updated in the cache, as compared with the second control method in which the cache and the main memory are always synchronized. Since the time for writing to the main memory can be shortened, the performance of the information processing device is improved.

[0005]

In the conventional method, when it becomes necessary to synchronize the cache with the main memory, all the necessary items in the cache must be updated to the main memory before a new cache is created. Unable to start the operation to.

Therefore, the data processing unit that operates the cache cannot perform any processing until the synchronization processing is completed. In particular, when the cache and the main memory are frequently synchronized with each other, the performance of the information processing apparatus is significantly deteriorated.

The present invention has been made in consideration of the above circumstances, and in an information processing apparatus for intermittently performing the processing for synchronizing the contents of the cache and the main memory only under a certain condition, (EN) A cache memory coherency holding method capable of improving the performance of an information processing apparatus by enabling writing of held contents to a main memory and updating processing to a cache in parallel. The purpose is to

[0008]

[Means and Actions for Solving the Problems]

(1) Two or more cache areas are held for each data processing unit, and these are connected by a communication path capable of efficient broadcast communication such as bus connection. One of the two or more cache areas is a positive cache area, and the other cache areas are secondary cache areas. Items are updated in all cache areas at the same time. However, in the positive cache area, a flag indicating that this cache item has been updated along with the data update is set,
This flag is not set in other cache areas. By not setting the flag indicating that the update was done in the cache area other than the positive cache area,
When these areas are later used as a positive cache area, unnecessary writing to the main memory is prohibited when it becomes necessary to synchronize the contents of the cache and the main memory. Each time the process of writing the contents of the cache to the main memory is performed, the cache area is circularly used while allocating a positive cache area.

In the following, the cache area being synchronized refers to the cache area under the processing for synchronizing the contents of the cache and the main memory. When it becomes necessary to synchronize the contents of the cache and main memory,
The positive cache area is set as the synchronizing cache area, and the processing of writing the updated cache contents to the main memory is started. A cache area that has been assigned as a secondary cache area in the order of the next positive cache area in the circular order is defined as a positive cache area. In the cache area during synchronization, items in the cache that were updated after the start of synchronization processing were updated to enable them when the processing of writing the updated cache contents to main memory was completed. A flag indicating invalidation of a cache item which is ignored during the process of writing the contents of the cache to the main memory is set. When the processing of writing the contents of the updated cache to the main memory is completed, the cache area that is being synced will actually see the items for which the flag indicating the invalidation of cache items that are ignored during synchronization is set. Then, the cache area that was the synchronizing cache area is set as a secondary cache area, and writing to this cache area is resumed simultaneously with other secondary cache areas.

When the process of synchronizing the contents of the cache and the main memory is started, the contents of the cache are written to the main memory in a cache area other than the positive cache area, so that the update is updated. Check whether there is any item that could not be processed, and if there is, copy all the corresponding items in the positive cache area to the corresponding items in the non-positive cache area, and then start the synchronization process. To do. As a result, the cache area which becomes the next positive cache area can hold the latest cache state.

As described above, when the process of synchronizing the contents of the cache and the main memory is needed, the process waits until the process of newly updating the cache is started until the process of synchronizing the contents is completed. There is no need, and the time can be shortened by starting a new cache update immediately.

Further, in the case where the cache area holds an item which has not been updated due to the reason that the cache content which has been updated in the past is being written to the main memory, or the like. , When there are multiple cache areas, the item is updated again after the processing of writing the cache contents to the main memory is finished, and the new update contents are reflected, and the data in other cache areas are Reduces the likelihood of duplication.

(2) In the above (1), the following points are changed. In the cache area during synchronization, a flag indicating that the item has been changed has been set for the cache item that has been updated after the synchronization process has started, and it is necessary to write to the main memory by the synchronization process. Only when it is an item, while performing the process of writing the updated cache contents to the main memory so that it becomes effective when the process of writing the updated cache contents to the main memory is completed. Sets a flag indicating invalidation of ignored cache items. If the flag indicating that the item has been changed is not set, the item is changed as in the sub cache area.

As described above, in the cache area being synchronized, when updating the cache, the cache area being synchronized was updated to the cache when the cache area being synchronized was a positive cache area. For items that are not items that need to be written to the main memory because they are items, it is possible to perform the same processing as for the sub cache area. This enables speeding up.

Further, after the synchronous process is completed, it is necessary to copy the items that are not held because the process of writing the updated cache contents to the main memory is performed from another cache area. According to the second aspect, it is not necessary to copy the items that have not been changed before the start of the synchronization processing. This makes it possible to start the synchronization processing earlier than (1).

(3) With the above-mentioned configuration (1) or (2), before the processing of synchronizing the contents of the cache and the main memory is completed, the processing of further synchronizing the contents of the cache and the main memory. When it becomes necessary and there is one or more secondary cache areas, first, the next cache area in the circular allocation order of the positive cache areas is set as the positive cache area. For the cache area that was positive until now, when the cache is updated, the same processing as the processing for the synchronizing cache area except the processing of writing the updated item to the main memory Do. This processing is performed until the cache area, which is currently performing the processing for synchronizing the contents of the cache and the main memory with respect to the cache area which has been positive until now, completes the synchronization processing. Hereinafter, the above-described processing for the cache area that has been positive until now is referred to as synchronization waiting processing, and the cache area performing the synchronization waiting processing is referred to as the synchronization waiting cache area. After the synchronous cache area finishes the synchronous processing, the synchronous cache area is used as the synchronous cache area, and the processing for synchronizing the cache and the main memory is started. Here, it was set during the process of waiting for synchronization,
The invalidation flag, which is ignored until the process of writing the updated cache contents to the main memory is completed, is treated in the same way as that set in the process of synchronizing.

When the process of synchronizing the contents of the cache and the main memory is required before the process of synchronizing the contents of the cache and the main memory is completed, and the sub cache area does not exist. Stops updating the cache until the process of synchronizing the contents of the cache and the main memory is completed.

In particular, when expanding the methods (1) and (2),
When starting the process of synchronizing the contents of the cache and the main memory, and when starting the process of waiting for the synchronization, the cache area, which becomes the next positive cache area in the circular allocation order, is previously stored. It is checked whether or not there is an item that cannot be updated because either the process of synchronizing the contents of the cache and the main memory or the process of waiting for synchronization is being performed. If such an item exists, the corresponding item in the positive cache area is simultaneously copied to the corresponding item in all the sub cache areas, and then the synchronization process is started. As a result, the next positive cache area can hold the latest cache state. Copying to items that correspond to all of the sub cache areas is performed because the cache area that has items that meet this condition in the sub cache area is the cache area that should be the next positive. This is because it is the cache area that has been subjected to the synchronization waiting process at that time, and further coincides with the cache area that should become positive after the next. As a result, it is possible to prevent copying of the cache contents, which is required thereafter.

As described above, it becomes possible to simultaneously control the processing of synchronizing the contents of the cache and the main memory by the number obtained by subtracting 1 from the number of cache areas provided, and within the limit of the number of cache areas. , The cache and the main memory can be synchronized without stopping the operation to the cache.

Further, when the method (2) is adopted, not only the cache area in synchronization but also the cache area waiting for synchronization can be applied to the items which do not need to be written to the main memory when updating to the cache. Has the feature of simplifying the processing.

(4) With the configuration of (3), the maximum number of items held in the cache area that directly reflects the update of the cache is the maximum number of items that can be physically held in the cache. Replace with a cache control that keeps the number of items to half or less. That is, in order to maintain the same cache capacity as (3), the physical capacity of each cache area must be doubled or more.

After the process of synchronizing the contents of the cache with the main memory is started, the contents of the cache that have been updated are updated to the cache area being synchronized when a change to the cache occurs. While writing to the main memory, set a flag indicating invalidation of cache items that are ignored, and at the same time, use the physical maximum amount of the cache area as an upper limit and perform it on other sub cache areas. Make the same changes that you make to the items listed.

As described above, the cache update can be accepted even in the synchronized cache area, and all the cache areas can individually hold the latest cache contents. As a result, when starting the process of synchronizing the cache contents with the main memory,
(1) To eliminate the time delay due to the process of checking whether the latest cache contents need to be copied from another cache area and the actual copying process that may occur in (2) and (3). You can Also, since it is not necessary to copy to the next positive cache area required in (3),
Even if there is no sub cache area, it is possible to put the positive cache area into a state of waiting for the processing of synchronizing the cache contents and the main memory.

(5) Hereinafter, the process in which the secondary cache area reflects the update to the cache in its own cache area is called normal writing, and the processing in which the synchronizing cache area receives the contents of the update is called extended writing. I will decide. With the configuration of (3), an expanded cache memory having the same capacity is provided in each cache area. The control unit of the cache area can specify for each item in the cache area whether to use the original cache memory or the extended cache memory for normal writing or extended writing. Shall be

In the synchronizing cache area, the cache memory designated for normal writing is used to write the updated item to the main memory and the updated cache content to the main memory. During the writing process, a process of setting a flag indicating invalidation that is ignored is performed. The cache memory designated for extended writing is used to update the cache. After the process of writing the updated cache contents to the main memory is completed, while the process of writing the updated cache contents to the main memory is ignored, for items having a flag indicating invalidation, The flag is used to actually invalidate, and the assignment of roles for normal writing and extended writing for the item is exchanged.

As described above, the cache update can be accepted even in the cache area being synchronized, and all the cache areas can individually hold the latest cache contents. As a result, when starting the process of synchronizing the cache contents with the main memory,
(1) To eliminate the time delay due to the process of checking whether the latest cache contents need to be copied from another cache area and the actual copying process that may occur in (2) and (3). You can Also, since it is not necessary to copy to the next positive cache area required in (3),
Even if there is no sub cache area, it is possible to put the positive cache area into a state of waiting for the processing of synchronizing the cache contents and the main memory.

Furthermore, in all cache areas,
Since it is actually guaranteed that the positions of the items in the cache are the same, it is not necessary to specify the position of each item when updating the cache areas. As a result, the time delay required for confirming the physical position of each cache area when performing the processing for the cache, which occurs in (4), can be eliminated.

[0028]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of the configuration of an information processing apparatus to which the present invention is applied. As shown in FIG. 1, the information processing apparatus includes a data processing unit (processor element: PE) 1 connected to a main memory (memory element: ME) 3 via a communication path 2. The data processing unit 1 reads data from the main memory 3, processes the data, and writes the data to the main memory 3.

FIG. 2 shows the configuration of the data processing unit 1. The data processing unit 1 includes a data processing device (CPU) 4 and a cache 5. The cache 5 stores the data read from the main memory 3 by the data processing device 4. The data processing device 4 performs data processing on the data stored in the cache 5.

FIG. 3 shows the structure of the cache 5. In the cache 5, as shown in FIG. 3, the cache controller 6 uses a plurality of cache area units (cache segments) via a communication path 7 in the cache 5.
8-1, 8-2, 8-3, 8-4 is connected and comprised. The communication path 7 in the cache 5 is capable of broadcast communication, and the data fetched from the outside of the cache 5 is simultaneously cached in a plurality of cache area sections 8-1, 8-2, 8-3, 8-.
4, and the cache area parts 8-1, 8-2,
Data is transferred between 8-3 and 8-4. It is assumed that the cache area units 8-1, 8-2, 8-3, and 8-4 are annularly assigned to the order. That is, when one of the cache area parts is set as the positive cache area, the other cache area parts are set as the sub cache area parts, and the synchronization processing for writing the contents of the cache 5 to the main memory 3 is performed. The positive cache area portion becomes in synchronization, and the cache area portion in the next order is assigned to the new positive cache area portion.

FIG. 4 shows the cache area section 8-k (k = 1.
4 to 4). The cache area unit 8-k includes a controller 9 and a cache memory 10. The controller 9 controls the cache memory 10 on the basis of data (hereinafter, item state data) indicating a state of each item of the cache memory 10 managed in the cache controller 6 for each of a plurality of items (blocks).

FIG. 5 shows the data structure of data indicating the state of each cache area portion 8-k in the cache 5 (hereinafter, cache area portion state data). The cache area section state data includes the cache area sections 8-1, 8-2,
It is placed in the controller 6 that controls 8-3 and 8-4.
The cache area portion state data is provided with 2 bits corresponding to each cache area portion, and "00" indicates that it is a positive cache area portion, and "01" indicates that it is a synchronizing cache area portion. It is assumed that "10" is a cache area portion (used in the third, fourth, and fifth embodiments) waiting for synchronization.

The flag indicating the positive cache area portion and the flag indicating the synchronized cache area portion are set to only one cache area portion at the same time. The data structure of the cache area part state data described above is an example, and other data structures may be used as long as they can represent three states.

FIG. 6 shows the data structure of item state data (cache tag) indicating the state of one item (cache block) in the cache memory 10. The item state data is provided corresponding to each of the plurality of items in the cache memory 10 of each cache area unit 8-k, and is placed in the controller 6. Item status data includes
A physical address 16 on the main memory 3 of the data held by the corresponding item exists corresponding to each cache area unit 8-k. Also, a flag 17 (hereinafter referred to as an invalid flag) indicating that the content of the item is invalid and a synchronous process of writing the updated cache content to the main memory 3 are associated with each cache area unit 8-k. A flag 18 indicating that the content of the item is invalid (hereinafter referred to as an invalid flag after synchronization) and a flag 19 indicating that the content of the item is changed (hereinafter referred to as an update flag) are provided. Has been. The items for which the post-synchronization invalid flag 18 is set are not changed when the processing request for changing the cache contents is issued during the synchronization process (the contents to be written in the main memory 3 are continuously held), and the synchronization process is performed. It is later invalidated because the contents have not been changed.

FIG. 7 and FIG. 8 show the contents of the processing when reading and writing to the main memory 3 using the cache 5. At a predetermined processing stage in FIG. 7, the processing having the contents shown in FIG. 8 is executed. In FIG. 8, the state of each cache area 8-k (primary, secondary, synchronizing, waiting for synchronization) and the type of operation to the main memory 3 using the cache 5 (writing, reading, invalidation of items). , Specific processing is shown. That is, for each combination of the cache area part and the type of operation, the presence or absence of the operation of the address in the item status data, the presence or absence of the operation of the content of the corresponding item, and the operation (set, reset) of various flags in the item status data. )It is shown. Note that the write processing and the item invalidation processing when the cache area is in synchronization and waiting for synchronization indicate the operation when the update flag is set, and when the update flag is not set, , And the processing for the sub cache area portion in each operation type.

The process for synchronizing the contents of the cache and the main memory (flashback process) performed in FIG.
This is realized by the procedure shown in the flowchart of FIG. 9 in the first embodiment, and realized by the procedure shown in the flowchart of FIG. 10 in the second, third, and fourth embodiments.

(A) Next, the operation of the first embodiment of the present invention will be described. The reading / writing process to / from the main memory 3 using the cache 5 can be realized by the procedure shown in the flowchart of FIG. 7.

The address 16, invalid flag 17, post-synchronization invalid flag 18, and update flag 19 in each cache area portion
8 is performed according to the relationship shown in FIG. 8 (however, in the case of waiting for synchronization in FIG. 8, it is used for explaining the third and fourth embodiments).

First, when the data processing unit 1 performs a read / write process with respect to data stored at a position indicated by a physical address in the main memory 3, the target physical address output from the data processing device 4 is set to the target physical address. First, it is checked whether or not the cache 5 holds data at a necessary address (step A1).

That is, first, the cache controller 6 of the cache 5 refers to the cache area portion state data indicating the state of each cache area portion 8-k, and determines the cache area portion currently assigned to the positive cache area portion. Determine. Then, the controller 6 refers to the physical address 16 on the main memory 3 stored in the item state data of the cache area portion currently assigned to the positive cache area portion for all items, and obtains the physical address It is checked whether or not the item corresponding to exists in the cache memory 10.

If there is an item corresponding to the desired physical address and the processing request from the data processing device 4 is a read process (steps A1 and A2), it is stored in the cache memory 10 of the positive cache area portion. The data of the corresponding item is taken out and transferred to the data processing device 4 (step A3). Here, the update flag 19 of the item status data corresponding to the applicable item is not set in any of the primary and secondary cache area parts together with other flags (processing of reading <hit> shown in FIG. 8).

On the other hand, in the case of the writing process (step A2), the cache controller 6 causes the cache 5
By the broadcast communication via the communication path 7 inside, the write processing is simultaneously requested to each cache area unit 8-k (update contents are transmitted). The cache controller 9 of each cache area unit 8-k corresponds to the cache memory 10 when it is a primary or secondary cache area unit according to the state of its own cache area unit set in the cache area unit state data. A writing process (writing <hit> process shown in FIG. 8) is performed on the item (step A4).

That is, the controller 9 in the positive cache area section writes the corresponding item in the cache memory 10, and the controller 9 in the sub cache area section writes the corresponding item in the cache memory 10. The cache controller 6 sets a flag corresponding to the positive cache area portion in the update flag 19 of the cache area portion state data of the same item, resets the invalid flag 17, and invalid flag corresponding to the secondary cache area portion. Reset 17.

By not setting the update flag for the sub cache area part, when the sub cache area is later used as a positive cache area, the contents stored in the cache 5 and the main memory 3 are synchronized. When it is necessary to take (in the case of synchronous processing), the unnecessary main memory 3 already written back by the previous positive cache area part 3
Writing to can be prohibited.

When there is a cache area in synchronization when a write processing request is made, that is, a synchronous processing (flashback processing) for writing back the changed contents in the cache 5 to the main memory 3 is executed. If
The following processing is performed on the cache area portion during synchronization. (Synchronous processing and writing processing to the cache 5 are performed in parallel).

With respect to the cache area portion being synchronized, the post-synchronization invalid flag 18 is set for all items corresponding to the item status data changed after the start of the synchronization processing.
The flag corresponding to the cache area portion in synchronization with is set. Since the post-synchronization invalid flag 18 is set, it is ignored while the synchronization processing is being performed. Therefore, even if a new update is made to an item that has not been updated before the synchronization processing is started, the content is changed. Without affecting the synchronization process.

On the other hand, if the item corresponding to the desired physical address does not exist (step A1), the invalid flag is referred to by referring to the item state data over all items in the positive cache area section indicated by the cache area state section data. It is checked whether or not there is an item for which 17 is set (step A5). If there is an item for which the invalid flag 17 is set, that is, an empty item, that item is used to store the data to be read and written (step A6). For all of the positive cache area section and the secondary cache area section, the physical address indicating the data currently being referred to is written in the item state data corresponding to the corresponding item. Regarding the update of the contents of the cache memory for each of the other cache area parts and the operation of the flag, the same processing as when the desired physical address is present is performed.

If there is no empty item in the cache memory 10 (step A5), the item whose data is to be removed from the cache memory 10 to obtain the empty item is an arbitrary algorithm (for example, LRU: Least Rece.
ntly Used method) (step A7).

When the update flag 19 is not set in the item state data in the positive cache area of the selected item (step A8), the contents of the data stored in this item are stored in the main memory 3. Since it is not necessary to reflect it, the same processing as when the invalid flag 17 is set is performed for this item.

On the other hand, when the update flag 19 is set (step A8), the synchronous processing (flashback processing) for synchronizing the contents stored in the cache 5 and the main memory 3 is started (step A8). A9).

When it is necessary to invalidate an item in the cache 5, such as when a request to hold data in the cache 5 that exceeds the capacity of the cache 5 occurs,
For the item for which invalidation is requested, invalid flag 1 corresponding to the positive cache area part and the secondary cache area part
7 is set (invalidation processing of items shown in FIG. 8).

In step A9, when the synchronization processing for synchronizing the contents stored in the cache 5 and the contents stored in the main memory 3 is requested, the flashback processing whose procedure is shown in the flowchart of FIG. 9 is performed.

First, the cache controller 6 of the cache 5 determines whether or not there is a cache area portion in synchronization (step B1). If there is a cache area part in synchronization, the process waits until there is no cache area part in synchronization, that is, until the cache area part is changed to a secondary cache area part.

When there is no cache area in synchronization,
The cache controller 6 sets an in-interpolation flag (not shown and held in the cache controller 6) to stop the operation on the cache 5, that is, prohibit access to the main memory 3 using the cache 5 ( Step B2).

The cache controller 6 refers to the cache area portion state data and checks the cache area portion corresponding to the next order of the cache area which is currently the positive cache area portion in the circular order, and the cache area portion Check whether it is a sub cache area.

If the cache area section next to the primary cache area section is not the sub cache area section, the operation of the cache is kept suspended until this cache area section becomes the sub cache area section.

When the cache area section next to the positive cache area section is the sub cache area section, first,
The following process is performed to complement the contents of the area of the positive cache.

The cache controller 6 compares all the invalid flags 17 corresponding to the positive cache area portion and the next positive cache area portion of the item state data corresponding to each item, and responds to the positive cache area portion. Although the invalid flag is reset, the invalid flag corresponding to the next positive cache area portion determines all the items that are set.

Then, the contents of the corresponding item in the cache memory 10 of the positive cache area portion are copied to the corresponding item of the cache memory 10 corresponding to the next positive cache area portion, and the next positive item of the item is copied. The invalid flag corresponding to the cache area part of is reset (step B3).

That is, there is an item that cannot be updated in the cache area portion, which is the next positive cache area portion, because the synchronization processing for previously writing back the contents of the cache memory 10 to the main memory 3 was performed. Then, by copying all the corresponding items in the positive cache area portion, the latest cache 5 content can be held in the cache area portion which will be the next positive cache area portion.

After that, the cache controller 6 resets the interpolation flag and restarts the operation on the cache 5 (step B4). Next, the contents of the cache memory 10 are reflected in the main memory 3 as follows. The cache controller 6 changes the cache area part state data so that the flag representing the positive cache area part up to that point indicates the cache area part being synchronized, and sets the flag 13 indicating the positive cache area part to
The flag corresponding to the cache area portion in the next order, which is annularly assigned, is changed to indicate the positive cache area portion (step B5).

Next, all the update flags 19 corresponding to the cache area portion (the cache processing portion which has been the positive cache area portion until that time) in synchronization with the item state data are checked,
A process of writing the contents in the cache memory 10 of the item for which the update flag 19 is set (items whose contents have been changed) to the main memory 3 according to the physical address 16 is performed (step B6).

After the processing is completed for all the items for which all the update flags 19 are set, all the post-synchronization invalid flags 18 corresponding to the cache area portion being synchronized are checked, and the post-synchronization invalid flags 18 are set. For the item, the invalid flag 17 corresponding to the cache area portion being synchronized is set, and finally, the post-synchronization invalid flag 18 is reset.

After the writing process is completed, the cache controller 6 changes the synchronizing cache area portion to the sub cache area portion, and ends the flashback processing (step B7).

After writing the contents of the changed item in the main memory 3, the item is invalidated so that the data to be read and written can be stored (step A1).
0). Here, when the processing request from the data processing device 4 is a reading process (step A11), the target data is directly read from the main memory 3, and the cache 5
In each of the primary and secondary cache areas (each cache area section 8-k), the read content is stored in the corresponding item. Then, in each cache area unit 8-k, the invalid flag is reset for the primary and secondary cache area units for the item state data corresponding to the item whose content has been changed (read <miss shown in FIG. 8
> Processing).

On the other hand, in the case of the writing process (step A11), as in the case of the reading process, the target data is directly read from the main memory 3 and the data in both the primary and secondary cache areas in the cache 5 are read. (Each cache area 8-k) stores the read content in the corresponding item. Then, in each cache area unit 8-k, with respect to the item state data corresponding to the item whose contents have been changed, the update flag is set and the invalid flag is reset for the positive cache area unit, and the sub cache area unit is reset. The invalid flag is reset (processing of write <miss> shown in FIG. 8).

In this way, the cache 5 is provided with a plurality of cache area units 8-1, 8-2, 8-3, 8-4, which are allocated to the primary and secondary sides, and under the control of the cache controller 6, The data of the same content is stored in each. And cache 5 and main memory 3
When it becomes necessary to synchronize the contents of the data with the cache memory, the positive cache area portion is used (the cache area portion being synchronized is written to the main memory 3), and the data processing device 4 receives data from the data processing device 4 during the synchronization processing. When a read / write process request is issued, the cache process is performed using another cache area that has not been synchronized.

In the cache area during the synchronous processing, the items updated after the synchronous processing is started are ignored during the synchronous processing of writing to the main memory 3 by setting the post-synchronization invalidation flag, It can be made invalid after the update process. For items whose contents have not been updated because the synchronization process was being performed, the first cache region part in the circular order is the positive cache region part, and this positive region part starts the synchronization process. At this time, since all the items that have not been updated are copied, the latest contents can be held before they are newly assigned to the positive cache area section.

From the above, when the synchronous processing is required, it is possible to immediately execute the processing in parallel without waiting for the processing for updating the contents of the cache 5 until the synchronous processing is completed. Therefore, the processing time of the entire system can be shortened.

In the above description of the first embodiment, in step A4, for items that have changed after the start of synchronization processing, the cache area portion being synchronized is flagged as invalid after synchronization in the item state data. Although the description has been given assuming that the flag corresponding to the cache area portion in synchronization with 18 is set, the following method may be used (hereinafter, referred to as another update method. Second Embodiment and Third Embodiment described later).
It shall be used in the embodiment and the fourth embodiment).

In the cache area during synchronization, the update flag 19 is referred to check whether or not the item has been updated before the synchronization processing. Only when there is an update, the cache after synchronization with the post-synchronization invalid flag 18 is cached. If the flag corresponding to the area portion is set and there is no update, the same processing as the sub cache area portion is performed.

Inhibiting the update after the synchronous processing is started in such an item is particularly effective for the positive cache area section from the other cache area section immediately before starting the synchronous processing. The method that may require copying increases the amount of copying, which is a problem. The other updating method described above can reduce such copying. (B) Next, a second embodiment will be described.

In the second embodiment, it is possible to deal with the case where further synchronization processing is required before the completion of the synchronization processing for synchronizing the contents of the cache 5 and the main memory 3 in the first embodiment. In this case, it is possible to further set the cache area part waiting for synchronization. The cache area section waiting for synchronization indicates a cache area section which becomes the next cache area section during synchronization.

The configuration of the second embodiment is the same as the first embodiment described above.
The same as in the embodiment. The read / write processing to the main memory 3 using the cache 5 can be realized by the method shown in FIG. Further, it is assumed that the other updating method described above is used.

In the second embodiment, when the data processing unit 1 uses the contents of a certain physical address in the main memory 3,
In addition to the processing in the first embodiment, the same operation as the operation of each flag corresponding to the synchronizing cache area section is performed on each item state data, and the cache area section waiting for synchronization (details will be described later). For each flag corresponding to. Further, when it becomes necessary to invalidate the contents of the cache 5, the same processing as that in the synchronizing cache area portion is performed for the synchronizing cache area portion in addition to the processing in the first embodiment.

When a process for synchronizing the contents of the cache 5 and the main memory 3 is requested, the process (flashback process) shown in the flowchart of FIG. 10 is performed in the second embodiment. When a process of synchronizing the contents of the cache 5 and the main memory 3 is requested, first, the cache controller 6 of the cache 5 determines whether the cache area part next to the positive cache area part is the sub cache area part. Is checked (step C1). Here, if there is no secondary cache area portion, it waits until the synchronizing cache area portion completes the synchronization processing and becomes the secondary cache area portion.

When the cache area portion being synchronized becomes the secondary cache area portion, the cache controller 6 sets an interpolation flag (not shown and held in the cache controller 6) to operate the cache 5. Stop,
That is, access to the main memory 3 using the cache 5 is prohibited (step C2).

When the cache area section next to the positive cache area section is the sub cache area section, first,
The following process is performed to complement the contents of the next positive cache area (secondary cache area portion).

In the item state data corresponding to each item, all invalid flags 17 corresponding to the positive cache area portion and the next positive cache area portion are compared, and the invalid flag corresponding to the positive cache area portion is reset. However, the invalid flag corresponding to the next positive cache area portion discriminates all the items that are set. Then, the content of the corresponding item in the cache memory 10 of the positive cache area portion is copied to the item corresponding to the next positive cache area portion, and the invalid flag corresponding to the next positive cache area portion of the item is copied. Is reset (Step C
3).

In other words, the cache area portion, which is the next positive cache area portion, has been previously subjected to either the synchronous processing for writing back the contents of the cache memory 10 to the main memory 3 or the synchronous waiting processing. If there is an item that could not be created, the corresponding item in the positive cache area section is copied to the corresponding item in the sub cache area section.

At this time, copying is simultaneously performed on all the sub cache area portions. As a result, the latest contents of the cache 5 can be held in the cache area portion which becomes positive next. Copying to items that correspond to all of the secondary cache area part is performed by synchronizing the cache area part that has the item that meets this condition in the secondary cache area part and the cache area part that should become positive next time. This is because it is the cache area that was in the process of waiting for synchronization when performing the above process, and further matches the cache area part that should be positive after the next time.

Thereafter, the in-interpolation flag is reset and the operation on the cache 5 is restarted (step C4). Next, the cache controller 6 refers to the cache area portion state data to check whether there is a cache area portion that is being synchronized (step C5).

If there is a cache area part in synchronization,
The flag 15 indicating the cache area portion waiting for synchronization of the cache area portion state data is set so that the cache area portion, which is currently the positive cache area portion, becomes the cache flag area waiting for synchronization, and the circular order is set. The cache area part corresponding to the next positive cache area part is
The flag 13 is set so as to become a new positive cache area portion (step C7).

Here, the cache controller 6 refers to the cache area portion state data to check whether there is a cache area portion in synchronization (step C8). That is, the cache controller 6 waits for the currently synchronized cache area unit to be changed to the sub cache area unit.

When the cache area portion being synchronized is changed to the sub cache area portion, the cache controller 6
If the next cache area in the circular order is the cache area waiting for the synchronization, the flag 1 indicating the cache area waiting for the synchronization is sent to this cache area.
5 is reset, and the flag 14 is set so as to indicate the cache area portion being synchronized (step C9).

On the other hand, in step C5, if there is no cache area section in synchronization, the cache controller 6 sets the cache area section state data to the cache area in synchronization with the flag representing the positive cache area section until then. The flag 13 indicating the positive cache area portion is changed, and the flag corresponding to the next cache area portion allocated in a ring shape is changed to indicate the positive cache area portion (step C
6).

For the cache waiting area for synchronization, which has been the positive cache area until now, the same processing as the processing for the synchronizing cache area, that is, the item that has been updated after the start of the synchronization processing is performed. The post-synchronization invalidation flag is set so that it is ignored during the synchronous processing of writing to the main memory 3 (the cache area portion during synchronization is the update of the cache 5 when the update is performed to the cache 5). The process of writing the existing items to the main memory 3 is different). The cache area waiting for synchronization performs the above processing.
The process is performed until the synchronization process by the cache area unit being synchronized is completed.

Next, all update flags 19 corresponding to the cache area portion (the cache processing portion which has been the positive cache area portion until that time) in synchronization with the item state data are checked,
The contents of the item (item whose contents have been changed) in which the update flag 19 is set in the cache memory 10 are written into the main memory 3 according to the physical address 16 (step C10).

After the synchronizing cache area portion completes the synchronization processing, the flag 14 indicating the synchronizing cache area portion corresponding to the same cache area portion is reset and set to become the sub cache area portion ( Step C1
1).

The post-synchronization invalid flag set during the processing waiting for the synchronization is treated in the same manner as the post-synchronization invalid flag set in the cache area during synchronization. In this way, in addition to the effect of the first embodiment, it is possible to further provide a cache area section that is waiting for synchronization, so that when there is a cache area section that is in synchronization, further synchronization processing is required. You can also deal with it. At this time, it is possible to simultaneously control the synchronous processing within the limit of the number of cache area parts provided in the cache 5 (the number obtained by subtracting 1 from the total number), and stop the operation to the cache 5. Instead, the cache 5 and the main memory 3 can be synchronized.

Further, by using the other updating method in the first embodiment, not only the cache area portion in synchronization but also the cache area portion waiting for synchronization is updated when it is a positive cache area portion. For items that are not filled, the same process as for the sub cache area can be performed. (C) Next, a third embodiment will be described.

In the third embodiment, the cache memory 10 in each of the cache areas 8-1, 8-2, 8-3 and 8-4 in the second embodiment is divided into two areas, and each area is divided into two areas. It can be controlled.

The structure of the third embodiment is similar to that of the second embodiment.
The same as the embodiment (however, the cache area unit 8
Controller 9 for cache memory 10 in -k
Control by different). Further, the read / write processing to the main memory 3 using the cache 5 can be realized by the method shown in FIG. Further, when the processing for synchronizing the contents of the cache 5 and the main memory 3 is requested, the processing shown in FIG. 10 is performed to perform the processing for synchronization (however, the processing of step C3 is unnecessary).

The controller 9 uses the cache memory 10
The maximum number of items in which the update of the cache 5 is directly reflected is controlled to be half or less of the maximum number of items that can be physically held in the cache memory 10. (Therefore, in order to maintain the same cache capacity as the configuration of the second embodiment, it is necessary to double the physical memory capacity of the cache memory 10 in each cache area section.) That is, during synchronization. The controller 9 in the cache area unit stores the updated contents in the main memory when the change to the cache 5 occurs after the synchronization process is started for one of the areas of the cache memory 10 to be divided and used. The post-synchronization invalid flag, which is set to be ignored during the process of writing to 3, is set corresponding to the corresponding item, and the upper limit of the physical maximum amount of the cache memory 10 for the other area is set. Using as
The same change as the item change made to the other sub cache area section is made.

As a result, it becomes possible to receive the update of the contents of the item even in the cache area section during synchronization, and each cache area section is the latest cache 5 by itself.
It is possible to retain the contents of.

In the third embodiment, it is not guaranteed that an item on the cache 5 has the same physical position on the cache memory 10 for each cache area. Whether or not the item corresponding to the content of the physical address of the main memory 3 to be processed exists in the cache 5 is checked by checking the item state data corresponding to all the items in each cache area section and the invalid flag. The determination is made by checking the physical addresses 20 on the main memory 3 of all the items for which 21 is not set. If it is determined that the physical address exists, the item that holds the content of the physical address is determined at the same time.

It is determined whether an item corresponding to the physical address of the main memory 3 exists in the cache 5, and the position on the cache 5 where the item corresponding to the physical address of the main memory 3 exists is found. The processing after this is the same as that of the second embodiment described above for the positive cache area portion and the secondary cache area portion.

When the item corresponding to the target physical address exists in the cache 5 and the process is a read process, the contents of the corresponding item stored in the positive cache area portion are extracted and stored in the data processing device 4. Forward.

In the case of writing processing, writing is performed in the cache memory 10 in the positive cache area portion,
The flag corresponding to the positive cache area portion of the update flag 19 of the data structure indicating the state of the cache area portion of the corresponding item is set. Regarding the sub cache area portion, only the contents are updated in the cache memory 10.
For the cache area portion in synchronization and the cache area portion waiting for synchronization, the update flag 19 is referred to check whether or not the item has been changed. If there is a change, the post-synchronization invalid flag 18 of the cache area portion being synchronized
Is set and the target item for which the invalid flag 17 is newly set, that is, the item in the other area of the cache memory 10 is searched for from the cache area section in synchronization, and a secondary cache for that item is set. The same processing as that performed on the area portion is performed. If there is no update, the same processing as the sub cache area section is performed.

In this way, when the process of synchronizing the contents of the cache 5 with the main memory 3 is started, the latest contents generated in the above-described first and second embodiments are stored in another cache. It is possible to eliminate the time delay due to the process of determining whether or not it is necessary to copy from the area portion, and the process of actually copying according to the result of the determination, and it is possible to realize higher-speed processing. Further, since copying to the next positive cache area portion required in the second embodiment is not necessary, even if there is no sub cache area portion, the positive cache area portion is cached 5 It becomes possible to wait for the synchronization between the contents of the main memory 3 and the contents of. (D) Next, a fourth embodiment will be described.

In the fourth embodiment, two cache memories are provided in each of the cache areas 8-1, 8-2, 8-3, 8-4 in the second embodiment and used for normal writing. It is possible to specify whether to use it for extended writing.

The cache area portion in the fourth embodiment is
The configuration is as shown in FIG. As shown in FIG. 11, a controller 39 and two cache memories 40a and 40b are provided in the cache area section.
The controller 39 has two cache memories 40a,
40b is controlled. Cache memory 40a, 40
One of b is used as an original cache memory and the other is used as an expansive cache memory.

FIG. 12 shows the cache memories 40a, 40.
The data structure of the item state data which shows the state of one item of b is shown. The item state data is provided corresponding to each of a plurality of items in the cache memories 40a and 40b of each cache area unit 8-k, and is placed in the controller 6. The item status data is provided with a physical address 20 of the data held by the corresponding item on the main memory 3, and a flag 21 (invalid flag) indicating that the content of the item is invalid. An address indicating the position on the physical memory of the data held by the corresponding item is provided for each cache area unit 8-k. Also, corresponding to each cache area unit 8-k,
A flag 23 (hereinafter referred to as a selection flag) indicating whether to use the original cache memory or the extended cache memory for normal writing, and a process of writing the updated cache content to the main memory 3 are performed. Flag 24 indicating that the item is invalid while
A (post-synchronization invalid flag) and a flag 25 (update flag) indicating that the content of the item has been changed are provided. The items for which the post-synchronization invalid flag 24 is set are not changed when the processing request for changing the contents of the cache is issued during the synchronization processing (the contents to be written in the main memory 3 are continuously held), and the synchronization processing is performed. It is later invalidated because the contents have not been changed.

In the fourth embodiment, the read / write processing to the main memory 3 using the cache 5 can be realized by the method shown in FIG. Further, when the processing for synchronizing the contents of the cache 5 and the main memory 3 is requested, the processing shown in FIG. 10 is performed to perform the processing for synchronization.

When the data processing device 4 performs a read / write process with respect to the data stored at the position indicated by a certain physical address in the main memory 3, the target physical address output from the data processing device 4 is used as a basis. First, it is checked whether or not the cache 5 holds data at a necessary address.

The cache controller 6 refers to all the physical addresses 20 stored in the item status data corresponding to each item of the cache 5 existing in the main memory 3, and the item corresponding to the desired physical address exists in the cache 5. Find out whether to do.

Each cache area 8-k holds two cache memories 40a and 40b as shown in FIG. The cache controller 6 refers to the selection flag 23 of the item status data corresponding to the corresponding item,
Of the normal writing and the extended writing, one cache memory indicating the normal writing is selected.

A normal write cache memory is used as a cache memory for storing changed contents in the primary and secondary cache area parts and a cache memory referred to for synchronization processing in the synchronizing cache area part. use.

When the normal write cache memory side is modified in the synchronizing cache area, the write cache memory extended as follows is used.

When it is necessary to write or invalidate an item in the cache area that is being synchronized or is waiting for synchronization, the update flag 25 is referred to and whether or not the item has been changed is checked. Find out.

If the item has been changed, the post-synchronization invalid flag 24 is set corresponding to the corresponding cache area portion of the item state data corresponding to the item, and the selection flag 23 is extended to the write cache memory. Set to indicate the side of, and for the same cache memory,
Performs the same processing as the sub cache area section. In other words, the expanded cache memory for writing holds the latest contents of the cache 5.

After the synchronization processing is completed, the invalid flag 21 is set for the item for which the post-synchronization invalid flag 24 is set.
Is set, and the selection flag 24 set to select the extended write cache memory is inverted, that is, the normal write target is exchanged with the normal write cache memory side.

If no change has been made, the same processing as the sub cache area section is performed on the side of the normal write cache memory. When it becomes necessary to invalidate an item in the cache, an invalid flag 2 that manages whether the item is invalid over the entire cache area.
Reset 1

In this way, when the process of synchronizing the contents of the cache 5 with the main memory 3 is started, the latest contents generated in the above-mentioned first and second embodiments are stored in another cache. It is possible to eliminate the time delay due to the process of determining whether or not it is necessary to copy from the area portion and the process of actually copying according to the result of the determination. Further, since copying to the next positive cache area portion required in the second embodiment is not necessary, even if there is no sub cache area portion, the positive cache area portion is cached 5 It becomes possible to wait for the synchronization between the contents of the main memory 3 and the contents of.

Furthermore, since it is guaranteed that the positions of the items of the cache 5 are actually the same in all the cache area parts 8-k, all the items are dealt with in the update processing for each cache area part. The process of determining the item position with reference to the item state data to be performed is unnecessary. This eliminates the time delay required for confirming the physical position for each cache area when performing the processing for the cache 5 in the third embodiment, and enables the processing at higher speed. can do.

[0116]

As described above in detail, according to the present invention, it is possible to write the content held in the cache to the main memory and update the cache in parallel, thereby processing information. It is possible to improve the performance of the device.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a configuration of an information processing apparatus to which the present invention is applied.

FIG. 2 is a diagram showing a configuration of a data processing unit 1 in FIG.

FIG. 3 is a diagram showing a configuration of a cache 5 in FIG.

FIG. 4 is a diagram showing a configuration of a cache area unit in FIG.

FIG. 5 is a diagram showing a data structure of data (cache area portion state data) showing a state of each cache area portion 8-k in the cache 5;

FIG. 6 is a diagram showing a data structure of item state data showing the state of one item in the cache memory 10.

FIG. 7 is a flowchart showing the contents of processing when reading / writing data from / to the main memory 3 using the cache 5 according to the present invention.

FIG. 8 is a diagram showing the state of each cache area unit 8-k and specific processing for each type of operation to the main memory 3 using the cache 5;

FIG. 9 is a flowchart showing a processing procedure when a synchronization process for synchronizing the contents stored in each of the cache 5 and the main memory 3 is requested in the first embodiment of the present invention.

FIG. 10 is a flowchart showing a processing procedure when a synchronization process for synchronizing the contents stored in the cache 5 and the contents stored in the main memory 3 is requested in the second, third, and fourth embodiments of the present invention.

FIG. 11 is a diagram showing the configuration of a cache area unit in the fourth embodiment of the present invention.

FIG. 12 is a diagram showing a data structure of item state data in the fourth example of the present invention.

[Explanation of symbols]

1 ... Data processing unit (processor element: P
E), 2 ... communication path, 3 ... main memory (memory element: M
E), 4 ... Data processing device (CPU), 5 ... Cache, 6 ... Cache controller, 7 ... Communication path, 8-
1, 8-2, 8-3, 8-4 ... Cache area section (cache segment), 9, 39 ... Controller, 10,
40a, 40b ... Cache memory, 17 ... Invalid flag, 18, 24 ... Synchronous invalid flag, 19, 25 ... Update flag, 23 ... Selection flag.

Claims (9)

[Claims] 1. A cache in an information processing device for intermittently performing a synchronization process for writing the updated contents of a cache to a main memory and synchronizing the contents of the cache and the main memory only under a certain condition. Multiplexed as two or more cache areas with the same capacity, the operation to the cache updates the contents of all cache areas at the same time, and at that time, the cache contents are written only in one cache area. Of the cache that has been updated, and for all other cache areas without leaving a trace that the contents of the cache have been updated. When there is a request for synchronous processing to write to the cache area, a cache area that leaves a trace that the content has been updated In the cache area, which was changed to one of the areas and left a trace that the content was updated, data is not changed for items whose cache content has changed after the start of synchronous processing, and synchronous processing is not performed. After leaving the synchronization process, only the trace indicating that it should be invalidated is left, and after the synchronization process ends, the item that has the trace indicating that it should be invalidated after the synchronization process is invalidated is Restarts the cache update process for each cache area at the same time, and when the synchronization process is started again, the cache area that leaves a trace that the cache content has been updated Items that have traces indicating that they have been updated, and items that have not been updated because the update was performed after the start of synchronization processing are stored in another cache area. If the area holds it, copy the contents of all this items to another cache area, then start writing the contents of the updated cache to the main memory, and perform the synchronization process and the update process to the cache. A method for maintaining coherency in cache memory, which is characterized by performing parallel processing. 2. When the synchronous processing request is made, the cache area is changed after the synchronous processing is started with respect to the item whose cache area has been changed, which leaves a trace indicating the update of the content to the cache. Only if
A cache that does not change data, leaves only a trace that it should be invalidated after the processing of writing the contents of the updated cache to the main memory is completed, and does not leave a trace that the contents of the cache have been changed. If there is a change in the cache content after the start of synchronization processing for the area where the area has not changed,
2. The cache memory coherency holding method according to claim 1, wherein the cache memory is updated without leaving a trace that the content of the cache has been updated. 3. An area used for performing the synchronous processing when a request for writing the contents of the cache that has been repeatedly updated into the main memory occurs during the synchronous processing. The same processing as the update processing to the main memory, but not the processing to write to the main memory is further increased, and when the synchronous processing ends, the processing to write the contents of the cache that has been repeatedly requested to the main memory The cache memory coherency holding method according to claim 1 or 2, wherein the method is executed. 4. A control in which, in each cache area, half of the maximum number of items physically held in the cache is set as the maximum number of items held in the cache area that directly reflects the cache update. For the cache area that left a trace that the contents of the cache were updated after the synchronous process was started, the location where the cache contents were changed after the synchronous process was started. Data is not updated and a trace indicating that it should be invalidated is left after the write processing to the main memory is completed.At the same time, the update content is written to the other half unused items, and the same process is performed again. 3. When the cache area is used for synchronous processing, the data held in the cache area is used. Or claim 3
Cache memory coherency retention method described. 5. Each cache area has two cache memories of the same capacity, and in each cache area, two cache memories are allocated to each item for normal writing and extended writing, When updating the cache contents, the cache memory allocated for normal writing in each cache area is updated at the same time, and after synchronization processing is started, a trace indicating the update of the contents to the cache. For the cache area that has been left behind, the process of writing the updated contents of the cache memory for normal writing to the main memory, and at the same time changing the contents of the cache after starting the synchronous process For normal writing, there is a trace that the data should not be updated and should be invalidated after the main memory write processing is completed. The update contents are written to the cache memory set for extended writing while remaining in the cache memory, and after the synchronization process is completed, the cache memory set for extended writing is updated. In the cache area where the contents are written, the roles of normal writing and extended writing are exchanged, and even when writing to the extended writing cache area, normal writing is performed. 4. A cache memory coherency method according to claim 1, claim 2 or claim 3, characterized in that a corresponding location with a cache memory for the same is used. 6. An information processing apparatus for intermittently performing a synchronization process for writing the updated contents of a cache to a main memory and synchronizing the contents of the cache and the main memory under a certain condition, The cache has a plurality of cache area means for multiplexing an area for storing data, and each of the cache area means has a cache memory for storing data in item units and each of the cache memory means. Item state data storage means for storing item state data indicating the state of the item,
And a control means for controlling the cache memory for each item according to the data stored in the item state data storage means, and updating of the items is performed to all the cache area means at the same time. At this time, the fact that the cache content was updated by the write processing in only one cache area was set in the item state data storage means, and a request for synchronous processing to write the updated cache content to the main memory occurred. In this case, the cache area means in which the item state data storage means is set to indicate the update of the content to the cache is changed to one of the other cache area means, and the content of the cache is changed after the synchronization processing is started. The data in the cache memory is not changed at the location where After the completion of the synchronization processing, the control means performs the invalidation of the set item indicating that the synchronization processing is to be invalidated, and after the synchronization processing is completed, , The cache area set in the item state data storage means that the contents of the cache are updated when restarting the processing of updating the cache for each cache area means at the same time and restarting the update processing again. If the means has an item whose cache content has been updated, and another cache area means holds an item whose update content is not held because the update was performed after the start of the synchronization processing, all of this item After copying the contents to another cache area, start writing the updated cache contents to the main memory, and The information processing apparatus characterized by performing in parallel the update process. 7. The item state data storage means, for each of the plurality of cache area means, data indicating a physical position in the cache memory, a flag indicating that the data is valid, and writing to the main memory. The data is not changed at the location where the cache content has changed after the start of the processing of 1. and the flag indicating that it should be invalidated after the completion of the writing processing of the updated cache content to the main memory, and the updated 7. The information processing apparatus according to claim 6, wherein a flag indicating that is set. 8. The control means sets half of the maximum number of items physically held in the cache memory as the maximum number of items held in a cache area that directly reflects a cache update. After the synchronization processing is started, the cache area means that has been set in the item state data storage means that the cache contents have been updated is For items whose cache contents have changed after the start of the process of writing to the memory, set that the data should not be updated and should be invalidated after the end of the synchronization process, and at the same time for the other half of the unused items The update contents are written, and when they are used again for the synchronization process, the updates made by the writing process for the other half items are used. Claim 6, wherein the door, the information processing apparatus according to claim 7 wherein. 9. Each of the cache area means comprises:
The control means has two cache memories of the same capacity, and the control means allocates the two cache memories for each item to either normal writing or extended writing and updates the contents of the cache. If the cache memory allocated for normal writing is updated at the same time, and after the synchronous processing is started, it is set that the item state data storage means indicates the content update to the cache, A place where the contents of the cache for normal writing are changed after the synchronous process is started at the same time that the process of writing the updated contents of the cache memory for ordinary writing to the main memory is performed. Data is not updated and the item state data storage means is set to invalidate after completion of the writing process to the main memory. Setting, the process of writing the updated contents to the cache memory set for extended writing, and the process of writing the updated contents to the cache memory set for extended writing after the synchronization process ends. , The role assignments for normal writing and extended writing are exchanged, and even when writing to the extended writing cache area is performed, the normal writing cache memory The information processing apparatus according to claim 6, wherein the corresponding position is used.