JPH08237514A - Display device - Google Patents

Abstract

PURPOSE: To prevent image data from being distorted even when there is no video signal in an input image signal by operating this device as a PLL circuit when a composite synchronizing signal is contained in the image signal but generating an internal synchronizing signal when this signal is not contained. CONSTITUTION: A composite synchronizing signal C-Sync outputted from a television linear circuit 13 is sent to a synchronizing control circuit 21. The circuit 21 is synchronized with this signal C-Sync but when no signal C-Sync is inputted, on the other hand, various kinds of timing signals are prepared by an internal transmitter and outputted to a control part 22 and an A/D converter 17 or the like. The control part 22 decides the presence/absence of a horizontal synchronizing signal HD and a vertical synchronizing signal VD inputted from the circuit 21 and sends out a synchronizing deciding signal to the circuit 21. When the signal C-Sync is inputted from the circuit 13, at the circuit 21, various kinds of timing signals are prepared and outputted to the other circuit. Besides, when no signal C-Sync is inputted, various kinds of timing signals are prepared and outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device such as a liquid crystal television device or a video monitor device.

[0002]

2. Description of the Related Art A circuit configuration of a general liquid crystal television device is shown in FIG. In the figure, reference numeral 11 is a receiving antenna such as a rod antenna. The television broadcast radio wave received by the receiving antenna 11 is sent to the tuner 12. The tuner 12 selects a desired channel from the received radio waves, converts it into an intermediate frequency signal, and sends it to the television linear circuit 13.

The television linear circuit 13 extracts the video signal and the composite synchronizing signal C-Sync from the intermediate frequency signal,
The video signal is sent to the signal switcher 14, and the composite sync signal C-Sy is sent.
nc is output to the synchronization control circuit 15.

The synchronization control circuit 15 has a PLL circuit inside, and generates various timing signals from the composite synchronization signal C-Sync to control the control section 16 and the A / D converter 1.
7, output to the segment electrode drive circuit 18 and the common electrode drive circuit 19.

The control unit 16 appropriately displays a channel number, a volume value, various messages and the like for displaying an operating state on the screen according to the timing of the horizontal synchronizing signal HD and the vertical synchronizing signal VD from the synchronizing control circuit 15. Data is created and sent to the signal switcher 14, while a blank signal for distinguishing a part with the image data and a part without the image data is sent to the signal switcher 14.

In response to the blank signal from the control unit 16, the signal switch 14 receives the image data for screen display in a portion having image data for screen display and the video signal from the television linear circuit 13 in a portion not having image data for screen display. To A / D converter 17
Output to.

The A / D converter 17 converts the video signal into digital data having a gradation of several bits for each pixel in synchronization with the sampling clock from the synchronization control circuit 15, and outputs it to the segment electrode drive circuit 18. To do.

This segment electrode drive circuit 18 is
A gradation signal is created according to the digital data from the D converter 17, and a segment electrode drive signal is created based on this gradation signal to drive the segment electrodes of the liquid crystal display panel 20 for display.

On the other hand, the common electrode drive circuit 19 creates a common drive signal in accordance with the timing signal from the synchronization control circuit 15 and sequentially scans and drives the common electrodes of the liquid crystal display panel 20.

[0010]

With the above-mentioned structure, the PLL circuit is formed in the sync control circuit 15, and the composite sync signal C sent from the television linear circuit 13 by this PLL circuit. -Various timing signals synchronized with Sync are generated.

Therefore, the composite sync signal C is received in the received radio wave.
-When Sync is not included, that is, when there is no video signal during tuning, the above PLL circuit does not operate, and only image data for screen display such as channel numbers and volume values indicating operating conditions and various messages. There was a problem that the image was distorted even when was displayed.

The present invention has been made in view of the above situation, and an object of the present invention is to display an operating state on a screen even when there is no video signal in an input image signal. An object of the present invention is to provide a display device capable of displaying image data without being disturbed.

[0013]

That is, the present invention determines whether or not a composite sync signal is included in an input image signal, and when the composite sync signal is included, the composite sync signal is detected. It operates as a PLL circuit in synchronism with, and generates an internal synchronization signal when it is determined that the composite synchronization signal is not included.

[0014]

With the above-described structure, even if there is no video signal in the input signal (received radio wave), such as when tuning the liquid crystal television set, a screen display for displaying the operating state is provided. The image data can be displayed without being disturbed.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a liquid crystal television device will be described below with reference to the drawings. FIG. 1 shows the circuit configuration thereof, which is basically the same as that shown in FIG.

In FIG. 1, the composite sync signal C-Sync output from the television linear circuit 13 is sent to the sync control circuit 21. The synchronization control circuit 21 has a PLL circuit and an internal oscillator. When the composite synchronization signal C-Sync is input from the television linear circuit 13, the synchronization control circuit 21 synchronizes with the composite synchronization signal C-Sync, while When the composite sync signal C-Sync is not input, various timing signals are created by the internal oscillator in response to the sync determination signal from the control unit 22, and the control unit 22, the A / D converter 17, the segment electrodes are generated. Output to the drive circuit 18 and the common electrode drive circuit 19.

The control unit 22 determines the presence / absence of the horizontal synchronization signal HD and the vertical synchronization signal VD input from the synchronization control circuit 21, and sends a synchronization determination signal according to the determination result to the synchronization control circuit 21. At the same time, image data for screen display such as channel numbers and volume values indicating various operating states, various messages, etc. are created and sent to the signal switcher 14, and this signal switcher 14 does not have a portion having the image data. A blank signal is sent to distinguish it from the part.

Next, the operation of the control section 22 will be mainly described. FIG. 2 shows the processing content of the horizontal synchronization determination performed by the control unit 22 at regular time intervals after the power is turned on. At the beginning, a horizontal synchronization determination subroutine (indicated as “horizontal synchronization determination sub” in the figure) is activated ( Step A
1) After the presence or absence of synchronization is determined by the number of pulses of the horizontal synchronization signal HD and the vertical synchronization signal VD from the synchronization control circuit 21, subsequently, it is determined whether or not there is synchronization (step A2).

FIG. 3 exemplifies the content of this horizontal synchronization determination subroutine. First, a composite synchronization consisting of a horizontal synchronization signal HD and a vertical synchronization signal VD is performed for a fixed time, for example, 0.54 [mS]. The number of pulses of the signal C-Sync is counted (step B1).

When the input horizontal synchronizing signal HD is counted and the period of the horizontal synchronizing signal HD is set to 63.5 [μs] during this 0.54 [mS], "0.54
It should be possible to count an average of about 8.5 pulses with [mS] /63.5 [μs] ”, so allow a margin of ± 1.5 to set this to 7 to 10, and then It is determined whether the count value is "7" to "10" (step B2).

When it is judged that the count value is within the range of "7" to "10", it is judged that there is synchronization as it is (step B3), this subroutine is ended and the process returns to the process of FIG.

When it is determined that the count value is out of the range of "7" to "10", it is determined that there is no synchronization (step B4), this subroutine is terminated, and the process of FIG. Return.

However, if the result of determination in step A2 is that there is synchronization, the processing of FIG. 2 is terminated as it is, but if there is no synchronization, the horizontal synchronization determination subroutine is started again (step A3). ), Synchronous control circuit 2
The presence or absence of synchronization is determined by the number of pulses of the horizontal synchronization signal HD and the vertical synchronization signal VD from 1, and then it is determined whether or not there is synchronization as a result of the determination (step A4).

The above operation is repeated again in step A.
5 and A6 are repeatedly executed, and if it is determined that there is no synchronization as a result of the determination, the fourth horizontal synchronization determination subroutine is activated to determine the presence or absence of synchronization.
This is the end of the processing in FIG.

The horizontal synchronization determination subroutine is performed up to 4 times in consideration of the equalizing pulse in the vertical blanking period. That is, when the number of pulses is counted by the above subroutine in the vertical blanking period as shown in FIG. 4, the count value is "1" due to the equalization pulse, although synchronization is originally present.
It exceeds 0 ”, and it is determined that there is no synchronization. Therefore, when the subroutine is executed four times in succession, the count is made at least once in the part where there is no equalization pulse, so that the count value falls within the range of "7 to 10" and there is sure synchronization The state of can be determined.

In this way, by making the number of pulses input within a fixed time have a predetermined range, in the received radio wave, when the video signal and the composite sync signal C-Sync are not actually present, The noise can be easily distinguished without being erroneously recognized as a pulse of the synchronization signal.

The control unit 22 sends the result of the above determination as a synchronization determination signal to the synchronization control circuit 21, and when the synchronization control circuit 21 determines that there is synchronization, that is, the television linear circuit. When the composite sync signal C-Sync is actually input from 13, the internal PLL circuit is synchronized with the composite sync signal C-Sync to create various timing signals and output to other circuits.

When it is determined that there is no synchronization, that is, the television linear circuit 13 outputs the composite synchronization signal C-Syn.
When c is not input, the synchronization control circuit 21 creates various timing signals by the internal oscillator and outputs them to other circuits.

Therefore, only the image data for screen display such as the channel number and volume value indicating the operating state, various messages, etc. are digitized by the A / D converter 17 from the control section 22 via the signal switch 14, and the segment is displayed. Even when the liquid crystal display panel 20 performs display output by the electrode drive circuit 18, the display image can be obtained easily without being disturbed.

In the above embodiment, the control unit 22 determines that the number of pulses input within a fixed time is within a predetermined range as shown in FIGS.
When it was determined that there was synchronization at least once out of a maximum of four times, it was processed as if there was synchronization immediately. However, measurement was performed a certain number of times, and synchronization was the first time when it was determined that there was synchronization a prescribed number of times. If it is processed as, the reliability can be further improved.

Hereinafter, such a case will be described with reference to FIG. 5 as another operation example of the embodiment of the present invention. FIG. 5 shows the processing content of the horizontal synchronization determination performed by the control unit 22 at a specific time interval after the power is turned on. At the beginning, the horizontal synchronization signal HD is initially set for a fixed time, for example, 0.54 [mS].
And a vertical sync signal VD, which is a composite sync signal C-Sync.
The number of pulses is counted (step C1).

When the input horizontal synchronizing signal HD is counted and the period is set to 63.5 [μs] during this 0.54 [mS], “0.54 [mS] / 6
Since it should be possible to count an average of about 8.5 pulses in "3.5 [μs]", allow some margin,
Then, it is determined whether the count value is "7" or more (step C2).

Only when it is judged that the count value is "7" or more, the number of detection times is updated and set to "+1" (step C3), and thereafter, the number of times of measurement is "+" regardless of the count value.
1 ”is updated and set (step C4).

Next, the number of times of measurement is constant, for example, "1".
It is judged whether or not it becomes "5" (step C5), and "15".
If it is less than this, this process is once terminated, and the execution start of the next process is awaited.

Then, when the number of times of measurement becomes "15" and this is judged, it is then judged whether or not it is judged to be in synchronization at the time of the previous measurement (step C6). If it is determined that there is synchronization during the previous measurement, the composite synchronization signal C
-It is determined whether or not the number of Sync detections is "0" (step C7), and it is determined that there is synchronization if at least "1" is detected during "15" measurements instead of "0". (Step C11).

On the contrary, if the number of detections of the composite synchronization signal C-Sync is "0" in this step C7 and "1" is not detected during "15" times of measurement, it means that there is no synchronization. The determination is made (step C8).

If it is determined in step S6 that there is no synchronization during the previous measurement, the composite synchronization signal C
-It is determined whether or not the number of Sync detections is "3" or more (step C10), and if "3" or more is detected, it is determined that there is synchronization (step C11).

On the contrary, in this step C10, the number of detections of the composite synchronizing signal C-Sync is less than "3", and "1" is detected.
If only “2” times are detected at the maximum during 5 ”times of measurement, it is determined that there is no synchronization (step C8).

However, after the presence / absence of synchronization in step C8 or C11 is determined, both the number of times of measurement and the number of times of detection are reset to the initial value "0" for the next determination (step C9). When the processing is completed, it waits for the next execution start of this processing.

In this way, a certain number of times, for example, "15"
Only when the measurement is performed a predetermined number of times, for example, "1" times or more when it is determined that there is synchronization in the previous time, and "3" times or more when it is not determined that there is synchronization in the last time. If processing is performed with synchronization for the first time, the reliability can be further improved.

The control unit 22 determines the presence or absence of synchronization as described above, and the result is used as a synchronization determination signal, which is the synchronization control circuit 21.
Since the operation of the synchronous control circuit 21 after being sent to the above is the same as the case shown in FIGS. 2 to 4, the description thereof will be omitted.

In the above embodiment, the present invention is applied to a liquid crystal television set, but the present invention is not limited to this. For example, a video monitor device or the like may be affected by the presence or absence of a synchronization signal in the input image signal. It is needless to say that the present invention can be applied to all display devices that receive the information.

[0043]

As described above in detail, according to the present invention, it is possible to reliably judge whether or not a composite synchronizing signal is included in an input image signal, and to display an operating state even if there is no composite synchronizing signal. A display device capable of displaying image data without being disturbed can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration according to an embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of the embodiment.

FIG. 3 is a flowchart for explaining the operation of the embodiment.

FIG. 4 is a diagram for explaining the operation of the embodiment.

FIG. 5 is a flowchart for explaining another operation example of the same embodiment.

FIG. 6 is a block diagram showing a circuit configuration of a general liquid crystal television receiver.

[Explanation of symbols]

 11 ... Receiving antenna 12 ... Tuner 13 ... Television linear circuit 14 ... Signal switcher 15, 21 ... Synchronous control circuit 16, 22 ... Control part 17 ... A / D converter 18 ... Segment electrode drive circuit 19 ... Common electrode drive circuit 20 ... Liquid crystal display panel

Claims (3)

[Claims] 1. The number of pulses of a composite sync signal obtained from an input image signal within a fixed time is measured. If the measured value is within a predetermined range, it is determined that there is a composite sync signal, and the above measurement is performed. If the measured value does not fall within the predetermined range even after repeating a specific number of times, it is judged that there is no composite sync signal, and a judging means for judging the presence or absence of the composite sync signal; A display device comprising: a PLL circuit that synchronizes with the composite synchronization signal at this time; and an internal synchronization generation means that generates an internal synchronization signal when the determination means determines that there is no composite synchronization signal. 2. The composite synchronizing signal is included when the determining means repeats the measurement a specific number of times and the number of times when the pulse of the composite synchronizing signal is within a predetermined range reaches a certain level. The display device according to claim 1, wherein the display device determines that the display device has been turned on. 3. The determination level of the number of times when the pulse of the composite synchronizing signal is within a predetermined range after the measurement is repeated a specific number of times by the determining means, the pulse of the composite synchronizing signal is predetermined in the previous measurement. The display device according to claim 2, wherein the display device is made different depending on whether or not it is within the range.