JPH08237238A - Clock oscillation circuit and voltage controlled oscillation circuit using the circuit - Google Patents

Abstract

PURPOSE: To provide a clock oscillation circuit which executes a free-running oscillation at a great rate frequency. CONSTITUTION: In SR-FF20C, the level of a clock signal CK in an output terminal Q is given to a gate 20A, and the level of an inverse clock signal CK/in an inverse output terminal Q/is given to a gate 20B. The gate 20A obtains the inverted value of AND between the level obtained by inverting a phase control signal S1 and the level of the signal CK/. When the signal S1 is 'L', SR-FF20 is set or reset by the inverted value of AND and the inverted value of OR and it executes a free-running oscillation. Time for one period in the free-running frequency becomes only the fall time of the signal CK and the signal CK/, and the time is set by the capacitance value of respective capacitors 51 and 52. When the signal S1 becomes 'H', SR-FF20 is set and the phases of the signal CK and the signal CK/change.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock oscillating circuit which is used in a communication device or the like and which outputs a clock signal by self-oscillating with supply of a power source and a voltage controlled oscillating circuit using the same.

[0002]

2. Description of the Related Art FIG. 2 is a logic circuit diagram showing a conventional clock oscillator circuit. A clock extraction circuit and a clock oscillation circuit for instantaneously obtaining a clock signal synchronized with the phase of the received data from the received data are important circuits in a communication device. In recent years, technological developments such as high-speed operation, high stability, and miniaturization of circuits for clock extraction circuits and clock generation circuits, etc., which have been performed along with the speedup of data communication, have been conducted.
It is considered to be an important technology for realizing a high-speed communication device. The clock generation circuit of FIG. 2 is configured to control the output phase of the clock oscillation by inputting the phase control pulse PI, and the 2-input N having the pulse PI as one input.
The AND gate 1 is provided. On the output side of the NAND gate 1, four stages of inverting amplifier circuits (hereinafter referred to as inverters) 2 to 5 are connected in series. The output side of the final stage inverter 5 is connected to the output terminal out, and NA
It is feedback-connected to the other input terminal of the ND gate 1.
In the clock oscillation circuit having such a configuration, for example, NA
When the pulse PI becomes "H" when the feedback input of the ND gate 1 is "L", the NAND gate 1 outputs "H". Each of the inverters 2 to 5 continues to invert “H” of the output of the NAND gate 1, and the inverter 5 outputs “H”. "H" of the output of the inverter 5 is the NAND gate 1
Be returned to. In this way, the clock oscillation circuit oscillates at a frequency that depends on the transmission time of the inverters 2-5 and the like.

[0003]

However, the conventional clock oscillator circuit has the following problems. FIG. 3 is a circuit diagram showing the configuration of the inverter shown in FIG. 2, and shows an inverter generally used in a clock oscillator circuit and the like. Each of the inverters 2 to 5 has the same configuration, and an npn-type transistor 6 (hereinafter simply referred to as a transistor) whose base is connected to the input terminal in1 for the output signal of the preceding stage and a transistor whose base is connected to the reference voltage input terminal in2 7 and 7, respectively. The collector of the transistor 6 is connected to the power source V via the resistor 8.
It is connected to CC, and the collector of the transistor 7 is directly connected to the power supply VCC. The emitters of the transistors 6 and 7 are commonly connected to the constant current source 9, and the output side of the constant current source 9 is connected to the power supply VEE. A connection node between the collector of the transistor 6 and the resistor 8 is connected to the base of the transistor 10, and the collector of the transistor 10 is connected to the power supply VCC. The emitter of the transistor 10 is connected to the output terminal out and also to the constant current source 11, and the constant current source 11 is connected to the power supply VEE.

The transmission time in each inverter 2-5 is
The operating characteristics of the transistors 6, 7 and 10 are respectively determined, but these operating characteristics are easily affected by manufacturing variations, temperature changes, and the like. Therefore, each inverter 2
In the clock oscillation circuit whose oscillation frequency is determined by the transmission time of ~ 5, the accuracy of the free-running frequency could not be improved. Therefore, the applicant of the present application proposes the following clock oscillation circuit (hereinafter referred to as the previous proposal) in Japanese Patent Application No. 6-38580 (not yet published). In the configuration of the previously proposed clock oscillation circuit in which oscillation is controlled by inputting a phase control signal, a plurality of gates are connected in series. And
By inputting the phase control signal to two or more gate circuits among these gates, it becomes easy to determine the phase control of the clock signal, and by connecting a capacitor between the output terminal of each gate and the power supply. The oscillation frequency is adjusted by the capacitance value of the capacitor.

FIGS. 4 (i) and (ii) are diagrams for explaining the previously proposed clock oscillation circuit. FIG. 4 (i) shows a configuration example, and FIG. 4 (ii) shows its output waveform. There is. This clock oscillation circuit includes a 2-input NOR gate 12, and the output side of the NOR gate 12 is connected to one input terminal of a 2-input NOR gate 13. An inverter 14 is connected to the output side of the NOR gate 13 and the inverter 14
Is connected to the output terminal out and is also feedback-connected to one input terminal of the NOR gate 12. Each N
The phase control signals are commonly input to the other input terminals of the OR gates 12 and 13. When the output of the inverter 14 is fed back, this clock oscillation circuit oscillates free-running, and the output terminal out outputs the clock signal having a waveform of one cycle shown in FIG. 4 (ii). However,
In the above proposal, the number of gates becomes large, and the delay due to the gates hinders the generation of the high speed clock signal. Also, assuming that the rise time of the output signal of the clock oscillator is sufficiently smaller than the fall time, the fall time is changed so that the oscillation frequency can be changed. In this case, the rise time of the output signal cannot be ignored, and there is a problem in obtaining a wide range of desired frequencies. Further, the duty ratio of the output waveform is not 50%, and there is room for improvement.

[0006]

Means for Solving the Problems The first to thirteenth inventions are as follows.
In order to solve the above problems, a clock oscillating circuit that is phase-controlled based on a phase control pulse and frequency-controlled based on the capacitance value of a frequency setting capacitor to oscillate and output a clock signal of the free-running oscillation frequency In, the following structure is taken. That is, the clock oscillator circuit is set and reset based on the logic between the phase control signal for forming the phase control pulse and the first feedback signal and the second feedback signal fed back from the output side. A set-reset flip-flop (hereinafter referred to as SR-FF) which self-oscillates by setting and resetting to generate the clock signal and an inverted clock signal obtained by inverting the clock signal.
And a second capacitor that sets a rise time or a fall time in the first feedback signal, and a second capacitor that sets a rise time or a fall time in the second feedback signal. The first and second feedback signals are composed of frequency signals corresponding to the clock signal and the inverted clock signal, respectively. In a fourteenth aspect of the invention, in a voltage controlled oscillator circuit, charge and discharge charges based on a control voltage provided from the outside are given to the first and second capacitors in the clock oscillator circuit of the first to thirteenth aspects. The constant current sources are connected to each other and are configured to oscillate at a frequency corresponding to the control voltage.

[0007]

According to the first to thirteenth aspects of the invention, since the clock oscillation circuit is configured as described above, the first and second frequency signals corresponding to the clock signal and the inverted clock signal output from the SR-FF are provided. Is fed back to the input side of the SR-FF, and the SR-FF oscillates by itself. SR-F
F is set and reset based on the logic between the phase control signal and the first and second feedback signals. For example, when the phase control pulse is formed in the phase control signal, SR-FF is set in synchronization with the phase pulse. Thereby, the phase control of the free-running oscillation of the SR-FF is performed. In addition, the first and second capacitors allow the first
And the rising or falling time of the second feedback signal is set. The clock signal output from the SR-FF and the inverted clock signal are complementary, and the repetitive operation is performed such that the second feedback signal starts to fall when the first feedback signal has finished falling. By changing the falling edges of the first and second feedback signals,
The oscillation frequency of SR-FF changes. That is, the oscillation frequency is changed by the first and second capacitors. According to the fourteenth invention, the constant current source is controlled by the control voltage. As a result, the charge / discharge time of the capacitor of the clock oscillation circuit of the first to thirteenth inventions is controlled by the control voltage,
The free-running oscillation frequency is controlled. Therefore, by changing the control voltage, signals of different frequencies can be obtained, and the voltage control oscillation circuit can perform the phase control of the frequency signal by the phase control pulse.

[0008]

First Embodiment The purpose of this embodiment is to realize a clock oscillation circuit which oscillates at a high-speed frequency and outputs a clock signal CK having the free-running oscillation frequency. FIG. 1 is a logic circuit diagram of a clock oscillation circuit showing a first embodiment of the present invention. This clock oscillator circuit has an input terminal IN for inputting a phase control signal S1 and an output terminal out for outputting a clock signal CK.
It has one SR-FF 20 connected in between. S
The output terminal Q of the R-FF 20 is connected to the output terminal out and one electrode of the first capacitor 51, and SR
-Feedback connection to the input side of FF20. SR-FF
The inverting output terminal Q / of 20 is connected to one electrode of the second capacitor 52 and is feedback-connected to the input side of the SR-FF 20. The other electrodes of the capacitors 51 and 52 are connected to the power supply VCC. That is, the clock signal CK and the inverted clock signal CK / are the first and second feedback signals.

The SR-FF 20 is set when the inverted value of the logical product between the level obtained by inverting the phase control signal S1 in which the phase control pulse PI is formed and the level of the clock signal is effective, and is set to the level of the signal S1. It has the function of being reset and oscillating when the inverted value of the logical sum between it and the level of the inverted clock signal is valid. The SR-FF 20 is equivalent to one including the two gates 20A and 20B shown in FIG. 1 and a general SR-FF 20C. That is, the signal S1 and the fed back clock signal CK are given to the gate 20A, the signal S1 and the fed back inverted clock signal CK / are given to the gate 20B, and the outputs of the respective gates 20A and 20B are SR-. This is equivalent to the configuration given to the set terminal S and the reset terminal R of the FF 20C, respectively. FIG. 5 is a circuit diagram showing FIG. 1 at the transistor level.

In FIG. 5, the clock oscillator circuit of FIG. 1 is configured without using the gates 20A and 20B. S in FIG.
The R-FF 20 has a reference voltage input terminal in serving as a threshold, an input terminal IN for the phase control signal S1, a power supply VCC, and a power supply VE.
Twelve transistors 21 to 32 connected between E and
And four resistors 33 to 36 and five constant current sources 37 to 4
1 and. Input terminal IN for inputting signal S1
Are the two transistors 21, 22 in the SR-FF 20.
Each is connected to the base. Transistor 21
Is connected to the collectors of the transistors 23 and 27, the base of the transistor 31, and one end of the resistor 34. The other end of the resistor 34 is connected to the power supply VCC. The emitter of the transistor 21 is connected to one end of the constant current source 40 together with the emitters of the transistors 25 and 23, and the other end of the constant current source 40 is connected to the power source VEE. The base of the transistor 25 is connected to one electrode of the capacitor 51 and the base of the transistor 27, and the other electrode of the capacitor 51 is connected to the power supply VCC. The collector of the transistor 25 is connected to the base of the transistor 29 and one end of the resistor 33, and the other end of the resistor 33 is connected to the power supply VCC.

The collector of transistor 22 is the collector of transistor 26, the base of transistor 30,
It is connected to one end of the resistor 36, and the other end of the resistor 36 is connected to the power supply VCC. The emitter of the transistor 22 is connected to one end of the constant current source 41 together with the emitters of the transistor 24 and the transistor 26.
The other end of 1 is connected to the power supply VEE. Input terminal in
Are connected to the bases of the respective transistors 23 and 24. The collector of the transistor 24 is connected to the collector of the transistor 28, the base of the transistor 32, and one end of the resistor 35. The other end of the resistor 35 is connected to the power supply VCC. Transistor 26
The base of the capacitor 52 is connected to one electrode of the capacitor 52 and the base of the transistor 28, and the other electrode of the capacitor 52 is connected to the power supply VCC. The emitter of the transistor 29 is connected to the base of the transistor 27, the emitter of the transistor 32, the output terminal out, and one end of the constant current source 38. The other end of the constant current source 38 is connected to the power source VEE. The emitter of the transistor 27 is connected to the emitter of the transistor 28 and one end of the constant current source 37, and the other end of the constant current source 37 is connected to the power supply VEE. The base of the transistor 28 is the emitter of the transistor 30 and the transistor 31.
Of the constant current source 39, and the other end of the constant current source 39 is connected to the power source VEE. The collectors of the transistors 29, 30, 31, 32 are connected to the power source V
Each is connected to CC. That is, the transistor 2
Except for Nos. 1 and 22, normal SR-FFs in which the nodes Na and Nb to which the bases of the transistors 25 and 26 are connected are the inversion set terminal S / and the inversion reset terminal R /, respectively.
Is.

6 (1) and 6 (2) show the SR-FF in FIG.
It is a figure explaining operation | movement of 20C and SR-FF20. The operation of FIG. 1 will be described with reference to FIG. When the phase control signal S1 is at "L" level, the SR-FF 20
When “L” level is input to the set terminal S of C and “L” level is input to the reset terminal R, that is, the node N in FIG.
When both a and Nb become "H" level, the immediately preceding data is held and output from the output terminal Q. When “L” level is input to the set terminal S and “H” level is input to the reset terminal R, “L” level is output from the output terminal Q. When “H” level is input to the set terminal S and “L” level is input to the reset terminal R, from the output terminal Q,
The "H" level is output. When “H” is input to both the set terminal S and the reset terminal R, the output from the output terminal Q becomes indefinite. The clock oscillation circuit of FIG. 1 oscillates at a predetermined free-running frequency after power is supplied, and a clock signal CK having the oscillation frequency is output from the output terminal out. That is, in the state where the level of the signal S1 is "L" without the phase control pulse PI, the SR-FF 20C outputs the clock signal CK of "L" level, and the first gate 20A outputs the signal S1 and its clock signal. The logic of the signal CK is obtained and the "H" level is set to the set terminal S of the SR-FF20C.
Give to. As a result, the level of the clock signal CK output from the output terminal Q changes to "H". At this time, the inverting output terminal Q / transits to "L", and "H" is output from the second gate 20B. This "H" level is input to the reset terminal R, and the level of the output terminal Q becomes "L" again. By repeating this operation, the clock signal CK becomes a periodic wave having a predetermined frequency.

On the other hand, in the circuit configuration of FIG. 5, each of the transistors 21, 23, 25 performs the operation corresponding to the gate 20A, and each of the transistors 22, 24, 26 has the gate 20.
The operation corresponding to B is performed. Therefore, the clock signal CK
Is a periodic wave of a predetermined frequency. For example, when the level of the phase control signal S1 is "L" level, the transistors 21 and 2 are
2 is off. In this state, for example, when "H" level is input to the node Na, the transistor 23 turns off and the transistor 25 turns on. Also, the node Nb
When the "L" level is input to the transistor 24, the transistor 24 is turned on and the transistor 26 is turned off. At this time, the resistance 34
Current does not flow into the transistor 31, and the base of the transistor 31 becomes the level of the power supply VCC. Therefore, the transistor 31 is turned on. Also, since the transistor 25 is on,
The base of the transistor 29 is connected to the resistor 33 from the power supply VCC.
Then, the transistor 29 is turned off because the voltage drops to the lower level. Complementarily, since transistor 24 is on and transistor 26 is off, transistor 32 is off and transistor 30 is on. Each transistor 29, 3
Since the emitter of 2 and the emitters of the transistors 30 and 31 are connected to the bases of the transistors 27 and 28, respectively, an emitter follower is formed.

Since the bases of the transistors 29 and 32 are at a level lower than the power supply VCC by the voltage drop of the resistors 33 and 35 and the emitter-base voltage Vbe, the base of the transistor 27 is the resistance of the power supply VCC. The level becomes lower than the voltage drop of 33, 35 and the emitter-base voltage Vbe. Transistor 30,
The bases of 31 are both at the level of the power supply VCC, and the base of the transistor 28 is at a level lower than the power supply VCC by the emitter-base voltage Vbe. Transistor 2
7 and the transistor 28 form a differential pair, and the base level of the transistor 28 is higher.
7 turns off and transistor 28 turns on. Similarly, the base of the transistor 32 is at a level lower than the power supply VCC by the voltage drop of the resistor 35, and the base of the transistor 31 is at the level of the power supply VCC. Therefore, the power supply VC
Not only a current flows from C through the resistor 35 and the transistor 24, but also a current flows through the resistor 35 and the transistor 28, so that the level of the base of the transistor 32 becomes more stable. As a result, the node Na changes to the "L" level and the node Nb changes to the "H" level.

FIG. 7 is an output waveform diagram of the output terminal Q and the inverting output terminal Q / of FIG. 1, and the horizontal axis is the time axis. The period from time t _{a to} t _c in FIG. 7 is the fall time of the inverted clock signal CK / output from the inverted output terminal Q /, and time t _{c to} t _e is the clock signal output from the output terminal Q. This is the fall time of CK. The sum of these fall times is the output time for one cycle of the clock oscillation circuit. Here, the phase control for the clock signal CK will be described. If the time t _a ~t _c phase control pulse PI in the period is input, i.e., when the phase control signal S1 becomes "H" level, the output signal of the phase of the SR-FF20C does not change. When the phase control pulse PI is input during the period of time t _{c to} t _e , SR-FF2
The "H" level is input to the set terminal S of 0C, and the "L" level is input to the reset terminal. Therefore, when set, the level of the output terminal Q rises toward the "H" level, and the level of the inverting output terminal Q / falls toward the "L" level.

In FIG. 5, the signal S1 becomes "H" level and the transistors 21 and 22 are turned on. For example, when the transistors 21 and 22 are turned on while the node Na is at the “L” level and the node Nb is at the “H” level, the transistor 22 is turned on, the transistor 25 is turned off, and a current flows through the resistor 34 so that the transistor 31 The base level becomes lower than the power supply VCC by the voltage drop of the resistor 34, and the transistor 31 is turned off. In addition, the transistor 29 is turned on. On the other hand, the transistor 22 is turned on, the transistor 24 is turned off, and the base of the transistor 30 is
The voltage drops from the power supply VCC by the voltage drop due to the resistor 36, and the transistor 30 is turned off. Transistor 3
The base of 2 is the power supply VCC because the transistor 24 is off.
And the transistor 32 is turned on.
Therefore, the transistor 27 is turned on and the transistor 28 is turned on.
Turns off. Similar to the above, the base of the transistor 32 is at the level of the power supply VCC, and the base of the transistor 31 is at the level lower than the power supply VCC by the voltage drop of the resistor 34. A current flows from the power supply VCC through the resistor 34 and the transistor 21, and a current flows from the power supply VCC through the resistor 34 and the transistor 27. Therefore, transistor 3
The base level of 1 is more stable, and the node Na is "H".
The level of the node Nb changes to "L" level. That is,
The level of the output terminal Q rises and the phase of the clock signal CK changes.

As described above, in the clock oscillation circuit of the first embodiment, the sum of the level fall times at the output terminal Q and the inverting output terminal Q / is the output time of one cycle, and The free-running frequency is set only by these fall times. The fall time of the level of each output terminal Q and the inverting output terminal Q /
Since the values are respectively determined by 52, an arbitrary free-running oscillation frequency can be obtained by adjusting the capacitance values of these capacitors 51, 52, and a clock signal CK having a high oscillation frequency can be generated. In addition, as shown in FIG. 5, the functions of the gates 20A and 20B are set by the SR-FF 20,
Each input stage transistor 21, which sets the reset condition,
23 and 25 and the transistors 22, 24 and 26 can be provided, the delay due to the gate is eliminated, and a high-speed clock oscillation circuit can be configured. On the other hand, a clock extraction circuit for extracting a clock signal synchronized with the data is composed of the clock oscillation circuit of this embodiment and the data change point extraction circuit, and the change point detection signal output from the data change point extraction circuit is When the phase control pulse PI is input to the input terminal IN, it is possible to correct the phase of the clock signal CK which is free-running and oscillated so as to be synchronized with the phase control pulse PI. Further, during the period when the phase control pulse PI is not input,
The clock signal CK in the corrected phase state can be output. Second Embodiment FIG. 8 is a circuit diagram of a clock oscillating circuit showing a second embodiment of the present invention, and elements common to those in FIG. 5 are designated by common reference numerals.

This clock oscillator circuit comprises an SR-FF 20 having the same structure as that of FIG. 5 of the first embodiment, and the SR-FF 2.
It is composed of two oscillation frequency setting circuits 60 and 70 connected to 0. The oscillation frequency setting circuit 60 uses the power supply VC
An emitter follower transistor 61 having a collector connected to C, a first capacitor 62, and a first constant current source 63 are provided. Similarly, the oscillation frequency setting circuit 70
Is provided with an emitter follower transistor 71 having a collector connected to the power supply VCC, a second capacitor 72, and a second constant current source 73. The base of the transistor 61 in the oscillation frequency setting circuit 60 is SR-FF20.
It is connected to the base of the transistor 32 therein, and the emitter of the transistor 61 is connected to one electrode of the capacitor 62, one end of the constant current source 63, and the base of the transistor 25. The other electrode of the capacitor 62 is connected to the power supply VCC, and the other end of the constant current source 63 is connected to the power supply VE.
It is connected to E. The base of the transistor 71 in the oscillation frequency setting circuit 70 is connected to the base of the transistor 31 in the SR-FF 20, and the emitter of the transistor 71 is connected to one electrode of the capacitor 72 and the constant current source 7.
3 is connected to one end of the transistor 3 and the base of the transistor 26. The other electrode of the capacitor 72 is connected to the power supply VCC, and the other end of the constant current source 73 is connected to the power supply VEE. It is assumed that the base-emitter voltages in the forward active regions of all the transistors shown in FIG. 8 have the same value Vbe. Next, the operation of the clock oscillator circuit of FIG. 8 will be described.

This clock oscillation circuit also has a clock signal C.
First and second corresponding to K and the inverted clock signal CK /
Of the feedback signal of the input node Na of the SR-FF 20,
The clock oscillation circuit is fed back to Nb and self-oscillates at a predetermined frequency. In this embodiment, the first and second feedback signals are
Based on the level of the bases of the transistors 32 and 31,
Has been generated. The level transition of the base of each of the transistors 32 and 31 has the same frequency as that of the clock signal CK and the frequency of the inverted clock signal CK /. That is, the first and second feedback signals having the same frequencies as the frequencies of the clock signal CK and the inverted clock signal CK / are generated by the oscillation frequency setting circuits 60 and 70 to generate the nodes Na and Nb.
Be returned to. FIG. 9 is a waveform diagram showing one cycle of the oscillation waveforms of the nodes Na and Nb in FIG. 8 and the output waveform at the output terminal out. Vr in the output waveform of the output terminal out in FIG. 9 is a voltage value applied across the resistors 34 and 35 having the same value. The oscillation frequency setting circuit 60 performs an operation that satisfies the following expression (1). C ₆₂ · V ₁ = i ₆₃ · t ₁ (1) where C ₆₂ is the capacitance of the capacitor 62, and V ₁ is the node N.
The amplitude voltage of a, i ₆₃ is the current value of the constant current source 63, and t ₁
Is the discharge time of the capacitor 62 (that is, the fall time of the oscillation waveform at the node Na).

The oscillation frequency setting circuit 70 operates in the same manner, and operates to satisfy the following equation (2). C ₇₂ · V ₂ = i ₇₃ · t ₂ (2) where C ₇₂ is the capacity of the capacitor 72 and V ₂ is the node N
The amplitude voltage of b, i ₇₃ is the current value of the constant current source 73, and t ₂
Is the discharge time of the capacitor 72 (that is, the fall time of the oscillation waveform at the node Nb). In the expressions (1) and (2), the amplitudes of the oscillation waveforms of the node Na and the node Nb are differential amplitudes, so V ₁ = V ₂ and C ₆₂
= C ₇₂ (= C), i ₆₃ = i ₇₃ = (= i), t ₁ =
It becomes t ₂ . The fall time at the node Na and the fall time at the node Nb are equal. When the oscillation amplitude at the node Na and the node Nb is V, the fall time t of each of the nodes Na and Nb is represented by (3). t = C · V / i (3) In FIG. 9, the period from t _{a to} t _c is the fall time of the waveform of the node Nb, and the period from t _{c to} t _e is the fall time of the waveform of the node Na. Has become. The output time T of one cycle of the output waveform of this clock oscillation circuit is expressed by the equation (4), and the free-running oscillation frequency F is expressed by the equation (5).

T = 2 · t = 2 · C · V / i (4) F = 1 / T = i / 2 · C · V (5) The clock oscillator circuit of the present embodiment and the The clock oscillation circuits of the first embodiment will be compared. In the first embodiment, the capacitor 51
Is directly connected to the output terminal out to prolong the fall time of the clock signal CK and the inverted clock signal CK /, and is fed back to the input stage of the SR-FF20. In this embodiment, since the capacitors 62 and 72 are not directly connected to the output terminal out, the clock signal CK output from the output terminal out is not affected. Therefore, the fall time of the clock signal CK is shortened, and the duty ratio is improved to 50%. Here, the phase control for the clock signal CK will be described. Phase control pulse P during the period from time t _{a to} t _c
When I is input and the phase control signal S1 becomes "H" level, the phase of the output signal of the SR-FF 20 does not change. When the phase control pulse PI is input during the period from time t _{c to} t _e , the waveform of the node Na rises toward the “H” level and the level of the node Nb becomes “L” as in the first embodiment. Get down. That is, the phase of the clock signal CK changes. As described above, in the clock oscillation circuit of the second embodiment, the oscillation frequency setting circuits 60 and 70
Is provided, the clock signal CK is output without being affected by the capacitor. Therefore, the clock signal CK
The duty ratio of is improved. Further, the sum of the fall time of the waveform at the node Na and the fall time of the node Nb is the time for one cycle of free-running oscillation. Therefore, by adjusting the capacitance values of these capacitors 62 and 72, any value can be obtained. The free-running oscillation frequency is obtained, and the clock signal CK having a high-speed oscillation frequency can be generated.

Further, as shown in FIG. 8, gates 20A, 20
The function of B can be given to the transistors 21, 23, 25 and the transistors 22, 24, 26 of the input stage for setting the set and reset conditions of the SR-FF 20, and the delay is delayed as compared with the case of forming the gates 20A, 20B. Is reduced, and a high-speed clock oscillation circuit can be configured. On the other hand, a clock extraction circuit for extracting a clock signal synchronized with data is composed of the clock oscillation circuit of this embodiment and the data change point extraction circuit, and the change point detection signal output from the data change point extraction circuit Input terminal I as phase control pulse PI
If input to N, it is possible to correct the phase of the clock signal CK oscillating free-running so as to be synchronized with the phase control pulse PI, as in the first embodiment.
During the period when I is not input, the clock signal CK in the corrected phase state can be output.

Third Embodiment FIG. 10 is a logic circuit diagram of a clock oscillator circuit showing a third embodiment of the present invention. This clock oscillator circuit includes an input terminal IN for inputting a phase control signal S1 and a clock signal C.
One SR-connected between the output terminals out that outputs K
It has an FF 80 and two gates 81 and 82. SR
-The output terminal Q of the FF80 is connected to the output terminal out and one electrode of the second capacitor 83, and
2 is connected to the input side. The output side of the gate 82 is S
It is connected to the reset terminal R of the R-FF80. SR
-The inverting output terminal Q / of the FF80 is the first capacitor 8
4 is connected to one electrode and is also connected to the input side of the gate 81. The output side of the gate 81 is SR-FF
It is connected to the set terminal S of 80. Each gate 81,
An input terminal IN is commonly connected to the input side of 82. The other electrodes of the capacitors 83 and 84 are connected to the power source VC.
It is connected to C respectively. That is, SR-FF80
Is set when the logical product between the inverted level of the signal S1 and the level of the inverted clock signal CK / which is the second feedback signal is valid, and the level of the signal S1 and the clock signal which is the first feedback signal It is configured to be reset when the logical sum with the CK level is valid.

Next, the operation of the clock oscillator circuit of FIG. 10 will be described. This clock oscillation circuit also self-oscillates at a predetermined frequency after power is supplied, and outputs the clock signal CK having the self-oscillation frequency from the output terminal out. SR-F
The operation of F80 is the same as that of the SR-FF 20C of the first embodiment, and is omitted here. FIG. 11 is an output waveform diagram of the output terminal Q and the inverting output terminal Q / of FIG. Period from the time t _a ~t _c is an inverted clock signal CK / rise time outputted from the inverted output terminal Q /, the time t _c ~t _e clock signal C output from the output terminal Q
This is the rise time of K. The total of these rising times is the output time of one cycle of the clock oscillation circuit. If the phase control pulse PI is input during the period from time t _{a to} t _c and the phase control signal S1 becomes “H” level, SR-F
The phase of the output signal of F80 does not change. Time t _{c to} t
_{When the} phase control pulse PI is input during the period _e , the set terminal S is input with "L" level and the reset terminal R is input with "H" level. Therefore, the level of the output terminal Q falls toward "L" and the level of the inverting output terminal Q / rises toward "H" level. Therefore, the phase of the clock signal CK changes.

As described above, in the third embodiment, the clock signal CK and the inverted clock signal CK / are supplied to the gates 81 and 8
Since it is fed back to the SR-FF80 via 2, the total rising time of the output terminal Q and the inverting output terminal Q / becomes one cycle of free-running oscillation, and the free-running oscillation frequency becomes the output waveform. It is decided only by the rising edge, and a high-speed oscillation frequency can be obtained. Further, the free-running oscillation frequency can be arbitrarily set only by adjusting the capacitors 83 and 84. Further, a clock extraction circuit for extracting a clock signal synchronized with the data is constituted by the clock oscillation circuit of this embodiment and the data change point extraction circuit, and a change point detection signal output from the data change point extraction circuit is output. If the phase control pulse PI is input to the input terminal IN, the phase of the clock signal CK that is free-running oscillates.
Can be corrected so that the clock signal CK is output in the period in which the phase control pulse PI is not input.

Fourth Embodiment FIG. 12 is a logic circuit diagram of a clock oscillator circuit showing a fourth embodiment of the present invention. This clock oscillator circuit includes an input terminal IN for inputting a phase control signal S1 and a clock signal C.
One SR-connected between the output terminals out that outputs K
Equipped with FF90. The output terminal Q of the SR-FF 90 is connected to the output terminal out and the first inverting amplifier circuit 100, and the inverting output terminal Q / is connected to the second inverting amplifier circuit 110. The first inverting amplifier circuit 100 is for generating a first feedback signal, and the output terminal Y of the inverting amplifier circuit 100 is connected to one electrode of the first capacitor 121 and has a two-input gate. It is feedback-connected to one input terminal of 123. Second inverting amplifier circuit 110
Is for generating a second feedback signal, the output terminal Y / of the inverting amplifier circuit 110 is connected to one electrode of the second capacitor 122, and the two-input gate 124
It is feedback-connected to one of the input terminals. The other electrodes of the capacitors 121 and 122 are connected to the power supply VDD. The other input terminal of each of the gates 123 and 124 is connected to the input terminal IN.

The inverting amplifier circuit 100 is provided with a PMOS 101 and an NMOS 102 whose gates are connected to the output terminal Q of the clock signal CK in the SR-FF 90.
The drain of each PMOS 101 and the drain of the NMOS 102 are commonly connected to the output terminal Y. PMOS 10
The source of 1 is connected to one end of the constant current source 103, and the other end of the constant current source 103 is connected to the power supply VDD. N
The source of the MOS 102 is connected to the power supply VSS.
The inverting amplifier circuit 110 includes a PMOS 111 and an NMOS 112 whose gates are connected to an inverting output terminal Q / that outputs an inverted clock signal CK / in the SR-FF 90. The drain of each PMOS 111 and the NMOS 11
The drains of 2 are commonly connected to the output terminal Y /.
The source of the PMOS 111 is connected to one end of the constant current source 113, and the other end of the constant current source 113 is connected to the power supply VDD. The source of the NMOS 112 is connected to the power supply VSS.

Next, the operation of the clock oscillator circuit of FIG. 12 will be described. This clock oscillation circuit also self-oscillates at a predetermined frequency after power is supplied, and outputs the clock signal CK having the self-oscillation frequency from the output terminal out. SR-F
Clock signal CK output from the output terminal Q of F90
Is input to the inverting amplifier circuit 100 and the clock signal CK
The PMOS 101 and the NMOS 102 are complementarily turned on and off according to the level. As a result, the inverting amplifier circuit 10
From 0, the first feedback signal having the same frequency as the clock signal CK is output. The inverted clock signal CK / output from the inverting output terminal Q / is input to the inverting amplifier circuit 110, and the PMOS 111 and the NMOS 112 are complementarily turned on,
Turn off. As a result, the inverting amplifier circuit 110 outputs the second feedback signal having the same frequency as the inverted clock signal CK /. The rise times of the first and second output signals are lengthened by the capacitors 121 and 122, for example, and are transmitted to the gates 123 and 124, respectively. The SR-FF 90 is set or reset by the output of each gate 123, 124. Here, SR-FF90
Is set when the logical product between the inverted level of the signal S1 and the level of the first feedback signal is valid, and the logical sum between the level of the signal S1 and the level of the second feedback signal is valid. When reset. The operation of the SR-FF90 is the first
Since it is the same as the embodiment of FIG.

FIG. 13 is a waveform diagram showing the oscillation waveforms of the output terminals Y and Y / and the output waveform of the output terminal out of FIG. Period from the time t _a ~t _c is the rise time of the oscillation waveform at the output terminal Y /, the time t _c ~t _e is a rise time of the oscillation waveform at the output terminal Y. The total of these rising times is the output time for one cycle of the clock oscillation circuit. Third Embodiment of Clock Oscillation Circuit of this Embodiment
The clock oscillation circuits of the embodiments will be compared. In the third embodiment, the capacitor 83 is directly connected to the output terminal out to lengthen the rising time of the clock signal CK, and the gate 8
Returned to 2. In this embodiment, the capacitors 121,
Since 122 is not directly connected to the output terminal out, it does not affect the clock signal CK output from the output terminal out. Therefore, the fall time of the clock signal CK is shortened, and the duty ratio is improved to 50%. The phase control for the clock signal CK will be described. Time t _{a to} t _c
When the phase control pulse PI is input during the period of 1 and the phase control signal S1 becomes "H" level, the phase of the output signal of the SR-FF 90 does not change. When the phase control pulse PI is input during the period of time t _{c to} t _e , “L” level is input to the set terminal S and “H” level is input to the reset terminal R. Therefore, the level of the output terminal Q falls toward "L", and the level of the inverting output terminal Q / is "H".
Get up to the level. Therefore, the clock signal C
The phase of K changes.

As described above, since the clock oscillation circuit of the fourth embodiment is provided with the inverting amplifier circuits 100 and 110, the clock signal CK is output without being affected by the capacitor. Therefore, the duty ratio of the clock signal CK is improved. Also, since the total of the rising times of the output terminals Y and Y / is one cycle of free-running oscillation,
By adjusting the capacitance value of the capacitors 121 and 122,
An arbitrary free-running oscillation frequency can be obtained, and the clock signal CK having a high-speed oscillation frequency can be generated. Further, a clock extraction circuit for extracting a clock signal synchronized with the data is constituted by the clock oscillation circuit of this embodiment and the data change point extraction circuit, and a change point detection signal output from the data change point extraction circuit is output. Input terminal I as phase control pulse PI
If input to N, it is possible to correct the phase of the clock signal CK that is oscillating free-running so as to be synchronized with the phase control pulse PI. During the period when the phase control pulse PI is not input, the clock in the corrected phase state is input. The signal CK can be output.

Fifth Embodiment Generally, in the SR-FF, the set terminal S has an "H" level,
When the "H" level is input to the reset terminal R, the levels of the output terminal Q and the inverting output terminal Q / become indefinite.
If this happens, free-running oscillation may stop, so
We must avoid becoming indefinite. FIG. 14 is a logic circuit diagram of a clock oscillation circuit showing a fifth embodiment of the present invention. In this embodiment, an indefiniteness prevention circuit 130 is provided in the clock oscillation circuit of the first embodiment. The indefiniteness prevention circuit 130 includes a 2-input AND gate 131 and a 2-input OR gate 132. The output terminal Q and the inverting output terminal Q / of the SR-FF 20C are connected to the input terminal of the AND gate 131, and the output side of the AND gate 131 is connected to one input terminal of the OR gate 132. The other input terminal of the OR gate 132 is connected to the input terminal IN of the phase control signal S1, and the output side of the OR gate 132 is commonly connected to the input sides of the gates 20A and 20B.

When the clock oscillator circuit is also powered on, it oscillates free-running and outputs the clock signal CK having the free-running oscillation frequency from the output terminal out. SR-FF20
The operation in C is the same as that of the first embodiment, but when the levels of the output terminal Q and the inverting output terminal Q / are both at "H" level, the AND gate 131 outputs "H" level, The output of the OR gate 132 also becomes "H". Therefore, in the first embodiment, the same operation as in the case where the phase control is performed is performed, and the “H” level is not input to both the set terminal S and the reset terminal R of the SR-FF 20C. That is, the level of the clock signal output from the output terminal out does not become indefinite. As described above, in the fifth embodiment, the instability prevention circuit 130 is provided in the clock oscillator circuit of the first embodiment. Therefore, it is possible to realize the clock oscillating circuit which has the same effect as that of the clock oscillating circuit of the first embodiment and in which the level of the clock signal CK output from the output terminal out is not indefinite.

The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (1) In the first and second embodiments, the gate 20 of FIG.
Transistor 2 in SR-FF20 has the functions of A and 20B.
1 to 26, each gate 20A, 2
A section corresponding to 0B is separately provided, and a normal SR-FF20C is provided.
May be set and reset. (2) Capacitors 51, 52, 62, 72, 83, 8
Although the electrode of No. 4 is connected to the power supply VCC, the same structure as that of each of the above-described embodiments can be achieved even if it is connected to the power supply VEE.
Although the capacitors 121 and 122 are also connected to the power supply VDD, they may be connected to the power supply VSS. (3) In the clock oscillation circuits of the first to fifth embodiments,
Although only the clock signal CK is output from one output terminal out, it is also possible to output it in the form of a differential signal by using the inverted clock signal CK /. In this case, for example, an effective clock signal can be obtained with respect to noise due to fluctuations in the ground level.

(4) Both the transistors 21 and 22 in the first and second embodiments, both the gates 81 and 82, or the gates 123 and 124 in the third and fourth embodiments.
Although the phase control signal S1 is input to both of them, the phase control signal S1 may be input to either one of the transistor and the gate, and in that case also, the first to fourth embodiments described above. Each clock oscillation circuit of the above-mentioned functions similarly. Further, in the fifth embodiment, the output of the indefiniteness prevention circuit 130 is input to the gates 20A and 20B, but the same effect can be obtained by inputting the output to either one of the gates 20A and 20B. (5) Capacitor 51 in the first to fifth embodiments,
If the constant current source that charges and discharges the electric charges for 52, 62, 72, 83, 84, 121, 122 is controlled by the control voltage, the phase control can be performed by the phase control pulse PI.
In addition, it is possible to realize a voltage controlled oscillator circuit capable of controlling the oscillation frequency at high speed by the capacity of the capacitor and the control voltage. (6) In the fifth embodiment, an example is described in which the clock oscillation circuit of the first embodiment is provided with the indetermination prevention circuit 130, but the clock oscillation circuits of other embodiments are provided with the indetermination prevention circuit. Also, the same effect as that of the fifth embodiment can be expected.

[0035]

As described in detail above, according to the first to thirteenth inventions, the setting is made based on the logic between the first feedback signal and the second feedback signal fed back from the output side. And an SR which is reset and self-oscillates by the set and reset to generate a clock signal and an inverted clock signal.
The -FF is provided in the clock oscillation circuit, and the first and second capacitors that set the rising time or the falling time of the first and second feedback signals are provided. Therefore, the free-running oscillation cycle of the clock oscillation circuit can be determined only by the rising or falling of the clock signal and the inverted clock signal, and not only the phase control of the clock signal but also the capacitance value of the first and second capacitors can be determined. By changing the frequency, it is possible to realize a clock oscillation circuit capable of changing the frequency of the clock signal in a wide range of frequencies.

In the second to seventh inventions, the setting condition for setting and resetting in the SR-FF is defined by the inversion value and the phase of the logical product between the inverted level of the phase control signal and the level of the first feedback signal. Inverted value of the logical sum between the level of the control signal and the level of the second feedback signal, the inverted value of the logical product and the inverted value of the level of the second feedback signal, or the level of the first feedback signal Since the inversion value and the inversion value of the logical sum are used, a gate having a delay time is unnecessary and a high-speed clock oscillation circuit can be configured. According to the fifth to seventh inventions and the eleventh to thirteenth inventions, the first and second feedback signals are not the clock signals themselves, so that the first and second capacitors have a clock signal waveform. It is possible to realize a clock oscillation circuit having an excellent duty ratio without any influence. According to the fourteenth invention, the first to thirteenth inventions are provided.
Since a constant current source controlled based on a control voltage given from the outside is connected to each of the first and second capacitors in the clock oscillation circuit of the invention described above, phase control is possible and high frequency It is possible to realize a voltage controlled oscillator that oscillates at.

[Brief description of drawings]

FIG. 1 is a logic circuit diagram of a clock oscillation circuit showing a first embodiment of the present invention.

FIG. 2 is a logic circuit diagram showing a conventional clock oscillator circuit.

FIG. 3 is a circuit diagram showing a configuration of an inverter in FIG.

FIG. 4 is a diagram illustrating a previously proposed clock oscillation circuit.

5 is a circuit diagram showing FIG. 1 at a transistor level. FIG.

FIG. 6 is a diagram for explaining the operation of SR-FF20C and SR-FF20 in FIG.

7 is an output waveform diagram of the output terminal Q and the inverting output terminal Q / of FIG.

FIG. 8 is a circuit diagram of a clock oscillator circuit showing a second embodiment of the present invention.

9 is a waveform diagram showing one cycle of the oscillation waveforms of the nodes Na and Nb and the output waveform at the output terminal out in FIG.

FIG. 10 is a logic circuit diagram of a clock oscillator circuit showing a third embodiment of the present invention.

11 is an output waveform diagram of the output terminal Q and the inverting output terminal Q / of FIG.

FIG. 12 is a logic circuit diagram of a clock oscillator circuit showing a fourth embodiment of the present invention.

13 is a waveform diagram showing oscillation waveforms of output terminals Y and Y / and an output waveform of output terminal out in FIG.

FIG. 14 is a logic circuit diagram of a clock oscillator circuit showing a fifth embodiment of the present invention.

[Explanation of symbols]

20, 20C, 80, 90 SR-F
F 51, 52, 62, 72, 121, 122 First and second capacitors 61, 71 Emitter follower circuit 63, 73 First and second constant current source 100, 110 First and second inverting amplifier circuit Q Clock signal output terminal Q / Inverted clock signal output terminal S1 Phase control signal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shuichi Matsumoto 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (14)

[Claims] 1. A clock oscillating circuit that is phase-controlled based on a phase control pulse and frequency-controlled based on the capacitance value of a frequency setting capacitor to oscillate to self-oscillate and output a clock signal of the self-oscillating frequency. It is set and reset based on the logic between the phase control signal formed of the phase control pulse and the first feedback signal and the second feedback signal fed back from the output side, and self-oscillating by the set and reset. Set reset flip-flop for generating the clock signal and an inverted clock signal obtained by inverting the clock signal, a first capacitor for setting a rising time or a falling time of the first feedback signal, and the second feedback A second capacitor for setting a rising time or a falling time of a signal, Clock oscillation circuit the second feedback signal, characterized in that is constituted by a frequency signal corresponding to each of the clock signal and the inverted clock signal. 2. The first and second feedback signals are the clock signal and the inverted clock signal, respectively, and the first and second capacitors have fall times of the first and second feedback signals. The set-reset flip-flop is set when the inverted value of the logical product between the inverted level of the phase control signal and the level of the first feedback signal is valid, and the phase control signal is set. 2. The clock oscillation circuit according to claim 1, wherein the clock oscillation circuit is configured to be reset when the inversion value of the logical sum between the level of 1 and the level of the second feedback signal is valid. 3. The first and second feedback signals are the clock signal and the inverted clock signal, respectively, and the first and second capacitors have fall times of the first and second feedback signals. The set-reset flip-flop is set when the inverted value of the logical product between the level obtained by inverting the phase control signal and the level of the first feedback signal is valid, and the set-reset flip-flop is set by the second reset signal. 2. The clock oscillator circuit according to claim 1, wherein the clock oscillator circuit is reset when the inverted value of the level of the feedback signal is valid. 4. The first and second feedback signals are the clock signal and the inverted clock signal, respectively, and the first and second capacitors have fall times of the first and second feedback signals. The set-reset flip-flop is set when the inverted value of the level of the first feedback signal is valid, and is set between the level of the phase control signal and the level of the second feedback signal. 2. The clock oscillation circuit according to claim 1, wherein the clock oscillation circuit is configured to be reset when the inverted value of the logical sum is valid. 5. A first emitter follower circuit for generating the first feedback signal having the same frequency as the clock signal, and a second emitter follower circuit for generating the second feedback signal having the same frequency as the inverted clock signal. An emitter follower circuit and first and second constant current sources for discharging the electric charges of the first and second capacitors, respectively, the first and second capacitors being the first and second capacitors, respectively. When the fall time of the feedback signal is set, the set-reset flip-flop is effective when the inverted value of the logical product between the inverted level of the phase control signal and the level of the first feedback signal is effective. 7. A structure which is set and reset when an inverted value of a logical sum between the level of the phase control signal and the level of the second feedback signal is valid. Clock oscillation circuit described. 6. A first emitter follower circuit for generating the first feedback signal having the same frequency as the clock signal and a second emitter follower circuit for generating the second feedback signal having the same frequency as the inverted clock signal. An emitter follower circuit and first and second constant current sources for discharging the electric charges of the first and second capacitors, respectively, the first and second capacitors being the first and second capacitors, respectively. When the fall time of the feedback signal is set, the set-reset flip-flop is effective when the inverted value of the logical product between the inverted level of the phase control signal and the level of the first feedback signal is effective. 2. The clock oscillator circuit according to claim 1, wherein the clock oscillator circuit is set and reset when the inverted value of the level of the second feedback signal is valid. 7. A first emitter follower circuit for generating the first feedback signal having the same frequency as the clock signal and a second emitter follower circuit for generating the second feedback signal having the same frequency as the inverted clock signal. An emitter follower circuit and first and second constant current sources for discharging the electric charges of the first and second capacitors, respectively, the first and second capacitors being the first and second capacitors, respectively. The set-up and reset flip-flops are set when the inverted value of the level of the first feedback signal is effective, and the fall time of the feedback signal is set, and the level of the phase control signal and the second feedback are set. 2. The clock oscillator circuit according to claim 1, wherein the clock oscillator circuit is configured to be reset when an inverted value of a logical sum between the signal level and the signal level is valid. 8. The first and second feedback signals are the inverted clock signal and the clock signal, respectively, and the first and second capacitors have rise times of the first and second feedback signals, respectively. The set / reset flip-flop is set when the logical product between the inverted level of the phase control signal and the level of the second feedback signal is effective, and the set / reset flip-flop is set to the level of the phase control signal. 2. The clock oscillation circuit according to claim 1, wherein the clock oscillation circuit is configured to be reset when the logical sum with the level of the first feedback signal is valid. 9. The first and second feedback signals are the inverted clock signal and the clock signal, respectively, and the first and second capacitors have rise times of the first and second feedback signals, respectively. The set-reset flip-flop is set when the logical product between the level obtained by inverting the phase control signal and the level of the second feedback signal is valid, and the level of the first feedback signal is set. 2. The clock oscillation circuit according to claim 1, wherein the clock oscillation circuit is reset when is valid. 10. The first and second feedback signals are the inverted clock signal and the clock signal, respectively, and the first and second capacitors have rise times of the first and second feedback signals, respectively. The set-reset flip-flop is set when the level of the second feedback signal is valid, and the logical sum between the level of the phase control signal and the level of the first feedback signal is valid. 2. The clock oscillator circuit according to claim 1, wherein the clock oscillator circuit is configured to be reset at any time. 11. A first inverting amplifier circuit having a CMOS transistor for generating the first feedback signal based on the clock signal, and a second inverting amplifier circuit having a CMOS transistor and based on the inverted clock signal. A second inverting amplifier circuit for generating the second inverting amplifier circuit, the first and second capacitors are configured to set rise times of the first and second feedback signals, respectively, and the set-reset flip-flop is configured to control the phase. It is set when the logical product between the inverted level of the control signal and the level of the first feedback signal is valid, and the logical sum between the level of the phase control signal and the level of the second feedback signal is 2. The clock oscillator circuit according to claim 1, wherein the clock oscillator circuit is configured to be reset when it is valid. 12. A first inverting amplifier circuit having a CMOS transistor for generating the first feedback signal based on the clock signal, and a second inverting amplifier circuit having a CMOS transistor and based on the inverted clock signal. A second inverting amplifier circuit for generating the second inverting amplifier circuit, the first and second capacitors are configured to set rise times of the first and second feedback signals, respectively, and the set-reset flip-flop is configured to control the phase. It is set when the logical product between the inverted level of the control signal and the level of the first feedback signal is valid, and is reset when the level of the second feedback signal is valid. The clock oscillation circuit according to claim 1. 13. A first inverting amplifier circuit having a CMOS transistor for generating the first feedback signal based on the clock signal, and a second inverting amplifier circuit having a CMOS transistor and based on the inverted clock signal. And a second inverting amplifier circuit for generating the second inverting amplifier circuit, the first and second capacitors are configured to set rise times of the first and second feedback signals, respectively, and the set-reset flip-flop is The configuration is such that it is set when the level of the feedback signal of 1 is valid, and reset when the logical sum between the level of the phase control signal and the level of the second feedback signal is valid. The clock oscillator circuit according to item 1. 14. Claims 1, 2, 3, 4, 5, 6, 7,
For the first and second capacitors in the clock oscillation circuit according to 8, 9, 10, 11, 12, or 13,
A voltage controlled oscillator circuit characterized in that a constant current source for supplying charge / discharge charges based on a control voltage given from the outside is connected to each other and oscillates at a frequency corresponding to the control voltage.