JPH08236717A - Method of fabrication of semiconductor device - Google Patents

Abstract

PURPOSE: To form the capacitance of a DRAM with a finer area than those of conventional DRAMs wherein there is no misaligning and an inner wall of a capacitor electrode concave part useable as the capacitor to ensure a large area by forming the capacitor electrode self-aligningly at a portion of a connection hole for forming the capacitor electrode. CONSTITUTION: After a capacitor electrode forming connection hole 21 is formed, polycrystalline silicon is formed with sufficiently thinner film thickness than an opening radius of the capacitor electrode forming connection hole. A concave part is formed in a part of the capacitor electrode forming connection hole, and a BPSG film is formed only on the concave part in a self alignment manner. The polycrystalline silicon is etched using the BPSG film as an etching mask to form a capacitor electrode in the capacitor electrode forming connection hole in a self alignment manner. After removal of the BPSG film, a capacitor oxide film 28 and an opposite electrode 29 are formed, and a capacitor is formed on an inner wall of a concave part in the capacitor electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a random access memory (hereinafter referred to as DRAM).
Described)).

[0002]

2. Description of the Related Art A conventional method of manufacturing a semiconductor device having a DRAM will be described with reference to the sectional views of FIGS.

As shown in FIG. 18, a P-type semiconductor substrate 1
A field oxide film 12 is formed in the element isolation region above 1. After that, a gate oxide film 13 of silicon oxide is formed by a thermal oxidation process. After that, the gate electrode 14 made of polycrystalline silicon is formed by a chemical vapor deposition method (hereinafter referred to as a CVD method). After that, the gate electrode 14 and the gate oxide film 13 are patterned by a photoetching process.

Next, as shown in FIG. 19, the semiconductor substrate 1 in which the gate electrode 14 and the field oxide film 12 are aligned with each other.
Impurities are introduced into the substrate 1 by the ion implantation method to form the high concentration diffusion region 15. After that, the first interlayer insulating film 1 made of silicon oxide containing phosphorus and boron is formed by the CVD method.
6 is formed.

Next, as shown in FIG. 20, a connection hole 21 for forming a capacitance electrode is formed in the first interlayer insulating film 16 by a photoetching process. Then, the polycrystalline silicon 22 is formed by the CVD method.

Next, as shown in FIG. 21, a photo-etching step is performed to pattern the polycrystalline silicon 22 and form a capacitor electrode 26.

Next, as shown in FIG. 22, a thermal oxidation process is performed to form a capacitive oxide film 2 made of silicon oxide.
8 is formed on the surface of the capacitor electrode 26. After that, the counter electrode 29 made of polycrystalline silicon is formed on the entire surface, and the counter electrode 29 is patterned by a photoetching process.

Next, as shown in FIG. 23, a second interlayer insulating film 27 made of silicon oxide containing phosphorus and boron is formed by the CVD method.

After that, heat treatment is performed in a nitrogen atmosphere,
A so-called reflow process is performed to fluidize the second interlayer insulating film 27 to flatten the surface of the second interlayer insulating film 27, and at the same time, activate the impurities in the high concentration diffusion region 15 formed by the ion implantation process. Turn into.

After that, a connection hole 17 is formed in the first interlayer insulating film 16 and the second interlayer insulating film 27 by a photoetching process. After that, the wiring 18 made of aluminum is formed on the entire surface by a sputtering method, and the wiring 1
8 is formed into a predetermined shape by a photoetching process.

[0011]

The method of forming a semiconductor device described with reference to FIGS. 18 to 23 requires a photolithography process for forming the capacitor electrode 26 of the DRAM, and requires a design that allows for misalignment. This must be done, and there is a limit to the miniaturization of semiconductor devices.

Further, in order to secure the capacitance value, the capacitance electrode 26 is larger than the area of the capacitance electrode forming connection hole 21,
It is necessary to increase the surface area, and it is difficult to miniaturize the recoil transmission device.

An object of the present invention is to solve the above problems, to eliminate misalignment when forming a capacitor electrode, to reduce the area of the capacitor, and to form a DRAM capacitor suitable for miniaturization. Is to provide.

[0014]

In order to achieve the above object, the method of forming a semiconductor device of the present invention employs the following steps.

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a field oxide film in an element isolation region on a semiconductor substrate, a step of forming a gate oxide film and a gate electrode,
A step of forming a high-concentration diffusion region on the semiconductor substrate in which the gate electrode and the field oxide film are aligned; a step of forming a first interlayer insulating film and a nitride film on the entire surface; A step of forming a connection hole for forming a capacitance electrode in the insulating film and the nitride film, a step of forming polycrystalline silicon and forming a recess in a connection hole portion for forming a capacitance electrode, a BPSG film is formed, and this BPSG is formed. A step of filling the film in the recess, a step of etching the BPSG film to leave the BPSG film only in the recess in a self-aligned manner, and a step of etching the polycrystalline silicon using the BPSG film left in the recess as an etching mask to form a capacitor electrode connection A step of forming a capacitive electrode in the hole portion, a step of removing the BPSG film and then a nitride film, and a step of forming a capacitive oxide film on the capacitive electrode, The counter electrode was formed on the surface by photoetching step, the step of patterning the counter electrode,
A step of forming a second interlayer insulating film on the entire surface, a step of performing heat treatment to activate impurities in the high concentration diffusion region,
The method is characterized by including a step of forming connection holes in the first interlayer insulating film and the second interlayer insulating film by a photoetching step, and a step of forming wiring.

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a field oxide film in an element isolation region on a semiconductor substrate, a step of forming a gate oxide film and a gate electrode,
A step of forming a high-concentration diffusion region on the semiconductor substrate in which the gate electrode and the field oxide film are aligned; a step of forming a first interlayer insulating film and a nitride film on the entire surface; A step of forming a connection hole for forming a capacitance electrode in the insulating film and the nitride film, a step of forming polycrystalline silicon and forming a recess in the connection hole portion for forming a capacitance electrode, and a SOG on the entire surface by a spin coating method. Formed,
The step of filling the concave portion with SOG, the step of etching the SOG and leaving the SOG only in the concave portion in a self-aligned manner, the step of etching the polycrystalline silicon with the SOG left in the concave portion as an etching mask, and forming the connecting hole portion for forming the capacitor electrode The steps of forming a capacitor electrode, removing SOG, and then removing the nitride film, forming a capacitor oxide film on the capacitor electrode, forming a counter electrode on the entire surface, and performing a photoetching process, A step of patterning the counter electrode, a step of forming a second interlayer insulating film on the entire surface, a step of performing heat treatment to activate impurities in the high-concentration diffusion region, and a photo-etching step for the first interlayer insulating film. The method is characterized by including a step of forming a connection hole in the film and the second interlayer insulating film and a step of forming a wiring.

[0017]

According to the method of manufacturing a semiconductor device of the present invention, the capacitance electrode of the DRAM is formed with a film thickness smaller than the radius of the capacitance electrode forming connection hole, whereby the capacitance electrode is formed in a concave shape and self-aligned with the concave portion. Embedded BPSG film or S
Using the OG as an etching mask, the capacitor electrode is patterned in the contact hole for forming the capacitor electrode in a self-aligned manner.

Therefore, there is no misalignment between the capacitance electrode and the connection hole for forming the capacitance electrode, and it is not necessary to design in consideration of the misalignment, so that miniaturization is possible.

Furthermore, since the capacitor electrode is formed in a concave shape and the capacitor is formed inside this recess, the surface area can be increased and a large capacitor can be formed in the area of the connection hole for forming the capacitor electrode. Therefore, there is no misalignment, a sufficiently large capacitance can be formed in the area of the connection hole for forming the capacitance electrode, and a finer semiconductor device than before can be formed.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. Introduction Figure 1 to Figure 1
A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIG. 1 to 11 are sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

As shown in FIG. 1, a P-type semiconductor substrate 11 is provided.
A 150 nm-thickness silicon nitride film (not shown) is formed on the entire surface by CVD. After that, a photosensitive resin (not shown) is formed on the entire surface by a spin coating method, exposed using a predetermined photomask, and developed to pattern the photosensitive resin on the element region.

Thereafter, using this photosensitive resin as an etching mask and using carbon tetrafluoride as an etching gas, silicon nitride is patterned in the element region by a reactive ion etching method (hereinafter referred to as RIE) to form an antioxidant film. (Not shown), and then the photosensitive resin is removed.

After that, the semiconductor substrate 11 having an anti-oxidation film matched thereto is heated to a temperature of 1000 in an oxygen atmosphere containing water vapor.
Heat treatment at ℃ for 105 minutes to form silicon oxide,
A field oxide film 12 of silicon oxide having a film thickness of 550 nm is formed in the element isolation region by so-called selective oxidation.
Then, the antioxidant film is removed with phosphoric acid heated to a temperature of 180 ° C.

Next, as shown in FIG. 2, a heat treatment at a temperature of 1000 ° C. is performed for 12 minutes in an oxygen atmosphere to form a gate oxide film of 20 nm in thickness made of silicon oxide on the semiconductor substrate 11 matching the field oxide film 12. 13 is formed.

After that, monosilane is used as a reactive gas and the gate electrode 1 having a film thickness of 350 nm is formed by the CVD method.
4 is formed on the entire surface. Then, a photosensitive resin (not shown)
Is formed on the entire surface by a spin coating method, is exposed using a photomask, is developed, and a photosensitive resin is patterned on the gate electrode formation region.

After that, the gate electrode 14 is formed by RIE using sulfur hexafluoride as an etching gas with this photosensitive resin as an etching mask, and the gate oxide film 13 is patterned with hydrofluoric acid to remove the photosensitive resin. Remove.

Next, as shown in FIG. 3, the gate electrode 1
4 and the field oxide film 12 are aligned in the semiconductor substrate 11
Arsenic is ion-implanted under the conditions of an acceleration energy of 60 keV and an ion implantation amount of 3.0 × 10 ¹⁵ atoms / cm ² to form a high concentration diffusion region 15.

Then, CVD is performed using monosilane, phosphine, diborane, oxygen and nitrogen as reactive gases.
By the method, the first interlayer insulating film 16 of silicon oxide containing 700 nm thick phosphorus and boron is formed.

Then, a film thickness of 20 is obtained by a CVD method using dichlorosilane and ammonia as reactive gases.
A nitride film 30 made of 0 nm silicon nitride is formed. This nitride film 30 will be formed in a subsequent step.
It is used as an etching stopper for forming the capacitive electrode.

Next, as shown in FIG. 4, a photosensitive resin (not shown) is formed on the entire surface, exposed and developed using a photomask, and the photosensitive resin is opened in the formation area of the connection hole 21 for forming the capacitance electrode. Pattern so that

Then, the nitride film 30 is etched by RIE using the photosensitive resin as an etching mask and carbon tetrafluoride as an etching gas.
The first interlayer insulating film 16 is etched by RIE using methane trifluoride as an etching gas using the photosensitive resin as an etching mask. After that, the photosensitive resin is removed, and the capacitor electrode forming connection hole 2 having an opening diameter of 0.8 μm is formed.
1 is formed.

Next, as shown in FIG. 5, phosphine and monosilane are used as reactive gases, and a polycrystalline silicon 2 containing phosphorus having a film thickness of 100 nm is formed by a CVD method.
2 is formed on the entire surface, and a recess 23 is formed in the connection hole 21 portion for forming the capacitance electrode.

Here, the film thickness of the polycrystalline silicon 22 is formed to be sufficiently smaller than 0.4 μm which is the opening radius of the connection hole 21 for forming the capacitance electrode. When a film thickness larger than the film thickness of the opening radius of the capacitance electrode forming connection hole 21 is formed, the polycrystalline silicon 22 is embedded in the capacitance electrode forming connection hole 21 and the recess 23 is not formed. The surface area of the capacitive electrode in the capacitive electrode forming connection hole 21 to be formed cannot be obtained.

Next, as shown in FIG. 6, silicon oxide containing phosphorus and boron having a film thickness of 500 nm was formed by a CVD method using monosilane, phosphine, diborane, oxygen and nitrogen as reactive gases. The BPSG film 24 is formed.

The film thickness of the BPSG film 24 is sufficiently thicker than 300 nm obtained by subtracting 100 nm of the polycrystalline silicon 22 from 0.4 μm of the opening radius of the connection hole 21 for forming the capacitor electrode. The recess 23 portion of the polycrystalline silicon 22 formed in the formation connection hole 21 portion is formed in the BPSG film 2
Embed with 4.

Therefore, the BPSG film 2 in the concave portion 23 is formed.
In addition to the film thickness of the BPSG film 24 of 500 nm,
The total thickness of the first interlayer insulating film 16 and the nitride film 30 is 900 nm, and the film thickness is about 1.4 μm.

Next, as shown in FIG. 7, BPS was performed by RIE using methane trifluoride as an etching gas.
The G film 24 is etched to a thickness of 600 nm.

In this etching process of the BPSG film 24, the BPSG film 24 other than the recess 23 is etched, but the thickness of the BPSG film 24 in the recess 23 is 1.4 μm.
Since it is about m, the BPSG film 24 remains in a self-aligned manner.
Further, the selection ratio between the BPSG film 24 and the underlying polycrystalline silicon 22 is large. Therefore, the polycrystalline silicon 22 is hardly etched.

Next, as shown in FIG.
Using the PSG film 24 as an etching mask, the polycrystalline silicon 22 is etched by RIE using hexafluoride as an etching gas to form a capacitor electrode 26.

By this etching process of the polycrystalline silicon 22, a sufficient selection ratio between the BPSG film 24 and the polycrystalline silicon 22 is obtained, but the nitride film 30 and the polycrystalline silicon 22 formed below the polycrystalline silicon 22 are Since a sufficient selection ratio cannot be obtained, control the time and
Etch 2.

The capacitance electrode 26 has a connection hole 2 for forming a capacitance electrode.
Since it is formed in 1 in a self-aligning manner, there is no misalignment with the connection electrode hole 21 for forming the capacitance electrode.

Next, as shown in FIG. 9, the BPSG film 24 is removed with hydrofluoric acid. Since the nitride film 30 formed as an etching stopper covers the first interlayer insulating film 16, the first interlayer insulating film 16 is not etched and only the BPSG film 24 can be removed. Then, the nitride film 30 is removed with phosphoric acid heated to a temperature of 180 ° C.

Next, as shown in FIG. 10, a heat treatment is performed at a temperature of 800 ° C. for 30 minutes in an oxygen atmosphere to which water vapor is added to obtain a capacitive oxide film 2 made of silicon oxide having a film thickness of 20 nm.
8 is formed on the capacitance electrode 26.

Then, using phosphine and monosilane as reactive gases, a film thickness of 300 n is obtained by the CVD method.
Counter electrode 29 made of polycrystalline silicon containing m of phosphorus
Is formed on the entire surface.

After that, a photosensitive resin (not shown) having a film thickness of 1.1 μm is formed on the entire surface by a spin coating method, exposed using a predetermined photomask, and developed to perform a counter electrode forming region of the DRAM capacitor. The photosensitive resin is patterned on the top.

Then, the photosensitive resin is removed by RIE using the photosensitive resin as an etching mask and sulfur hexafluoride as an etching gas.

Since the capacitance of this DRAM can be formed on the concave inner surface of the capacitance electrode 26 formed in the capacitance electrode forming connection hole 21, a comparatively large area can be obtained in the capacitance electrode forming connection hole 21. Suitable for miniaturization.

Next, as shown in FIG. 11, a silicon oxide containing 700 nm thick phosphorus and boron was formed by a CVD method using monosilane, phosphine, diborane, oxygen and nitrogen as reactive gases. Second interlayer insulating film 2
Form 7.

After that, a heat treatment at a temperature of 900 ° C. is performed for 30 minutes in a nitrogen atmosphere to fluidize the second interlayer insulating film 27, that is, so-called reflow is performed to perform the second interlayer insulating film 27.
At the same time as planarizing the surface of, the impurities of the high concentration diffusion region 15 formed by ion implantation are activated.

Next, a photosensitive resin (not shown) having a film thickness of 1.1 μm is formed on the entire surface, exposed and developed using a predetermined photomask, and the photosensitive resin is patterned so that only the connection hole forming region is opened. To do.

After that, the first interlayer insulating film 16 and the second interlayer insulating film 27 are etched by RIE by using a photosensitive resin as an etching mask and using methane trifluoride as an etching gas. The resin is removed and the connection hole 17 is formed.

Thereafter, the film thickness is 1 μm by the sputtering method.
The wiring 18 made of aluminum of m is formed on the entire surface.
After that, a photosensitive resin (not shown) having a film thickness of 1.6 μm is formed on the entire surface by a spin coating method, exposed by using a predetermined photomask, and developed, and the photosensitive resin is formed on a region where the wiring 18 is formed. Pattern.

After that, the wiring 18 is patterned by RIE using boron trichloride and methane trichloride as an etching gas with the photosensitive resin as an etching mask, and the wiring 18, the high concentration diffusion region 15, the wiring 18 and the gate are formed. The electrode 14, the wiring 18 and the counter electrode 29 are connected.
Then, the photosensitive resin is removed.

A method of manufacturing a semiconductor device according to the present invention is a DRA.
Since the capacitance electrode 26 is formed in the M capacitance electrode forming connection hole 21 in a self-aligning manner, there is no misalignment.

Further, the capacitor electrode 26 is formed in a concave shape in the capacitor electrode forming connection hole 21, and the inner wall portion thereof can also be used as a capacitor. Therefore, the surface area can be sufficiently increased by the area of the connection hole 21 for forming the capacitance electrode, and a finer semiconductor device than the conventional one can be formed.

Next, a method of manufacturing a semiconductor device according to another embodiment of the present invention will be described. In the second embodiment described below, the same effect as the first embodiment can be obtained.

A method of manufacturing a semiconductor device according to the second embodiment of the present invention will be described below with reference to FIGS. 12 to 17 are cross-sectional views showing a method of manufacturing a semiconductor device according to the embodiment of the present invention in the order of steps.

As shown in FIG. 12, the field oxide film 12 is formed in the element isolation region on the P type semiconductor substrate 11 by the same process as in the first embodiment, and the gate oxide film 1 is formed.
3 and the gate electrode 14 are formed, and the field oxide film 12 is formed.
And the gate electrode 14, the high-concentration diffusion region 15 is formed in the semiconductor substrate 11, the first interlayer insulating film 16 and the nitride film 30 are formed, and the first interlayer insulating film 16 and the nitride film 30 are formed. A connection hole 21 for forming a capacitance electrode is formed in the and, and a polycrystalline silicon 22 and a recess 23 are further formed.

Next, as shown in FIG. 13, a solution in which a silicon compound is dissolved in an organic solvent, so-called SOG25, is formed on the entire surface to a film thickness of 300 nm by a spin coating method.

Since the liquid SOG 25 is formed by the spin coating method, the surface of the SOG 25 has a smooth shape, the SOG 25 in the concave portion 23 becomes thick, and the SOG 2 is formed.
In addition to the film thickness of 300 nm in the flat portion of No. 5, the total film thickness of the first interlayer insulating film 16 and the nitride film 30 is 900 nm.
Then, the film thickness becomes about 1.2 μm.

After that, heat treatment is performed in a nitrogen atmosphere at a temperature of 320 ° C. to evaporate the solvent of SOG25,
To sinter.

Next, as shown in FIG. 14, RIE using methane trifluoride as an etching gas was performed to remove S.
The OG25 is etched to a thickness of 400 nm to reduce the thickness.

At this time, the SOG 25 in the flat portion is etched, but the film thickness of the SOG 25 in the concave portion 23 is 1.2.
Since the thickness is about μm, the SOG 25 remains in a self-aligned manner, and since the selection ratio between the SOG 25 and the underlying polycrystalline silicon 22 is large, the polycrystalline silicon 22 is hardly etched.

Next, as shown in FIG.
The polycrystalline silicon 22 is etched by RIE using OG25 as an etching mask and hexafluoride as an etching gas to form a capacitor electrode 26.

By etching the polycrystalline silicon 22,
A sufficient selection ratio between the SOG 25 and the polycrystalline silicon 22 can be obtained, but a sufficient selection ratio between the nitride film 30 formed in the lower layer of the polycrystalline silicon 22 and the polycrystalline silicon 22 cannot be obtained. Therefore, the polycrystalline silicon 2
Etch 2.

The capacitance electrode 26 has a connection hole 2 for forming a capacitance electrode.
Since it is formed in 1 in a self-aligning manner, there is no misalignment with the connection electrode hole 21 for forming the capacitance electrode.

Next, as shown in FIG. 16, the SOG 25 is removed with hydrofluoric acid. The nitride film 30 formed as an etching stopper is used as the first interlayer insulating film 16
Therefore, the first interlayer insulating film 16 is not etched and only the BPSG film 24 can be removed. Then, the nitride film 30 is removed with phosphoric acid heated to a temperature of 180 ° C.

Next, as shown in FIG. 17, the same process steps as those of the first embodiment are performed to form a capacitive oxide film 28 on the capacitive electrode 26, and a counter electrode 29 and a second interlayer insulating film 27.
And the connection hole 17 and the wiring 18 are formed.

In the method of manufacturing a semiconductor device according to the second embodiment of the present invention, similarly to the first embodiment, the capacitance electrode 26 is self-aligned in the connection hole 21 for forming the capacitance electrode of the DRAM.
There is no misalignment because it is formed.

Further, since the capacitance electrode 26 is formed in a concave shape in the capacitance electrode forming connection hole 21 and the inner wall thereof can also serve as a capacitance, the surface area can be sufficiently increased by the area of the capacitance electrode forming connection hole 21. Thus, a finer semiconductor device can be formed than before, and the same effects as those of the first embodiment can be obtained in the first embodiment.

[0071]

As is clear from the above description, in the method of manufacturing a semiconductor device of the present invention, since the capacitor electrode is formed in the capacitor electrode forming connection hole of the DRAM in a self-aligning manner, the capacitor electrode forming connection hole is not formed. There is no misalignment with the capacitive electrode. Furthermore, since the capacitor electrode is formed in a concave shape in the capacitor electrode forming connection hole, and the inner wall thereof can also be used as a capacitor, the capacity can be sufficiently increased by the area of the capacitor electrode forming connection hole, and a semiconductor device finer than conventional ones can be obtained. Can be formed.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the embodiment of the invention.

FIG. 3 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the embodiment of the invention.

FIG. 4 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the embodiment of the invention.

FIG. 5 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 6 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor device in the example of the present invention.

FIG. 8 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 9 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 10 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 11 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 12 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 13 is a cross-sectional view showing the method for manufacturing the semiconductor device in the example of the present invention.

FIG. 14 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 15 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 16 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 17 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 18 is a cross-sectional view showing the method of manufacturing the semiconductor device in the conventional example.

FIG. 19 is a cross-sectional view showing the method of manufacturing the semiconductor device in the conventional example.

FIG. 20 is a cross-sectional view showing the method of manufacturing the semiconductor device in the conventional example.

FIG. 21 is a cross-sectional view showing the method of manufacturing the semiconductor device in the conventional example.

FIG. 22 is a cross-sectional view showing the method of manufacturing the semiconductor device in the conventional example.

FIG. 23 is a cross-sectional view showing the method of manufacturing the semiconductor device in the conventional example.

[Explanation of symbols]

 11 Semiconductor Substrate 12 Field Oxide Film 13 Gate Oxide Film 14 Gate Electrode 15 High Concentration Diffusion Region 16 First Interlayer Insulating Film 17 Connection Hole 18 Wiring 21 Capacitor Electrode Forming Connection Hole 22 Polycrystalline Silicon 23 Recess 24 BPSG Film 25 SOG 26 Capacitance electrode 27 Second interlayer insulating film 28 Capacitance oxide film 29 Counter electrode 30 Nitride film

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 27/04 21/822

Claims (2)

[Claims] 1. A step of forming a field oxide film in an element isolation region on a semiconductor substrate to form a gate oxide film and a gate electrode, and a high-concentration diffusion region in a semiconductor substrate in which the gate electrode and the field oxide film are aligned with each other. And a step of forming a first interlayer insulating film and a nitride film on the entire surface and forming a capacitor electrode forming connection hole in the first interlayer insulating film and the nitride film by a photoetching step. , A step of forming polycrystalline silicon and forming a concave portion in the connection hole portion for forming the capacitor electrode, a step of forming a BPSG film and filling the concave portion with the BPSG film, and a step of etching the BPSG film,
A step of leaving the BPSG film only in the concave portion in a self-aligned manner, a step of etching the polycrystalline silicon using the BPSG film left in the concave portion as an etching mask to form a capacitive electrode in the connection hole portion for capacitive electrode formation, and a BPSG film After that, the step of removing the nitride film, the step of forming the capacitive oxide film on the capacitive electrode, the step of forming the counter electrode on the entire surface, and the step of patterning the counter electrode by the photoetching step, The step of forming the second interlayer insulating film, the step of performing heat treatment to activate the impurities in the high-concentration diffusion region, and the step of photoetching the first interlayer insulating film and the second interlayer insulating film.
2. A method of manufacturing a semiconductor device, comprising: a step of forming a connection hole in the interlayer insulating film and the step of forming a wiring. 2. A step of forming a field oxide film in an element isolation region on a semiconductor substrate, a step of forming a gate oxide film and a gate electrode, and a high concentration on a semiconductor substrate in which the gate electrode and the field oxide film are aligned. A step of forming a diffusion region, a step of forming a first interlayer insulating film and a nitride film on the entire surface, and a photoetching step are performed to form a capacitor electrode forming connection hole in the first interlayer insulating film and the nitride film. Forming step, forming polycrystalline silicon, forming a concave portion in the connection hole portion for forming the capacitor electrode, and applying S by spin coating method.
A step of forming OG on the entire surface and filling the recess with SOG,
SOG is etched, and SOG is self-aligned only in the recesses.
, A step of etching the polycrystalline silicon using the SOG left in the recess as an etching mask to form a capacitor electrode in the capacitor electrode forming connection hole, and removing the SOG,
After that, a step of removing the nitride film, a step of forming a capacitive oxide film on the capacitive electrode, a step of forming a counter electrode on the entire surface, and a step of patterning the counter electrode by a photoetching step, and a second step on the entire surface. A step of forming an interlayer insulating film, a step of performing heat treatment to activate impurities in the high-concentration diffusion region, and a photoetching step are performed to form connection holes in the first interlayer insulating film and the second interlayer insulating film. Forming process,
And a step of forming a wiring.