JPH08235893A - Semiconductor memory - Google Patents

Abstract

PURPOSE: To improve a column relief rate while suppressing a chip area from increasing by providing standby column decoders performing decodings while receiving a column address along with decoder outputs from standby row decoders. CONSTITUTION: This semiconductor memory is of a chip structure in which an integration degree is raised by making one piece of column decoder select cell arraies equal to or more than four pieces of cell arraies and has a column redundant circuit 30. Standby row decoders 31, 32 of the circuit 30 perform decodings by receiving row address for performing selections for plural cell arraies and standby column decoders 33, 34 perform decodings by receiving a row address along with outputs from standby row decoders 31, 32. An OR gate OG ORs both outputs of standby column decoders 33, 34 to output it to one line of a standby column selection line. Moreover, when the address corresponding to a normal bit is inputted to a column detector CD, the output of the column decoder CD is supplied to a column selection line as a column selection signal via a NOR gate NG.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory (D
RAM) redundant circuit.

[0002]

2. Description of the Related Art In recent years, with the increase in capacity and integration of DRAMs, many chip configurations have been adopted in which circuits are shared by using multilayer wiring. FIG. 6 shows a pattern layout of a chip structure in a conventional DRAM.
That is, the memory cell array has four cell arrays AL1 to A1.
It is divided into L4, and a column decoder CD and a sense amplifier (not shown) are provided for each of the cell arrays AL1 to AL4.

However, as the capacity of the memory increases, the number of divisions of the memory cell array must be increased, and if the column decoder CD is provided for each cell array as in the chip configuration of FIG. 6, the chip area increases, The degree of integration does not increase.
Therefore, the number of wiring layers has been further increased, and as shown in FIG. 7, a column decoder CD, a sense amplifier, and the like have been gathered in one place, and a chip configuration having a pattern layout with a high degree of integration has been widely adopted. When the column decoder CD, the sense amplifier, and the like are gathered in one place in this way, there are two circuit methods shown in FIG. 8 or FIG.

In the circuit system shown in FIG. 8, the additional wiring layer is added to the column selection line CDL output from the column decoder CD.
, And the column select lines CDL are assigned to each cell array A.
L1 and AL2 are provided in common on each cell array AL1,
AL2 ... column select transistors (CT1, / CT1),
It is used to select (CT2, / CT2) .... here,
(BL1, / BL1), (BL2, / BL2) ... Are column line pairs of each cell array AL1, AL2 ..., (DQ1, / DQ).
1), (DQ2, / DQ2) ... are each cell array AL1,
It is a common data line pair of AL2 .... The column selection lines CDL ... Are provided in parallel with the column line pairs (BL1, / BL1), (BL2, / BL2) ... Of the cell arrays AL1, AL2.

In the circuit system shown in FIG. 9, the increased number of wiring layers is assigned to the second column line pair (BL ", / BL") ... And the second column line pair (BL ", , / BL ″) are provided in common on each cell array AL1, AL2, ... And this is provided on one side of the first column selection transistors (CT1, / CT1), (CT2, / CT2), ... Of each cell array AL1, AL2. To the second column select transistor (C
T ″, / CT ″) ... Connect to one end side. Then, the other end side of the second column selection transistors (CT ″, / CT ″) ... Is connected to the common data line pair (DQ ″, / DQ ″),
The column selection lines CDL ... Which are output from the column decoder CD are used to select the second column selection transistors (CT ″, / CT ″). The first column selection transistors (CT1, / CT1), (CT2, / CT2) ... Are selected by the cell array selection row address. Further, the second column line pair (BL ″, / BL ″) is the first column line pair (BL1, / BL) of each cell array AL1, AL2 ...
1), (BL2, / BL2) ...

On the other hand, in recent DRAMs, a defect of several bits to several K bits is relieved by replacing it with a spare bit (memory cell) provided as a spare, and a defective chip is repaired (replaced with a good product). It has a redundant circuit for This redundant circuit replaces a row line or a column line to which a defective bit is connected in order to replace a defective bit with another bit provided as a spare.
This is means for replacing the row line or the column line with a spare row line or column line provided in the same cell array. For example, in the case of replacing a column line, a column redundancy circuit includes a fuse element group in a column decoder section necessary for selecting a column line, and by cutting a predetermined fuse element, a defective bit is input when a column address corresponding to the defective bit is input. It replaces with a spare column line without selecting.
Similarly, a row redundancy circuit for replacing a row line is provided with a fuse element group in a row decoder section necessary for selecting a row line, and by cutting a predetermined fuse element, a row address corresponding to a defective bit is input. The defective bit is replaced with a spare row line without selecting it.

FIG. 10 shows a part of a conventional column decoder section. That is, CD is a normal column decoder, NG is a NOR gate inserted at the output side of the column decoder CD, and CDL.
Is a column select line to which a column select signal is applied via the NOR gate NG, 100 is a column redundancy circuit, and SCDL is a spare column select line to which a spare column select signal is supplied from the column redundant circuit 100, and a spare memory cell (see FIG. A spare column line (not shown) to which a not shown) is connected is selected.

In the column redundancy circuit 100, the SCD is a programmable column decoder (spare column decoder) having a fuse element group and receives a column address. In the spare column decoder SCD, when there is a defective bit, the fuse element is blown in advance so that the spare column decoder SCD has a circuit connection for decoding the column address corresponding to the defective bit.

When the column address corresponding to the normal bit is input to the column decoder section, the output of the normal column decoder CD is supplied to the column selection line as a column selection signal via the NOR gate NG. At this time, the output of the spare column decoder SCD is inactive. On the other hand, when the column address corresponding to the defective bit is input, the spare column decoder SCD
Is activated and supplied to the spare column selection line as a spare column selection signal, and the defective bit is replaced with the bit connected to the spare column line. The output of the spare column decoder SCD at this time is input to the NOR gate NG,
The output (column selection signal) of the NOR gate NG is inactivated.

The maximum number of bits that can be repaired by the column redundancy circuit 100 is determined by the number of memory cells provided in reserve. However, the combinations of bits that can be actually repaired are the number of divisions of the memory cell array, the number of column decoders CD,
The number largely depends on the number of column redundancy circuits 100. For example, the repair rates of the columns will be compared between the chip configuration shown in FIG. 6 and the chip configuration shown in FIG.

In the case of the chip structure as shown in FIG. 6, since the column decoder CD is arranged for each cell array,
If one column redundancy circuit 100 is provided for each column decoder CD for each cell array, even if there is a defective column line for each cell array, a spare column line can be replaced for each cell array. That is, in the case of a chip having four column decoder CDs as shown in FIG. 6, one for each column decoder CD.
Defective column lines can be repaired, and up to four defective column lines can be repaired.

On the other hand, in the case of the chip structure as shown in FIG. 7, there is only one column decoder CD, and this one column decoder CD has a spare column address of the same column address in all cell arrays (4 cell arrays). Since the column lines are simultaneously selected, one column redundancy circuit 100 is provided for this one column decoder CD.
By providing the above, only one defective column line in the four cell arrays can be repaired, and the column repair rate is reduced to 1/4 as compared with the chip configuration shown in FIG.

In order to increase the column repair rate, if, for example, four column redundancy circuits 100 are provided for one column decoder CD in the chip configuration as shown in FIG. 7, a maximum of four defective column lines will be generated. Although it can be remedied, four spare column lines must be provided for each cell array, which causes a problem of increasing the chip area.

The same problem as described above also occurs when a row redundancy circuit is provided in a chip structure having a higher degree of integration by commonly selecting four or more cell arrays by one row decoder.

[0015]

As described above, the conventional semiconductor memory device is arranged in a chip structure having an increased degree of integration by commonly selecting four or more cell arrays by one column decoder. When a redundant circuit is provided, if one column redundant circuit is provided for the one column decoder, only one defective column line in the four or more cell arrays can be relieved, and the column remedy rate decreases. If a plurality of column redundancy circuits are provided for the one column decoder, there is a problem that the column repair rate is improved but the chip area is increased.

The present invention has been made to solve the above-mentioned problems, and an object thereof is a chip structure in which four or more cell arrays are commonly selected by one column decoder to increase the degree of integration. An object of the present invention is to provide a semiconductor memory device capable of realizing an improvement in column repair rate while suppressing an increase in chip area when a column redundancy circuit is provided.

[0017]

A semiconductor memory device according to the present invention has a chip configuration in which column lines of four or more cell arrays are commonly selected by a column selection line to which a column selection signal from one column decoder is applied. In the semiconductor memory device having a column redundancy circuit provided in each of the cell arrays for selecting a spare column line for relieving a defective bit line, the column redundancy circuit is commonly provided in the four or more cell arrays. A first spare decoder that receives a row address for performing a selection for each cell array and performs decoding, and at least two or more that receives the column address together with a decode output from the first spare decoder and performs decoding Of the second spare decoder and a logic circuit for taking the logical sum of the outputs of the second spare decoder and outputting the result to one spare column selection line. To.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a semiconductor memory device considered in the middle of the present invention, which has four or more (four in this case) cell arrays AL1 to AL4 by a column selection line to which a column selection signal from one column decoder is applied. By adopting a chip configuration in which the degree of integration is increased by commonly selecting column lines, a spare column line (not shown) for relieving a defective bit provided in each of the cell arrays AL1 to AL4 is selected. 1 schematically shows a pattern layout of a DRAM provided with a column redundancy circuit.

That is, the memory cell array is divided into, for example, four cell arrays AL1 to AL4, and one column decoder section 1 and a sense amplifier (not shown) are provided at one end of the pattern layout. The column decoder unit 1 is provided with one column decoder and one column redundancy circuit common to the above four cell arrays AL1 to AL4. In this column redundancy circuit, a spare column decoder including a programmable address decoder having a fuse element group receives a column address and an address for selecting each cell array, performs decoding, and a spare memory cell group is connected. The spare column line is selected, but the defective bit can be relieved for each cell array by one column redundancy circuit, and is configured as shown in FIG. 2, for example.

FIG. 2 shows the column decoder unit 1, where CD is the column decoder and NG is the column decoder CD.
Of the NOR gate NG, and the output (column selection signal) of this NOR gate NG is applied to the column selection line.
Reference numeral 10 is a column redundancy circuit, and its output (spare column selection signal)
Is applied to one spare column select line. The spare column selection line is provided to select the spare column line of each cell array.

The column redundancy circuit 10 includes the column decoder C.
As many as four spare column decoders SCD1 to SCD as the number of cell arrays selectable by the column selection line to which the output of D is given.
CD4 and these four spare column decoders SCD1 to SC
It has a logic circuit (OR gate OG in this example) which takes the logical sum of the outputs of D4 and outputs it to one spare column selection line. The spare column decoders SCD1 to SCD4 each include a fuse element group made of, for example, polysilicon, and each has an n-bit column address and an address (for example, 2 bits of a row address) for selecting each cell array. Receive and decode. That is, if there is a defective bit, the spare column decoders SCD1 to SCD
Numeral 4 has a predetermined fuse element cut in advance by laser light so as to be a circuit connection for decoding when an address having a defective bit is input.

It should be noted that, as shown in FIG. 1, the column decoder section 1 common to the four cell arrays AL1 to AL4 is used in one place. As shown in FIG. 9, there are two types of circuit systems. That is, in the first circuit system, the increased wiring layer is assigned to the column selection line and the spare column selection line, and the column selection line and the spare column selection line are commonly provided on the plurality of cell arrays, and It is provided in parallel with the column line and the spare column line of each cell array, and the column line and the spare column line are selected by the column selection line and the spare column selection line. Further, in the second circuit system, the increased wiring layer is assigned to the second column line and the second spare column line, and the second column line and the second column line are allocated.
Are provided in common on the plurality of cell arrays and in parallel to the first column line and the first column line of each cell array, and the second column line and the second column column are provided. A line is selected by the column selection line and the preliminary column selection.

In the above DRAM, when the column address corresponding to the normal bit is input to the column decoder CD, the output of the column decoder CD is supplied to the column selection line as a column selection signal via the NOR gate NG. At this time, the spare column decoders SCD1 to SCD4 have their outputs inactive even if an address in which only the column address corresponding to the defective bit or only the address for cell array selection is input is inactive, and the output of the OR gate OG. Is inactive and the spare column select line is not selected. On the other hand, when an address corresponding to a defective bit of a cell array is input, one of the outputs of the spare column decoders SCD1 to SCD4 is activated and the spare column selection line is selected by the spare column selection line via the OR gate OG. The defective bit is supplied as a signal and is replaced with the bit connected to the spare column line. Further, the signal of the spare column selection line at this time is input to the NOR gate NG, and the output (column selection signal) of this NOR gate NG is inactivated. In this case, even if an address in which only the column address corresponding to the defective bit or only the address for selecting the cell array matches is input to part of the spare column decoders SCD1 to SCD4, the output of this part of the spare column decoder Is inactive.

According to the DRAM having the above-mentioned structure, the spare column line to be replaced with respect to the defective bit to be repaired is independently selected for each cell array by adding the address for selecting each cell array. By using one possible column redundancy circuit 10, a conventional column redundancy circuit is provided for each column decoder of each cell array in a chip configuration in which a column decoder is arranged for each cell array as shown in FIG. A column repair rate equivalent to that in the case can be obtained, and an increase in chip area can be suppressed.

The column redundancy circuit 10 having the above structure
Of course, if a plurality of column decoders CD are used for each cell array, the column repair rate will be further improved.

Next, an embodiment of the present invention will be described. In this embodiment, the memory cell array is divided into four cell arrays AL1 to AL4 as shown in FIG. 1, and one column decoder unit 1 and a sense amplifier (not shown) are provided at one end of the pattern layout. Etc. are provided. The column decoder unit 1 is provided with one column decoder and one column redundancy circuit common to the above four cell arrays AL1 to AL4.

The column redundancy circuit 30 in this embodiment is
Two spare row decoders 3 each consisting of a programmable address decoder having a fuse element group and receiving a row address for selecting each cell array and performing decoding
1 and 32 and a programmable address decoder having a fuse element group, and the spare row decoder 3
1 and 32 and at least two (here, two) spare column decoders 33 and 34 for receiving and decoding the column address together with the decode outputs, and the logic of each output of the spare column decoders 33 and 34. It has a logic circuit (OR gate OG in this example) which sums and outputs to one spare column selection line.

When there is a defective bit, the spare row decoders 31 and 32 have a predetermined fuse element so that the spare row decoders 31 and 32 are connected to decode when the row address necessary for selecting the cell array having the defective bit is input. Has been disconnected. Further, the spare column decoders 33 and 34 are connected in such a manner that the decode output from the spare row decoder 31 or 32 is in a selected state and is decoded when a column address having a defective bit is input.
A predetermined fuse element is cut beforehand. in this case,
The number of cell arrays selected by the spare row decoder 31 or 32 is not limited to one, and a predetermined fuse element is cut so as to decode the upper 1 bit or the lower 1 bit of a 2-bit row address input, You may make it select two cell arrays simultaneously. This gives 2
When a defective bit exists at the same column address of each cell array, one spare column decoder 33 or 34
Accordingly, the repair selection for the defective bit of the two cell arrays can be commonly performed.

According to the column redundancy circuit 30 shown in FIG. 3,
As compared with the column redundancy circuit 10 shown in FIG. 2, the number of spare column decoders used can be saved. That is, the column redundancy circuit 10 shown in FIG. 2 requires four spare decoders SCD1 to SCD4 as many as the number of cell arrays selectable by the column selection line to which the output of the column decoder CD is applied. In the column redundancy circuit 30 shown in (1), the number of spare decoders (33, 34) can be set to an arbitrary number, the maximum number of which is the same as the number of cell arrays.

FIGS. 4 and 5 each schematically show a pattern layout of a chip structure of a DRAM according to another embodiment of the present invention, and the present invention can be applied similarly to the above embodiments. You can That is, the pattern layout shown in FIG. 4 is different from the pattern layout shown in FIG. 1 in that a column decoder unit (a column decoder and a spare column decoder) 1 is provided in the central portion of the pattern layout. Since they are the same, the parts corresponding to those in FIG. 1 are designated by the same reference numerals as those in FIG.

The pattern layout of FIG. 5 is as shown in FIG.
Since two sets of the pattern layouts shown in FIG. 2 are provided and the other parts are the same, the parts corresponding to those in FIG. 1 are designated by the same reference numerals as those in FIG.

[0032]

As described above, according to the semiconductor memory device of the present invention, column redundancy is provided for a chip structure having a higher degree of integration by commonly selecting four or more cell arrays by one column decoder. When the circuit is provided, the column repair rate can be improved while suppressing an increase in chip area.

[Brief description of drawings]

FIG. 1 is a diagram schematically showing a pattern layout of a chip configuration relating to a semiconductor memory device considered in the middle of the present invention;

FIG. 2 is a block diagram showing an example of a column decoder section in FIG.

FIG. 3 is a block diagram showing an example of a column decoder section according to an embodiment of a semiconductor memory device of the present invention,

FIG. 4 is a diagram schematically showing a pattern layout of a chip structure according to another embodiment of the semiconductor memory device of the invention.

FIG. 5 is a diagram schematically showing a pattern layout of a chip structure according to another embodiment of the semiconductor memory device of the invention.

FIG. 6 is a diagram showing a pattern layout of a conventional DRAM chip configuration;

FIG. 7 is a diagram showing a pattern layout of a conventional DRAM chip configuration;

8 is a circuit diagram showing an example of how to use an increased number of wiring layers for performing the pattern layout of the chip configuration shown in FIG.

9 is a circuit diagram showing another example of how to use one wiring layer increased to perform the pattern layout of the chip configuration shown in FIG.

FIG. 10 is a circuit diagram showing an example of a column decoder unit used in a conventional DRAM.

[Explanation of symbols]

AL1 to AL4 ... Cell array, CD ... Column decoder, 10, 30 ... Column redundancy circuit, 31, 32 ... Spare row decoder, 33, 34 ... Spare column decoder, SCD1-SCD4 ... Spare column decoder, OG ... OR gate, BL1, / BL1, BL2, / BL2 ... Column line pair, BL ", / BL" ... Second column line pair, CT1, / CT1, CT2, / CT2 ... Column selection transistor, CT ", / CT" ... 2 column select transistors.

Claims (1)

[Claims] 1. A chip configuration for commonly selecting column lines of four or more cell arrays by a column selection line supplied with a column selection signal from one column decoder, and defects provided in each of the cell arrays. In a semiconductor memory device in which a column redundancy circuit for selecting a spare column line for bit line relief is commonly provided in the four or more cell arrays, the column redundancy circuit outputs a row address for selecting each cell array. A first spare decoder for receiving and decoding, and at least two or more second spare decoders for receiving and decoding the column address together with the decode output from the first spare decoder; 2. A semiconductor memory device comprising: a logical circuit for taking the logical sum of the respective outputs of the spare decoders and outputting the result to one spare column selection line.