JPH08235882A - Nonvolatile semiconductor storage - Google Patents

Abstract

PURPOSE: To make the writing of multilevel information sure by providing a driving signal means impressing a driving signal in which a first and a second potentials are alternately repeated to control gates of memory cell transistors. CONSTITUTION: A memory cell transistor having a floating gate holding nonvolatile information and a control gate controlling the writing, the reading and the erasing of information to be held in the floating gate is provided in this storage. A driving signal WDPOUT in which plural kinds of positive potentials (+2/+3/+4V) and a negative potential (-10V) are alternately repeated is impressed on a word line to which the control gate of the memory cell transistor is connected. The driving signal WDPOUT is generated by a word line driving pulse generating circuit 2 by making the multilevel program level generating circuit 20 an input to be applied to control gates of the memory cell transistors via respective word lines.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device (EEPR) capable of electrically rewriting / erasing information.
OM).

[0002]

2. Description of the Related Art Nonvolatile semiconductor memory devices are roughly classified into (1) a write method by hot electrons and an erasing method by tunneling current.
(2) It is divided into a writing method using a tunnel current and an erasing method using a tunnel current.

A flash EEPROM is a typical example of a nonvolatile semiconductor memory device adopting the former method (1).
There is. In a flash EEPROM, a write voltage (high voltage Vpp) is applied to both the control gate and drain electrode of a MOS transistor that constitutes a memory cell.
Is applied to inject hot electrons into the floating gate to perform writing.

In such an EEPROM, the memory cell is changed by the channel length of the memory cell MOS transistor, the tunnel current passing insulating film thickness (tunnel oxide film thickness) under the floating gate, or the electrode voltage between the source and drain. The threshold of the transistor changes. As a result, the distribution of the threshold voltage VTH after writing information to each memory cell transistor (data “0”)
Shows a large variation as shown in the upper distribution chart that is shaded in FIG. 11 (a) or FIG. 11 (b).

On the other hand, at the time of erasing, the control gate of the memory cell MOS transistor is grounded, the erasing voltage (Vpp) is applied to the source electrode (or drain electrode), and the electrons trapped in the floating gate are shaped into a tunnel current. To the source electrode (or drain electrode). Even in this erase operation, the distribution (data ") of the threshold VTH of the memory cell transistor after erase
1 ") is the voltage of the control gate (word line voltage), drain voltage (bit line voltage), as in writing
Alternatively, depending on the variation in the film thickness of the tunnel oxide film or the like, there is a large variation as shown in the lower distribution diagram in FIG. 11A or FIG.

A typical example of a non-volatile semiconductor memory device adopting the latter method (2) is a NAND type EEPROM.
There is. In this NAND type EEPROM, writing and erasing are performed by a tunnel current from a floating gate of a MOS transistor which constitutes a memory cell.

The tunnel current of the method (2) depends on the word line voltage (control gate voltage), the bit line voltage (drain voltage) or the film thickness of the tunnel oxide film, as in the case of the erase of the method (1). It fluctuates depending on variations. Therefore, also in the case of the method (2), the distribution of the threshold voltage VTH of the memory cell transistor at the time of writing and erasing greatly varies as shown in the upper and lower distribution chart of FIG.

For example, referring to the example of FIG. 11B, of the variations in the threshold voltage VTH, the higher voltage side (data)
0 "writing is distributed above the read operation voltage (+ 5V of the TTL level) of the EEPROM, so that there are few problems. However, the threshold voltage VTH of the low voltage side (data" 1 "erasing) Since the variation is distributed inside the read operation voltage of the EEPROM (+ 5V of the TTL level), it greatly affects the data reading.

That is, when the threshold voltage VTH of the memory cell transistor (which constitutes the EEPROM) (particularly the threshold value after the electrons of the floating gate are extracted by the erase operation) greatly varies as described above, a fixed predetermined value is obtained. There is a possibility that the information reading operation based on the threshold voltage cannot be performed.

[0010]

Therefore, it is conceivable to change the write / erase time for each memory cell transistor (bit) and operate so that the threshold voltage VTH falls within a predetermined range. However, in that case, a circuit for detecting and correcting the write state and erased state of each memory cell transistor is required, but the circuit configuration is complicated and the area of the semiconductor pellet in which the EEPROM is incorporated is correspondingly large (defects). 1).

If the operation of keeping the threshold voltage of the memory cell transistor within a predetermined range by changing the write / erase time for each bit, the write / erase is performed when the number of bits is large.
There is a problem that the time required to complete the erasing becomes long (defect 2).

Further, a batch erasing type flash EEPROM
In order to prevent some cells from being over-erased in the writing / erasing operation, the electric charges are accumulated in advance in the floating gates of the plurality of memory cell transistors to write "0" data, and then the plurality of memory cell transistors are written. It is general to collectively erase the charges accumulated in the floating gates of the transistors, but doing so has a problem that the erase operation becomes complicated (defect 3).

If the write / erase time operation for each bit is simplified or omitted in order to avoid the above-mentioned disadvantages 1 to 3, there are large variations in the threshold values of many memory cell transistors. It becomes difficult (practically impossible) to realize a multi-valued memory for storing threshold data (defect 4).

The present invention has been made in view of the above circumstances, and a first object thereof is to suppress variations in threshold values of a plurality of memory cell transistors forming an information storage section,
Another object of the present invention is to provide a non-volatile semiconductor memory device that can surely erase information stored in a memory cell transistor without overerasing.

A second object of the present invention is to provide a non-volatile semiconductor memory device (multilevel memory) capable of storing a plurality of types of threshold value data in each memory cell.

[0016]

In the nonvolatile semiconductor memory device of the present invention according to the first object, the word line drive signal (WDP) peculiar to the present invention is applied to the word line to which the control gate of the memory cell transistor is connected. ) Is given. This word line drive signal (WDP) has one potential (for example +3 V) corresponding to a desired threshold value (for example, +2.5 V) for the target memory cell transistor (Ma1) and the floating gate for the target memory cell transistor (Ma1). The other electric potential (for example, −10 V) for extracting the electric charge accumulated in the electric field in the form of a tunnel current has an oscillating waveform (AC waveform) that alternates a predetermined number of times (for example, 10 times). Here, the word line drive signal (WD
The absolute value of the other potential (-10V) of P) is selected to be several times (about 2 to 5 times) the absolute value of the other potential (+ 3V), but what is the numerical value of the ratio of the other potential to the one potential? Whether or not it is determined appropriately according to each embodiment. The number of repetitions of the AC waveform of the word line drive signal (WDP) is also appropriately determined according to each embodiment. Further, the AC waveform itself of the word line drive signal (WDP) is not limited to a specific shape such as a rectangular wave, and various waveforms such as a sine wave, a triangular wave, and a sawtooth wave can be used as the word line drive signal (WDP). Applicable.

In the nonvolatile semiconductor memory device according to the second aspect of the present invention, a plurality of potentials (+ 2V, + 3V or +4) are used as one potential of the word line drive signal (WDP).
V) is selectively used. By using the selected one potential, one memory cell stores a plurality of multivalued data corresponding to the type of one potential.

In the nonvolatile semiconductor memory device of the present invention according to the first object, first, the word line drive signal (WDP) is generated.
One potential (for example, + 3V) is applied to the control gate of the target memory cell transistor (Ma1), and it is checked whether this one potential (+ 3V) turns on this memory cell transistor.

If turned on, the bit line potential is lowered between the drain and source of the memory cell transistor of interest, and then the other potential (-10 V) of the word line drive signal (WDP) is applied to the control gate of the memory cell transistor. However, the electric charge is not emitted from the floating gate due to the tunnel current (prevention of overerasure).

When the memory cell transistor is not turned on by one potential (+ 3V) of the first word line drive signal (WDP) (the threshold value of the memory cell transistor of interest is higher than the desired value), the bit line potential does not decrease. . Immediately after that, the word line drive signal (WD
When the other potential (-10 V) of P) is applied, the accumulated charges are slightly extracted in the form of tunnel current from the floating gate of the memory cell transistor of interest. Then, the threshold value of the memory cell transistor of interest is slightly lowered by the amount of the extracted charges.

Even if one potential (+ 3V) of the word line drive signal (WDP) is applied to the memory cell transistor whose threshold value is slightly lowered, this memory cell transistor is not turned on yet (the threshold value of the memory cell transistor of interest). Is still higher than the desired value), the decrease of the bit line potential does not occur. Immediately thereafter, when the other potential (-10 V) of the word line drive signal (WDP) is applied to the control gate, the accumulated charges are extracted again in the form of tunnel current from the floating gate of the memory cell transistor of interest. Then, the threshold value of the memory cell transistor of interest is further reduced by the amount of the extracted charges.

When one potential (+ 3V) of the word line drive signal (WDP) is applied again to the memory cell transistor whose threshold value is further lowered and this memory cell transistor is turned on (that is, the threshold value of the memory cell transistor of interest is (When it decreases to a desired value), the bit line potential decreases between the drain and the source of the turned-on target memory cell transistor. Then, even if the other potential (-10 V) of the word line drive signal (WDP) is applied to the control gate of the memory cell transistor thereafter, the floating gate does not discharge the charge due to the tunnel current (prevention of over-erase). ). At this point, the memory cell transistor of interest has been erased so as to have a desired threshold value accurately without overerasing (achieving the first object).

That is, according to the present invention, all the threshold values of each of the memory cell transistors forming the nonvolatile semiconductor memory device are desired to correspond to one potential (for example, +3 V) of the word line drive signal (WDP). Value (+2.
Since it can be converged to 5 V), the variation width of the threshold voltage of the memory cell transistor becomes extremely small (1/3 or less of the conventional value).

In the non-volatile semiconductor memory device of the present invention according to the second object, a plurality of levels are prepared as one potential for giving the convergence target. For example, if the one potential is + 4V, the threshold of the memory cell transistor converges to + 3.5V, for example, if the one potential is + 3V, the threshold of the memory cell transistor converges to + 2.5V, for example. For example, if the potential on the one hand is + 2V, the threshold value of the memory cell transistor converges to + 1.5V, for example. Since the variation in the threshold value obtained as a result of this convergence is extremely small, for example, three types of threshold value data (+ 3.5V, + 2.5V, + 1.5V), that is, multi-valued data, are respectively stored in one memory cell transistor. It can be stored separately.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION The configuration and operation of a nonvolatile semiconductor memory device (EEPROM) according to the present invention will be described below.
This will be described with reference to the drawings.

FIG. 1 shows an E according to an embodiment of the present invention.
It is a circuit diagram which shows the principal part of EPROM. In the figure,
The memory cell array 1 includes a bit line selection transistor Tsa1 that selectively connects the main bit line BLa1 to the sub bit line BLsa1, non-volatile memory cell transistors Ma1 and Ma2 whose drains are connected to the sub bit line BLsa1, and memory cell transistors. Ma1 and Ma2
Includes a bit line capacitor Ca1 connected between the common source circuit and the sub bit line BLsa1. Each of the nonvolatile memory cell transistors Ma1 and Ma2 has an N-channel MOS transistor structure having a control gate and a floating gate, and the floating gate holds nonvolatile charge information.

Here, the sub-bit line means a conductor line connected to the drain (or source) of the memory cell transistor. Further, the main bit line means a conductor line connected to the sub bit line via the switch means.

The memory cell array 1 further includes a bit line selection transistor Tsb1 for selectively connecting the main bit line BLb1 to the sub bit line BLsb1 and a sub bit line BLs.
Non-volatile memory cell transistors Mb1 and Mb2 whose drains are connected to b1, common source circuit of memory cell transistors Mb1 and Mb2, and sub-bit line BL
It includes a bit line capacitor Cb1 connected to sb1. The non-volatile memory cell transistors Mb1 and Mb2 also have a control gate and a floating gate, respectively, and non-volatile charge information is held in these floating gates.

Memory cell transistors Ma1, Ma2,
The common source circuit of Mb1 and Mb2 is selectively connected to the ground circuit (or the negative power supply Vss / 0V circuit) via the source side selection transistor Trs1.

A bit line selection gate line ST1 is connected to the gates of the bit line selection transistors Tsa1 and Tsb1, and a source side selection gate line SL1 is connected to the gate of the source side selection transistor Trs1. The word line W1 is connected to the gates of the memory cell transistors Ma1 and Mb1.
A word line W2 is connected to the gates of 2 and Mb2.

Here, each memory cell transistor (Ma
1 to Ma2 / Mb1 to Mb2) is specifically exemplified as follows.

* The floating gate is 3 μm × 1 μ
It has a size of m and is in contact with a part of the channel and the source / drain with the gate oxide film interposed therebetween.

* The size of the channel is 1 μm × 1 μm, and the thickness of the gate oxide film is 10 nm.

* The insulating film between the floating gate and the control gate is 15 nm in terms of silicon oxide film.
Of ONO film (silicon oxide film / silicon nitride film / silicon oxide film).

The bit line selection transistor Tsa1, the memory cell transistors Ma1 and Ma2 and the bit line capacitor Ca1 form a memory cell block 1a, and the bit line selection transistor Tsb1, the memory cell transistors Mb1 and Mb2 and the bit line capacitor Cb1 are the memory cell block. It constitutes 1b.

In FIG. 1, for the sake of clarity, the memory cell transistor (Ma) in each memory cell block is
1 to Ma2 or Mb1 to Mb2), the number of memory cell transistors constituting each memory cell block can be increased (for example, 256 to 1024 memory cells per block). Transistor). In this case, the word lines (W1-W
The number of 2) also increases corresponding to the actual number of memory cell transistors.

The memory cell block 1a has a combined capacitance (bit line equivalent capacitance Co; 100f) of the bit line capacitor Ca1 and the stray capacitance (parasitic capacitance) of the sub bit line BLsa1.
It has the function of a DRAM having information storage means of about F to 300 fF). That is, the bit line equivalent capacitance Co is charged with the voltage of the main bit line BLa1 when the bit line selection transistor Tsa1 is turned on, and the charged capacitance Co is charged.
If the voltage is refreshed periodically, information can be stored in the capacitance Co of the sub bit line BLsa1 according to the same operation principle as the DRAM.

The memory cell block 1b also has a DRAM function using the combined capacitance (bit line equivalent capacitance Co of about 100 fF to 300 fF) of the bit line capacitor Cb1 and the stray capacitance of the sub bit line BLsb1 as information storage means. There is. That is, if the bit line equivalent capacitance Co is charged with the voltage of the main bit line BLb1 when the bit line selection transistor Tsb1 is turned on, and the voltage of the charged capacitance Co is periodically refreshed, the sub operating principle is the same as that of the DRAM. Information can be stored in the capacitance Co of the bit line BLsb1.

As described above, the sub bit line BLsa1 (BL
When the configuration of FIG. 1 is captured as a DRAM in which the bit line equivalent capacitance Co of sb1) is used as a memory cell capacitor, the main bit line BLa1 (BLb1) corresponds to the bit line of the DRAM, and the bit line selection gate line ST1 is the word of the DRAM. It corresponds to a line.

The DRAM structure of the main bit line BLa1 functions as a write buffer having a relatively high speed with respect to the memory cell block 1a as the EEPROM. Further, the DRAM structure of the main bit line BLb1 is EEP
It functions as a relatively high speed write buffer for the memory cell block 1b as a ROM.

The sub-bit lines BLsa1 / BLs are becoming smaller along with the miniaturization of the memory device due to the progress of semiconductor manufacturing technology.
Although the stray capacitance of b1 itself (the electrostatic capacitance parasitic between the sub-bit line and the semiconductor region where the sub-bit line is formed) tends to be small, this stray capacitance and a large number of memory cell transistors (Ma1 to Ma1 When the sum of the drain-source capacitance of Ma2 / Mb1 to Mb2) is 100 to 300 fF or more, the capacitors Ca1 / Cb1 can be omitted.

FIG. 1 shows a part of the configuration of the EEPROM, and the actual memory cell array has more main / sub bit lines, word lines, select gate lines, select transistors,
Includes memory cell transistors and others. These memory cell transistors are arranged in a matrix.
A row / column decoder circuit (peripheral circuit) for specifying a predetermined memory cell according to an address input from the outside is connected to the memory cell matrix. Also, for each of the plurality of main bit lines, a bit line precharge circuit,
A sense amplifier for reading the stored data from the specified memory cell transistor is connected.
The configurations of these row / column decoder circuits, precharge circuits and sense amplifiers are well known in general DRAMs.

The sub bit line BLsa1 is provided with a switch circuit 5a.
Is connected to the charge extraction completion detecting circuit 4a via the switch, and the sub-bit line BLsb1 is connected to the charge extraction completion detecting circuit 4b via the switch circuit 5b. Charge extraction completion detection circuit 4
In each of a and 4b, a P-channel MOS transistor T6 is arranged on the positive power supply Vdd (+ 5V) side and a negative power supply V
It is composed of a CMOS inverter in which an N-channel MOS transistor T7 is arranged on the ss (0V) side.

The charge extraction completion detection circuit 4a has a Vss level (=) when the potential of the sub-bit line BLsa1 is higher than the gate threshold value of the N-channel MOS transistor T7 (for example, + 2.5V) at the time when the switch circuit 5a is closed. When the potential Da of the sub-bit line BLsa1 is lower than the gate threshold value of the P-channel MOS transistor T6 (for example, 5V-2.5V = + 2.5V) at the time when the switch circuit 5a is closed, the output Da is generated. The output Da of the Vdd level (= 5V) is generated.

That is, when the output Da of the charge extraction completion detection circuit 4a is at the Vss level (= 0V), the sub bit line B
Target memory cell transistor Ma connected to Lsa1
1 (or Ma2) charge extraction from the floating gate is not completed and the output Da changes to the Vdd level (= 5V), the memory cell transistor Ma1 (or Ma2) of interest connected to the sub-bit line BLsa1. It is detected that the electric charge extraction from the floating gate of the above) is completed.

Similarly, when the output Db of the charge extraction completion detecting circuit 4b is at the Vss level (= 0V), the sub bit line BL is generated.
Target memory cell transistor Mb1 connected to sb1
(Or Mb2) charge extraction from the floating gate is not completed, and when the output Db changes to the Vdd level (= 5V), the target memory cell transistor Mb1 (or Mb2) connected to the sub-bit line BLsb1. It is detected that the electric charge extraction from the floating gate of is completed.

The word lines W1 and W2 are commonly connected to the output circuit of the word line drive pulse generation circuit 2 via the word line switch circuit 3. This circuit 2 includes a CMOS inverter (P-channel transistor T2 + N-channel transistor T3) connected to a positive power source of + 3V and a negative power source of -10V, and a normally-on P-channel transistor T4 on its input side (if its gate potential is controlled. And a N-channel transistor T5 for positively feeding back the output of this CMOS inverter to its input side.

The word line drive pulse generation circuit 2 generates a pulse output WDPOUT whose potential changes between + 3V and -10V according to the signal potential of the input WDSIN whose potential changes between 0V and + 5V.

That is, the word line drive pulse generation circuit 2
When a word line drive signal input WDSIN having a waveform as shown in FIG. 2A is applied, generates a word line drive pulse output WDPOUT having a waveform as shown in FIG. 2B. This circuit 2 has 0V / + 5 as shown in FIG.
It has a function of level-shifting a V pulse to a + 3V / -10V pulse as shown in FIG.

+ 3V / -10V as shown in FIG. 2 (b)
The word line drive pulse output WDPOUT is supplied to the word lines W1 and W2 when the word line switch circuit 3 is turned on. As a result, all the memory cell transistors whose control gates are connected to the word lines W1 and W2 (the ones to which a sufficient sub-bit line potential is applied to their drains) are connected to the word line drive pulse output WDPOUT of + 3V / -10V. Thus, it becomes possible to collectively erase to a desired threshold value (all-bit-unit or memory-block-unit batch erase flash EEPROM operation).

Next, referring to FIG. 3, the EEPRO of FIG.
The circuit operation (erase / leakage current compensation) of the bit line select transistor Tsa1 and the memory cell transistor Ma1 in M will be described. Here, FIG. 3B is a circuit obtained by simplifying the memory configuration of FIG. 1, and voltage waveforms applied to respective parts thereof are shown in FIG. 3A.

In FIG. 3B, the main bit line BLa1
Is connected to the drain of the N-channel MOS type memory cell transistor Ma1 via the drain and source of the bit line selection transistor Tsa1, and the bit line equivalent capacitance Co and the leakage current component equivalent resistance Ro are connected in parallel between the drain and source of the transistor Ma1. It is connected.

Here, the bit line equivalent capacitance Co indicates a combined value of the floating capacitance of the sub bit line BLsa1 and the bit line capacitor Ca1, and the leakage current component equivalent resistance Ro indicates the source circuit of the memory cell transistor Ma1 from the sub bit line BLsa1. The resistance value of the current path leaking to (Vss / 0V) is shown. Here, it is assumed that the equivalent capacitance Co is about 1 pF and the equivalent resistance Ro is about 1000 MΩ.

First, the nonvolatile memory cell transistor M
The erase operation will be described assuming that the threshold voltage VTH of a1 is 6.5 V or more at the beginning (see FIG. 11B).

+ 5V as shown on the left side of the middle part of FIG.
While the potential of is applied to the bit line selection gate line ST1,
A potential of +5 V as shown in the upper part of the figure is applied to the main bit line BLa.
When set to 1, the transistor Tsa1 is turned on and the sub-bit line BLsa1 is precharged to approximately + 5V (potential reference 0V = Vss is the memory cell transistor Ma1).
Take the source circuit).

After that, when the potential of the bit line selection gate line ST1 is lowered to 0V as shown in the middle of the left side of the middle of FIG. 3A, the transistor Tsa1 is turned off and the sub bit line BLsa1 is electrically connected to the main bit line BLa1. Are separated and become floating. In this state, the precharge potential + 5V of the sub bit line BLsa1 is maintained by the electric charge charged in the sub bit line equivalent capacitance Co which is a minute capacitance (1 pF).

Then, the control gate of the memory cell transistor Ma1 is connected to the control gate of FIG.
A word line drive pulse as shown near the center on the left side of the lower part of (a) is applied. The output WDPOUT from the word line drive pulse generation circuit 2 of FIG. 1 is used for this pulse. Here, the period (0V period) in which there is no word line drive pulse in the lower part of FIG. 3A is a period in which the switch circuit 3 in FIG. 1 is off, and during the period in which this pulse is generated, the switch circuit 3 is on. There is.

When the switch circuit 3 is turned on, + 3V is applied to the control gate of the memory cell transistor Ma1 for a short time (for example, 20 μs), but it is assumed that the threshold voltage VTH is 6.5 V or more at first, so that the transistor Ma1 is used. Remains off. At this time, if the sub-bit line potential drop due to the leakage current flowing through the equivalent resistance Ro is still negligible, the sub-bit line BLsa1 is maintained in the floating state (+ 5V).

Next, when a word line drive pulse of -10 V is applied to the control gate of the memory cell transistor Ma1 for a short time (for example, 10 μs), the drain becomes +5.
Memory cell transistor M precharged to V
A tunnel current flows between the floating gate and drain of a1. Due to this tunnel current, the electric charge of the floating gate is slightly extracted, and as a result, the threshold voltage VTH of the memory cell transistor Ma1 is slightly decreased.

Even if the threshold voltage VTH of the memory cell transistor Ma1 is slightly lowered, as long as it is larger than + 3V of the word line drive pulse, the memory cell transistor M1 is reduced.
a1 does not turn on.

Even if the memory cell transistor Ma1 is not turned on, if a sufficient precharge potential is applied to its drain, electric charges are gradually added from its floating gate every time a −10 V word line drive pulse is applied. It is extracted in the form of a tunnel current, and its threshold voltage VTH gradually decreases gradually.

However, due to the tunnel current flowing through the floating gate of the memory cell transistor Ma1 and the leakage current flowing through the leakage current component equivalent resistance Ro, the charging voltage (sub-bit line precharge potential) of the bit line equivalent capacitance Co also changes with time. It is decreasing. If the precharge potential is too low (that is, the drain potential of the memory cell transistor Ma1 is too low), even if -10V is applied to the control gate of the transistor Ma1, the tunnel current will not flow to the floating gate. Then, the operation of gradually decreasing the threshold voltage VTH of the transistor Ma1 is stopped before the desired value (for example, + 2.5V) corresponding to the word line drive pulse + 3V is reached.

Therefore, in order to prevent the sub-bit line precharge potential from decreasing, in the configuration of FIG. 3, bit line selection is intermittently performed during the period in which the word line drive pulse output WDPOUT is applied to the word line W1. Transistor Tsa1
Is momentarily turned on to inject a small amount of charges from the main bit line BLa1 to the sub bit line BLsa1 in the floating state.

That is, when the potential of the sub-bit line BLsa1 in the floating state drops to some extent, the switch circuit 3 of FIG. 1 is turned off, and as shown in the center of the lower stage of FIG. WDPOUT
Is applied to the word line W1 (interruption period is 30 μs or less for one cycle of the pulse WDPOUT, for example, 7 μs).
To a degree). Then, as shown in the center of the middle part of FIG. 3A, a short pulse of +5 V (for example, a time space of 2 μs before and after is applied to the bit line selection gate line ST1 during the interruption period (7 μs) of the word line drive pulse output WDPOUT. The applied pulse having a width of 3 μs) is applied to momentarily turn on the bit line selection transistor Tsa1, and the sub bit line BLsa1 whose potential has dropped is returned to the full precharge state of + 5V.

By the combination of the pulses shown in the middle / lower part of FIG. 3A, the sub-bit line BLsa in the floating state even if there is a bit line leakage current.
Secure a potential of 1 (around + 5V). Then, by repeatedly applying −10 V of the word line drive pulse output WDPOUT, charges are gradually extracted from the floating gate of the memory cell transistor Ma1.

As a result of the above charge extraction, the threshold voltage VTH of the memory cell transistor Ma1 is the desired value (+2.5).
V), the word line drive pulse output WDPOUT + 3V immediately thereafter causes the memory cell transistor M
a1 turns on, and the potential of the sub-bit line BLsa1 drops to 0V. Then, after that, the charge extraction from the floating gate of the memory cell transistor Ma1 is stopped, and the threshold voltage VTH of the memory cell transistor Ma1 becomes exactly the desired value + 2.5V (this is the erased state of the memory cell transistor Ma1). .

Completion of erasing of the memory cell transistor Ma1 is detected by the charge extraction completion detecting circuit 4a of FIG. 1 connected to the sub bit line BLsa1 (Da = ").
1 "). After the end of erasing is detected, the application of the 3 μs width pulse at the center of the middle stage of FIG. 3A is also stopped.

The above erase operation is performed for all the memory cell transistors (Ma1 to Ma) of the memory cell block 1a of FIG.
If 2) is performed at the same time, batch erase (flash erase) in block units is realized. If this erasing operation is simultaneously performed for all memory cell blocks, batch erasing in memory chip units is realized. If this erase operation is sequentially performed for each memory cell transistor, bit-by-bit erase is realized.

In any erase operation, the sub-bit line potential during the erase operation is maintained at a predetermined value (around + 5V), and is sequentially compared with the predetermined word line potential (+ 3V) to change from the floating gate of the memory cell transistor. Since the electric charge is gradually extracted, the threshold voltage VTH of all the memory cell transistors is set to a desired value (+ 2.5V).
Can be accurately converged to.

Moreover, this convergence operation is performed at most 10 pulses (1 pulse 30 μ) of the word line drive pulse output WDPOUT.
Since it can be completed in about 300 μs at the longest as s,
Flash erasing in block units or memory chip units can be performed at high speed (within 300 μs).

Next, the threshold voltage VTH of the memory cell transistor Ma1 is lower than a desired value (for example, + 2V).
The mechanism for preventing overerasure in such a case will be described.

First, similarly to the case where the threshold voltage VTH is higher than a desired value, the potential Vss of the source line of the memory cell transistor Ma1 is set to the ground potential 0V, the bit line selection transistor Tsa1 is turned on, and the sub bit line BLsa is turned on.
After precharging the potential of 1 to + 5V, the bit line selection transistor Tsa1 is turned off, and the sub bit line BL
The sa1 is brought into a floating state of + 5V. In this case, the bit line equivalent capacitance Co is in a charged state.

Then, a word line drive pulse as shown in the lower part of FIG. 3A is applied to the word line W1. When the threshold voltage VTH is lower than the desired value (+ 2V), the drain of the memory cell transistor Ma1 has the sub-bit line precharge potential (+ 5V). Therefore, when a pulse of + 3V is applied to its control gate, The memory cell transistor Ma1 is turned on. Then, a channel current flows between the drain and source of the memory cell transistor, the bit line equivalent capacitance Co is discharged, and the drain voltage is lowered. Then, the memory cell transistor Ma1
Even if a pulse of -10V is applied to the control gate of, the tunnel current does not flow between the floating gate and the drain. Therefore, the threshold voltage VTH is originally
The charge is not further extracted from the floating gate of the memory cell transistor Ma1 having a low memory cell, and overerasure is prevented.

The threshold voltage VTH is the desired value (+
For memory cell transistors lower than (2.5V) (+ 2V), data "0" is then written, charges are injected into the floating gate, and the threshold voltage V
When 10 pulses of the word line drive pulse output WDPOUT are applied after TH becomes high (+6.5 V or more), the threshold voltage VTH converges to a desired value (+2.5 V).

As described above, in the EEPROM of the present invention, the threshold voltage VTH of a memory cell transistor whose original threshold voltage VTH is higher than a desired value is set.
While TH is converged to a desired value, electrons are not extracted from the floating gate of a memory cell transistor whose original threshold voltage VTH is a desired value or less.

Therefore, even if a plurality of memory cell transistors having different threshold voltages VTH are simultaneously erased at the same time, no memory cells will be over-erased, and almost all memory cell transistors will not be erased. The threshold voltage VTH can be accurately converged to a desired value. Therefore, the time-consuming "threshold alignment operation of the non-volatile memory accompanied by the write operation before erasure" which has been conventionally performed is unnecessary in the present invention.

In the above description, the word line voltage VW = 3V and the write threshold value VTH = 2.5V have been described, but this threshold value can take another value. For example, VW = 3
VTH = 3.7V, VW = 2V and VTH = 3.0V,
It is also possible to set VW = 1V and VTH = 2.3V.

The bit line connected to the memory cell transistor to which the word line drive pulse WDPOUT is applied is set to a floating state (precharged to + 5V, for example) before the pulse WDPOUT is applied to this transistor. To be done. Then, the gate threshold value of this transistor is pulsed by WDP.
It can be converged to a predetermined value (for example, VTH = 3.7V) corresponding to one potential of OUT (for example, + 3V).

That is, regarding the function of adjusting the threshold value of the memory cell transistor by applying a fluctuating voltage such as an alternating voltage to the gate of the transistor,
The following can be said. After applying the AC voltage to the gates of one or more memory cell transistors for a predetermined period (or a predetermined number of cycles) after realizing the floating state of the bit lines in advance, the threshold values of these memory cell transistors are automatically or uniquely determined. Is adjusted to a desired value.

In order to maximize the effect of the "threshold automatic adjustment function" for one or more memory cell transistors, it is preferable to "set the bit line in a floating state". This, however, does not preclude the "not floating" embodiment of the bit line. For example, an embodiment in which the bit line is connected to a circuit having a specific potential through an equivalently high resistance element or circuit may be used.

To set the bit line of the memory cell transistor (Ma1, Mb1 etc.) to which the word line drive pulse WDPOUT is applied to the floating state (precharge state), it is provided between the sub bit line and the main bit line. The transistors (Tsa1, Tsb1, etc.) that have been selected may be temporarily turned off. Alternatively, this transistor (M
common source circuit (a1, Mb1, etc.) and ground circuit Vss
Even if a transistor (Trs1 or the like) provided between the word line drive pulse WD and
A memory cell transistor (Ma) to which POUT is applied
1 and Mb1) can be set to a floating state (precharge state).

The drain side (sub-bit line BLsa1 etc.) of the memory cell transistor (Ma1 etc.) is, for example, +5.
After being precharged to V, the drain side is set to a floating state or a state that can be regarded as a floating state. Here, the state that can be regarded as a floating state means a state that is substantially in a floating state for a short time. To give a concrete example, the drain side of the memory cell transistor is connected to a predetermined power supply circuit (for example, a + 5V Vdd circuit) via a high resistance (including a high resistance that can be regarded as substantially infinite). The state can be regarded as a floating state.

The drain side potential in the floating state does not rise for a predetermined period once it drops. on the other hand,
The drain-side potential that can be regarded as the floating state is in a range where the potential increase can be ignored for at least a certain short time after the drain-side potential once decreases.

Here, D shown in FIG. 1 or FIG.
The erase / write / read / refresh operations of the RAM type memory device will be briefly summarized.

"Erase Operation" (1) DRAM cell portion (sub-bit lines BLsa1 / BLsb) including one or more memory cell transistors (for example, Ma1 to Ma2 / Mb1 to Mb2) to be erased
1) row (gate line ST1) and column (bit line BLa1 /
BLb1) is designated by a row / column decoder (not shown),
The selection transistor (Tsa1 / Tsb1) is turned on. As a result, the corresponding DRAM cell portion (sub-bit line BL
sa1 / BLsb1) is precharged to + 5V.

(2) One or more memories to be erased while the drains (sub-bit lines BLsa1 / BLsb1) of one or more memory cell transistors (Ma1 to Ma2 / Mb1 to Mb2) to be erased are precharged to + 5V. The control gates (word lines W1 / W2) of the cell transistors (Ma1 to Ma2 / Mb1 to Mb2) are connected to the control gates shown in FIG.
Erase word line drive pulse WDPO as shown in FIG.
Apply UT. As a result, the threshold values of the memory cell transistors (Ma1 to Ma2 / Mb1 to Mb2) to be erased are converged to desired values (for example, +2.5 V) (all-bit batch erase; flash EEPROM).
motion). By this batch erasing of all bits, all memory cell transistors are written with data "1" (corresponding to a threshold value of 2.5 V), for example.

"Write Operation (After Erase)" (1) DRAM cell portion (sub-bit line BL) including a memory cell transistor (for example, Ma1) to be written
The row (gate line ST1) and the column (bit line BLa1) of the equivalent capacitance Co of sa1 are designated by a row / column decoder (not shown) to turn on the selection transistor (Tsa1) (when the power supply voltage of the memory is + 5V). In this case, + 7V, for example, is applied to the gate of the selection transistor Tsa1).
As a result, the capacitance Co of the corresponding DRAM cell portion is a voltage corresponding to the write data ("1" or "0";"1" data corresponds to 0 V, "0" data corresponds to +5 V, for example).
Is charged).

(2) The drain (sub-bit line BLsa1) of the memory cell transistor (Ma1) to be written is used as the write voltage (charging voltage of the equivalent capacitance Co), and the control gate (of the memory cell transistor (Ma1) ( A high voltage for writing (for example, +6 V) is applied to the word line W1) to inject hot electrons corresponding to the writing voltage into the floating gate of the memory cell transistor (Ma1). As a result, writing is performed to the write target memory cell transistor (Ma1) using the DRAM cell portion (sub-bit line BLsa1) as a write buffer.

That is, the write data stored in the sub bit line capacitance Co is "0" (sub bit line BLsa1 = + 5).
If V), hot electrons are injected into the floating gate of the write target memory cell transistor (Ma1) to raise its threshold value to, for example, 6.5 V or more, and the write data is "1" (sub bit line BLsa1 = 0 V). Then, the hot electron injection is not performed and the threshold value of the memory cell transistor (Ma1) to be written is kept at 2.5 V at the time of erasing.

"Read Operation" (1) A DRAM cell portion (sub bit line BL) including a memory cell transistor (eg, Ma1) to be read.
A row (gate line ST1) and a column (bit line BLa1) of the equivalent capacitance Co of sa1 are designated by a row / column decoder (not shown) to turn on the selection transistor (Tsa1). As a result, the DRAM cell portion (sub-bit line BLs
The potential of a1) is the memory cell transistor (M
It is precharged to a low voltage (for example, +1 to 2 V) such that electrons (hot electrons) are not injected into a1). To do so, the column (bit line BLa
1) The potential is set low (for example, + 2.5V).

(2) The potential of the control gate (word line W1) of the memory cell transistor (Ma1) to be read is set to data "0" (threshold value + 6.5V) and data "
Intermediate potential of 1 "(threshold value + 2.5V) (around + 4V)
Set to.

If the data stored in the memory cell transistor (Ma1) to be read is "0", this transistor (Ma1) remains off and the potential of the DRAM cell portion (sub-bit line BLsa1) is set. It is at the electric potential (+1 to 2 V). This potential is the sub-bit line BLsa
It is detected by a sense amplifier (not shown) connected to 1, and is read out as data "0".

If the data stored in the memory cell transistor (Ma1) to be read is "1", this transistor (Ma1) is turned on (the memory cell current flows), so that the DRAM cell portion (sub-bit line BLsa1) is The potential drops to almost 0V. This approximately 0V potential is detected by a sense amplifier (not shown) connected to the sub bit line BLsa1 and is read out as data "1" to the outside.

"Refresh Operation" (1) The voltage information (high voltage / low voltage) stored in the capacitance Co of the DRAM cell portion (sub-bit line BLsa1) is periodically read by a sense amplifier (not shown).

(2) The sense amplifier uses the sub bit line BLs.
High voltage information of a1 (+ 5V for writing, + 1-2 for reading)
At the same time that V) is detected, the sub-bit line BLsa1 is recharged with the same voltage as the detected voltage. Similarly, the sense amplifier detects the low voltage information (0 V) of the sub bit line BLsa1 and, at the same time, recharges the sub bit line BLsa1 with the same voltage as the detected voltage.

As described above, the voltage information stored in the DRAM cell portion (sub-bit line BLsa1) is refreshed at the time of reading data or at every predetermined refresh cycle (this is a well-known DRAM refresh). The behavior is the same). As a result, the information on the DRAM cell portion (information on the voltage charged in the capacitor Co) is maintained unless it is rewritten by an external device or the power of the device is turned off.

Next, a nonvolatile semiconductor memory device according to the second embodiment of the present invention will be described with reference to FIG. The configuration of the embodiment of FIG. 4 is the same as that of the word line drive pulse generation circuit 2a of FIG. 1 except that the configuration of the word line drive pulse generation circuit 2a is the same, and the description of the same portions will be omitted.

The word line drive pulse generation circuit 2a includes a CMOS inverter 6 composed of transistors T8 + T9,
CMOS inverter 7 composed of transistors T10 + T11 and CMOS composed of transistors T12 + T13
A speed-up circuit 9 (C including an inverter 8 and a series circuit of inverters I1 and I2 and a capacitor C1)
When the rising / falling speed of the input pulse of the MOS inverter 8 is increased), the normally-on transistor T14
(It becomes a selection transistor if the gate potential is controlled)
And a positive feedback transistor T15, the drains of the transistors T11 and T12 are connected to each other, connected to the input terminal of the CMOS inverter 6, and 0 V is applied to the connection point.

The positive power supply of the CMOS inverter 7 (the source side of the P-channel MOS transistor T10) is the voltage + 3V (or + 5V) corresponding to the positive pulse potential of the word line drive pulse output WDPOUT, and its output terminal is the P-channel. It is connected to the source of the MOS transistor T8.

Further, the negative power source (N
The source side of the channel MOS transistor T13) has a voltage of -10 V corresponding to the negative pulse potential of the word line drive pulse output WDPOUT, and its output terminal is connected to the source of the N channel MOS transistor T9.

The source of the N-channel MOS transistor T11 and the drain of the P-channel MOS transistor T12 are connected to the input terminal of the CMOS inverter 6. The output terminal of the speed-up circuit 9 and the drain of the N-channel MOS transistor T15 are connected to the input terminal of the CMOS inverter 8, and the gate of the transistor T15 is connected to the output terminal. Transistor T15
Source is connected to a negative power supply of -10V.

A pulse having a peak value of 5V is applied to the input terminals of the CMOS inverters 7 and 8, a positive voltage + 3V (or + 5V) is applied to the source of the transistor T10, and a negative voltage is applied to the source of the transistor T13. A voltage of -10V is applied.

When word line drive signals WDSIN1 and WDSIN2 as shown in FIGS. 5A and 5B are input to the word line drive pulse generation circuit 2a of FIG. 4, the positive power supply voltage of the CMOS inverter 7 becomes + 3V. Then, Fig. 5 (c)
A word line drive pulse WDPOUT as shown in is obtained.

When word line drive signals WDSIN1 and WDSIN2 as shown in FIGS. 5D and 5E are input to the word line drive pulse generation circuit 2a shown in FIG.
Assuming that the positive power supply voltage of the OS inverter 7 is + 5V, FIG.
The word line drive pulse WDPOUT as shown in (f) is obtained.

The pulse W is shown in FIGS. 5C and 5F.
The reason why the waveform of DPOUT is changed is to suggest various variations.

Word line drive pulse WDPO of FIG. 5 (c)
The UT is the memory cell transistors Ma1 to Ma2 / of FIG.
If given to Mb1-Mb2, pulse WDPOUT -1
While pulling out electrons little by little from the floating gate of each memory cell transistor at 0V, the threshold voltage VTH of each memory cell transistor is changed to pulse WDPOU.
It can be converged to a value corresponding to + 3V of T.

Further, the word line drive pulse W of FIG.
DPOUT is connected to the memory cell transistors Ma1 to Ma of FIG.
If given to a2 / Mb1 to Mb2, the pulse WDPOUT
At −10 V, while pulling out electrons little by little from the floating gate of each memory cell transistor, the threshold voltage VTH of each memory cell transistor is changed to pulse WD.
It can be converged to a value corresponding to + 5V of POUT.

Next, the effect when the leakage of the charge precharged to the sub-bit line BLsa1 is large due to the leakage current component equivalent resistance Ro shown in FIG. 3B will be described.

When the word line drive pulse generation circuit 2a of FIG. 4 is operated with the waveforms of FIGS. 5 (d) to 5 (f),
FIG. 6A exemplifies the voltage waveform VFG of the floating gate of the MOS transistor forming each memory cell,
FIG. 6B exemplifies the voltage change VBL of the sub bit line to which this MOS transistor is connected, and FIG. 6C shows this M change.
Voltage waveform VC of control gate of OS transistor
G is illustrated.

In FIG. 6, (a) corresponds to the memory cell transistor Ma1 and the like of FIG. 4, (b) corresponds to the memory cell transistor Mb1 and the like of FIG. 4, and (c) shows the third cell not shown. It is considered to correspond to the memory cell transistor connected to the sub bit line.

When the value of the equivalent resistance Ro shown in FIG. 3B is small, that is, when the leakage current (leakage current) of the sub bit line is large, the floating gate voltage VFG does not easily converge to a desired value. FIG. 6A shows a waveform in such a case.

That is, as shown in FIG. 6C, the peak value is 5 V for erasing the nonvolatile memory cell transistor.
When a pulse oscillating from −10 V to −10 V is applied to the control gate of the memory cell transistor, the floating gate voltage VFG oscillates according to the amplitude of the pulse applied to the control gate electrode, as shown in FIG. 6A. In the process, due to the leakage current of the sub bit line (leakage current flowing through the resistor Ro), as shown in FIG. 6B, the nonvolatile memory cell transistor (a)
(B) (c) Sub-bit line voltage VB connected to each
L falls sharply (at different rates of change). However, if the sub-bit line potential drops too quickly, the nonvolatile memory cell transistors (a), (b) and (c) having different floating gate voltages VFG can easily reach the predetermined threshold voltage VTH. Does not converge.

If the embodiment of FIG. 3B is adopted, the drop of the sub-bit line voltage as shown in FIG. 6B can be prevented by the intermittent ON operation of the bit line selection transistor Tsa1. Convergence of the threshold voltage VTH (corresponding to the floating gate voltage VFG) of the memory cell transistor to a desired value can be ensured.

Next, a nonvolatile semiconductor memory device according to the third embodiment of the present invention will be described with reference to FIG.

FIG. 7A shows an embodiment in which a large leakage current steadily flows through the sub-bit lines BLsa1 and BLsb1. Therefore, a current supply means (compensated for the sub-bit line leakage current) is provided. Ra1 and Rb1). That is, the resistor Ra1 is provided between the main bit line BLa1 and the sub bit line BLsa1 of the memory cell block 1a, and the resistor Rb1 is provided between the main bit line BLb1 and the sub bit line BLsb1 of the memory cell block 1b.

When the leakage current is large, the sub bit line BL
The precharge potential of sa1 drops rapidly in a short time as shown in (c) of FIG. 6B.
Therefore, a current equal to or more than the leakage current due to the equivalent resistance Ro is supplied from the main bit line BLa1 to the sub bit line BLsa1 via the resistance Ra1 so as to suppress the decrease in the precharge potential of the sub bit line BLsa1. There is. Similarly, a current equal to or larger than the leakage current due to the equivalent resistance Ro is passed from the main bit line BLb1 to the sub bit line B through the resistance Rb1.
It is supplied to Lsb1 to suppress a decrease in the precharge potential of the sub bit line BLsb1.

FIG. 7C shows an equivalent circuit of a main part of the EEPROM configuration of FIG. 7A, and FIG. 7B shows a voltage waveform applied to each part of this equivalent circuit. Co represents an equivalent capacitance component (stray capacitance) parasitic on the sub-bit line BLsa1, Ro represents an equivalent resistance determined by the voltage applied to the sub-bit line BLsa1 and the leakage current, and Ra1
Is a leakage current compensating resistor that supplies the sub-bit line BLsa1 with a current equal to or greater than the leakage current due to the equivalent resistor Ro.

The leakage current compensation resistor Ra1 (R
b1) prevents the precharge potential of the sub-bit line BLsa1 (BLsb1) from decreasing, and FIG.
If the word line drive pulse as shown in the lower part is given to the control gate of the memory cell transistor, the threshold voltage VTH of each memory cell transistor is surely converged to the desired value corresponding to + 3V of the word line drive pulse. You can

Next, a nonvolatile semiconductor memory device according to the fourth embodiment of the present invention will be described with reference to FIG.

In FIG. 8A, the memory cell array 1
Has the same configuration as that of the embodiment of FIG. 7, and the current supply circuit for compensating the leakage current is a resistor-connected transistor Ta.
(Tb) and resistor Ra1 (Rb1) are connected in series. The drain of the transistor Ta (Tb) is connected to the main bit line BLa1 (BLb1), the source thereof is connected to one end of the resistor Ra1 (Rb1), and the resistor Ra1 is connected.
The other end of (Rb1) is the sub-bit line BLsa1 (BLsb
Connected to 1).

FIG. 8C shows an equivalent circuit of the main part of FIG. 8A, and FIG. 8B shows a voltage waveform applied to each part. The resistor-connected transistor Ta is shown in FIG.
When turned on by the + 5V signal in the middle and upper stages, a current equal to or higher than the leakage current flows through the resistor Ra1 to the sub bit line BL.
supplied to sa1.

In the embodiment of FIG. 7A or FIG. 8A, the leakage current compensating resistor Ra1 or Rb1 is used.
For this, the high resistance of a diode connected in reverse bias may be used.

The cause of the leakage current of the sub-bit line is that it is caused by a tunnel current between drains caused when the gate voltage of the memory cell transistor is negative, a crystal defect around the drain diffusion layer, and the like. Seems like
In particular, the former is the main factor.

In the embodiment shown in FIG. 8, a leakage current compensating current is supplied to the sub bit line connected to the drain of the memory cell transistor in synchronization with the leakage current, so that the fluctuation of the sub bit line voltage can be reduced. You can

FIG. 3C, FIG. 7C or FIG.
In the embodiment of (c), the charge escaping via the leakage current component equivalent resistance Ro is made into the leakage current compensation circuit (Tsa1, Ra).
1 or Ta + Ra1), the charge accumulated in the sub bit line BLsa1 can be held for a long time while the bit line selection transistor Tsa1 is turned off.

Therefore, the bit line selection transistor T
By using sa1 as a transfer gate and the equivalent capacitance Co of the sub-bit line BLsa1 as an information storage capacitance, a DRAM having a long refresh cycle can be obtained.
A configuration can be realized.

In the embodiment shown in FIGS. 3C and 8C, the high potential information of sub bit line BLsa1 can be maintained even if there is a leakage current. In addition, the sub bit line BLsa1
For the low potential information of the transistor Tsa1 or Tsa
By turning off a, the information can be maintained. However, in the embodiment of FIG. 7C, if the potential of the main bit line BLa1 remains high, the leakage compensation current always flows into the sub bit line BLsa1 via the compensation resistor Ra1, so that the sub bit line BLsa1 goes low. This makes it unsuitable for maintaining potential information for a long time. Therefore, in the case of adopting the embodiment of FIG. 7C, the main bit line BLa1 is held while the low potential information is held in the sub bit line BLsa1.
It is preferable to reduce the potential of.

FIG. 9 shows the floating gate voltage (VF
The operation states of the non-volatile memory cell transistors (a; for example Ma1) and (b; different for example Mb1) of different G) are shown.

As shown in FIG. 9C, positive and negative voltage [3] is applied to the floating gate of the memory cell transistor.
V, −10 V] and a pulse with a period of 30 μsec that changes in amplitude is applied. In this case, as shown in FIG.
The floating gate voltage (VFG) changes in response to the period of this pulse. Memory cell transistor (a)
And (b) different floating gate voltages (V
FG) is the control gate voltage −1 of FIG.
At 0V, it decreases gradually due to the tunnel current flowing from the floating gate and gradually converges to a predetermined voltage.

In FIG. 9B, in the drain voltage / bit line voltage VBL (voltage of the sub bit line BLsb1) of the memory cell transistor (B; for example, Mb1), electrons are extracted from the floating gate of this transistor by a predetermined amount. After that, pulsation occurs due to the rise of Rb1 due to the supply current and the fall due to the turning on of the memory cell transistor.

On the other hand, as shown in FIG. 9B, the drain voltage of the memory cell transistor (a; Ma1, for example) holds a sufficient potential until the electrons stored in the floating gate are largely extracted. Until the predetermined amount of drawing is completed (this memory cell transistor is off), the pulsation is almost absent.

In the embodiment of FIG. 7A or FIG. 8A, the integral time constant (RoCo) determined by the product of the equivalent resistance Ro and the capacitance component Co is applied to the floating gate of the memory cell transistor. It is set to be longer than the cycle of the word line drive pulse. This is shown in FIG.
This is to suppress the voltage fluctuation of the sub bit line due to the application of the word line drive pulse as shown in (b) of (b).
For example, if the period of the word line drive pulse is 30 μs, this time constant (RoCo) is 100 to 300 μsec.
It is set to a degree. Specifically, the sub bit line equivalent capacitance C
If o is about 100 to 300 fF, the resistance value of the resistor Ra1 is set to about 1000 MΩ.

FIG. 10 shows an example of the structure of a MOS diode with a control gate which can be used as an alternative means of the compensation current supply circuit (Ta, Ra1) shown in FIG. 8C.

That is, the N formed in the P-type substrate 15
A P-type well 11 is formed in the mold well 10. In the P-type well 11, an N-type source region 12s and a drain region 12d are formed. A gate electrode 13 is formed on the channel region between the regions 12s and 12d. A voltage signal similar to that applied to the gate of the transistor Ta in FIG. 8C is applied to the gate electrode 13.

The main bit line (BLa1) is connected to the N-type source / drain regions 12s and 12d and the N-type well 10, and the P-type well 11 is connected to the sub-bit line (BLsa1) through the high concentration P + region 14. Has been done. By synchronizing the voltage signal applied to the gate electrode 13 (the middle upper waveform in FIG. 8B) with the voltage signal applied to the gate of the bit line selection transistor Tsa1 (the middle lower waveform in FIG. 8B). , It is possible to suppress the voltage fluctuation of the sub bit line (BLsa1).

As described above, in the device of the embodiment of the present invention, the compensation current for supplying a current exceeding the leakage current to the sub-bit line so that the sub-bit line can maintain its potential after being precharged. It has a supply circuit. That is, a current source circuit formed by a resistor (Ra1) or the like is provided between the main bit line and the sub bit line. This compensation current supply circuit is disclosed in the embodiment (Ra1, Ta, FIG. 10). It goes without saying that various well-known circuits having equivalent circuit functions can be used without being limited to the gated MOS diode).

The nonvolatile semiconductor memory device of the present invention is not limited to the memory cell array structure as shown in FIG. 1, but a memory having a large number of memory cell transistors (several hundreds or more) on each of a large number of main bit lines. It can be applied to various memory cell arrays such as cell blocks connected to each other.

FIG. 12 shows the structure of a nonvolatile semiconductor memory device according to the fifth embodiment of the present invention. This is Figure 1
Alternatively, it is also a modification of the embodiment of FIG.

The number of circuits of the word line switch circuit 3 of FIG. 1 is as shown in FIG.
b) memory cell transistors Ma1 to Ma2 constituting
You may make it match with the number of (Mb1-Mb2). For example, if the memory cell block 1a is composed of 1024 memory cell transistors Ma1 to Ma1024, 1024 word line switch circuits are prepared. Alternatively, the word line switch circuit 3 is configured by a multiplexer that sequentially connects the output of the word line drive pulse generation circuit 2 to 1024 word lines W1 to W1024.

In FIG. 12, if all the word line switch circuits 31 to 32 are turned on at the same time to connect all the word lines to the output of the word line drive pulse generation circuit 2 at the same time, all the memory cell blocks The memory cell transistors can be simultaneously erased (this is the batch erase operation of the flash EEPROM).

On the other hand, if the word line switch circuits 31 to 32 are turned on one by one to connect a specific word line to the output of the word line drive pulse generating circuit 2, a specific memory in each memory cell block is formed. Only the cell transistor can be erased (bit-by-bit erase operation).

FIG. 13 shows a structure of a nonvolatile semiconductor memory device according to the sixth embodiment of the present invention. This is Figure 1
Alternatively, it is also a modification of the embodiment of FIG.

The number of circuits of the word line switch circuit 3 of FIG. 1 is as shown in FIG.
You may make it correspond to the number of b). For example, if the memory cell block is composed of 512 blocks, 512 word line switch circuits are prepared. Alternatively, the word line switch circuit 3 is configured by a multiplexer that sequentially connects the output of the word line drive pulse generation circuit 2 to 512 block unit word lines.

In FIG. 13, if all the word line switch circuits 3a and 3b are turned on at the same time and all the word lines are simultaneously connected to the output of the word line drive pulse generation circuit 2, all the memory cell blocks The memory cell transistors can be simultaneously erased (this is the batch erase operation of the flash EEPROM).

On the other hand, if the word line switch circuits 3a to 3b are turned on one by one and connected to the output of the word line drive pulse generation circuit 2 for each word line of a specific memory cell block, each memory cell block It is possible to erase all the memory cell transistors in each block for each block (block erase operation).

The structure of the memory cell array can be further modified. For example, as shown in FIG. 14, the source line SL to which the source side selection transistor Trs1 is connected
When the sub-source line SLb is provided in addition to a, the leakage current of the sub-bit line can be supplemented by connecting the compensation current supply circuit between the source line and the sub-source line. That is, the resistor-connected transistors Ta and Tb used in the embodiment of FIG. 8A are deleted and their drains / sources are short-circuited, and instead the third MOS is used.
The drain / source of the transistor Tab is connected to the source line SL.
The leakage current compensation can be performed by connecting between the a / sub source line SLb and turning on / off the third MOS transistor Tab at the same timing as the resistor connection transistors Ta and Tb. At this time, the leakage current compensation can be performed only when the selection transistor Trs1 of the source circuit (SLa / SLb) is turned on by the signal of the gate line SL1.

FIG. 15 is a circuit diagram illustrating a method of generating a multilevel program level applied to each embodiment of the present invention.

The stabilized multi-value level generating power supply Vs is connected to the resistor R via the multi-value level generating variable current source Is.
The series circuits of 1 to R3 are connected in parallel. This multi-level level generating variable current source Is is composed of a constant current source whose output current value can be arbitrarily set by a program level change signal PLC from the outside. For example, R1 = 2 kΩ, R
When 2 = 1 kΩ and R3 = 1 kΩ, the resistance R is set when the output current of the current source Is is set to 1 mA by the signal PLC.
Program level from 1 to + 2V is obtained, R1 + R2
Gives a program level of + 3V from R1 + R2 +
A program level of + 4V is obtained from R3. If it is desired to change these program levels, the output current of the current source Is may be changed by the signal PLC.

Program level + 2V from resistor R1
Is the drain of the N-channel MOS transistor TS1.
It is connected to the source circuit of the P-channel MOS transistor T2 in the word line drive pulse generation circuit 2 via the sources. The program level + 3V from the resistor R2 is
It is connected to the source circuit of the transistor T2 via the drain and source of the N-channel MOS transistor TS2. The program level + 4V from the resistor R3 is connected to the source circuit of the transistor T2 via the drain and source of the N-channel MOS transistor TS3.

Only one of the transistors TS1 to TS3 becomes conductive depending on the contents (PLS1 to PLS3) of the 3-bit program level selection signal PLS applied to their gates.

For example, when the logic level of PLS1, PLS2, PLS3 is "100", only transistor TS1 is conductive and + 2V is applied to the source circuit of P channel MOS transistor T2 in word line drive pulse generation circuit 2.
The program signal E20 is output. As a result, from the circuit 2 to the word lines (W1, W2,
...) word line drive pulse output WDPOUT
Is a signal waveform in which + 2V and −10V are alternately repeated.

When the logic level of PLS1, PLS2 and PLS3 is "010", only the transistor TS2 becomes conductive and the P channel M in the word line drive pulse generating circuit 2 is turned on.
A program signal E20 of + 3V is output to the source circuit of the OS transistor T2. As a result, the word line drive pulse output WDPOUT applied to the word lines (W1, W2, ...) Of the memory cell array 1 from the circuit 2 is + 3V.
The resulting signal waveform alternates between -10V (this waveform has been adopted in the previously described embodiment).

When the logic level of PLS1, PLS2, PLS3 is "001", only the transistor TS3 becomes conductive, and the P channel M in the word line drive pulse generation circuit 2 is turned on.
A program signal E20 of + 4V is output to the source circuit of the OS transistor T2. As a result, the word line drive pulse output WDPOUT given to the word lines (W1, W2, ...) Of the memory cell array 1 from the circuit 2 is + 4V.
The signal waveform has an alternating repetition of -10V.

When the circuit configuration of FIG. 15 is incorporated in a semiconductor IC, it is difficult to accurately set the absolute values of the resistance values of R1 to R3, but the relative values of these resistance values (the ratio of each resistance) are accurate. Can be set to. So R
When the resistance values of 1 to R3 are slightly deviated from the designed values, the output current value of the current source Is is slightly adjusted by the signal PLC, whereby accurate multilevel program levels + 4V, + 3V and + 2V can be obtained.

When the pulse WDPOUT in which the accurate multilevel program levels + 4V, + 3V or + 2V and -10V obtained in this way are alternately repeated is applied to the word line of the memory cell 1 for 10 pulses or more, for example, on that word line. The threshold value of the specific memory cell transistor of (1) corresponds to the level designated by the signal PLS (for example, +
It converges to 3.5V, + 2.5V or + 1.5V with almost no variation.

Thus, one memory cell transistor stores multivalued data according to the content of the program level selection signal PLS.

The multi-valued data of a plurality of threshold values (+ 3.5V, + 2.5V, + 1.5V) stored in one memory cell is read at a potential corresponding to the potential to be read. After making the transistor conductive, the potential of the bit line connected to the transistor may be detected by a sense amplifier (not shown).

More specifically, [1a] DRAM cell portion (sub-bit line B) including a memory cell transistor (eg, Ma1) to be read.
A row (gate line ST1) and a column (bit line BLa1) of the equivalent capacitance Co of Lsa1 are designated by a row / column decoder (not shown) to turn on the selection transistor (Tsa1). As a result, the DRAM cell portion (sub-bit line BLs
The potential of a1) is the memory cell transistor (M
It is precharged to such a low voltage that electrons (hot electrons) are not injected into a1). In order to do so, the potential of the column (bit line BLa1) at the time of reading is set low (for example, + 1V).

[2a] The potential of the control gate (word line W1) of the memory cell transistor (Ma1) to be read is set to the data "0" (threshold value + 6.5V) and the data "1a" (threshold value +1. It is set to a potential slightly lower than the middle of 5V) (around + 3V).

If the data stored in the memory cell transistor (Ma1) to be read is "0", this transistor (Ma1) remains off, and the potential of the DRAM cell portion (sub-bit line BLsa1) is set. It is at the potential (+ 1V). This potential is detected by a sense amplifier connected to the sub-bit line BLsa1 and data "
It is read out as "0".

Further, the data stored in the memory cell transistor (Ma1) to be read is "1a" (threshold value +
If the voltage is 1.5 V, the transistor (Ma1) is turned on (memory cell current flows), so that the potential of the DRAM cell portion (sub-bit line BLsa1) drops to almost 0 V. This approximately 0V potential is detected by a sense amplifier (not shown) connected to the sub bit line BLsa1 and data "1a" is detected.
Is read out as.

[1b] Row (gate line ST1) of DRAM cell portion (equivalent capacitance Co of sub-bit line BLsa1) including memory cell transistor (Ma1) to be read
And a column (bit line BLa1) are designated by a row / column decoder (not shown) to turn on the selection transistor (Tsa1). As a result, the DRAM cell portion (sub-bit line BL
The potential of sa1) is precharged to such a low voltage that electrons (hot electrons) are not injected into the memory cell transistor (Ma1) to be read. In order to do so, the potential of the column (bit line BLa1) at the time of reading is set low (for example, + 1.5V).

[2b] The potential of the control gate (word line W1) of the memory cell transistor (Ma1) to be read is set to data "0" (threshold value +6.5 V) and data "1b" (threshold value +2. 5V intermediate potential (+ 4V
Before and after).

If the data stored in the memory cell transistor (Ma1) to be read is "0", this transistor (Ma1) remains off and the potential of the DRAM cell portion (sub-bit line BLsa1) is set. It is at the electric potential (+ 1.5V). This potential is the sub-bit line BLsa
It is detected by a sense amplifier connected to 1) and is read out as data “0” to the outside.

Further, the data stored in the memory cell transistor (Ma1) to be read is "1b" (threshold value +
If the voltage is 2.5V, the transistor (Ma1) is turned on (memory cell current flows), so that the potential of the DRAM cell portion (sub-bit line BLsa1) drops to almost 0V. This approximately 0 V potential is detected by a sense amplifier (not shown) connected to the sub bit line BLsa1 and data "1b" is detected.
Is read out as.

[1c] Row (gate line ST1) of the DRAM cell portion (equivalent capacitance Co of sub-bit line BLsa1) including the memory cell transistor (Ma1) to be read
And a column (bit line BLa1) are designated by a row / column decoder (not shown) to turn on the selection transistor (Tsa1). As a result, the DRAM cell portion (sub-bit line BL
The potential of sa1) is precharged to such a low voltage that electrons (hot electrons) are not injected into the memory cell transistor (Ma1) to be read. To do so, the potential of the column (bit line BLa1) at the time of reading is set to a low level (for example, + 2V).

[2c] The potential of the control gate (word line W1) of the memory cell transistor (Ma1) to be read is set to data "0" (threshold value + 6.5V) and data "1b" (threshold value +3. 5V) intermediate potential (+ 5V
Before and after).

If the data stored in the memory cell transistor (Ma1) to be read is "0", this transistor (Ma1) remains off and the potential of the DRAM cell portion (sub-bit line BLsa1) is set. It is at the electric potential (+ 2V). This potential is detected by a sense amplifier connected to the sub-bit line BLsa1 and data "
It is read out as "0".

Further, the data stored in the memory cell transistor (Ma1) to be read is "1c" (threshold value +
If the voltage is 3.5 V, the transistor (Ma1) is turned on (memory cell current flows), so that the potential of the DRAM cell portion (sub-bit line BLsa1) drops to almost 0 V. This approximately 0V potential is detected by a sense amplifier (not shown) connected to the sub-bit line BLsa1 and data "1c" is detected.
Is read out as.

When the read operation of each of the above [1a] [2a], [1b] [2b] and [1c] [2c] is performed on one addressed memory cell, the data stored in that cell is It can be distinguished whether it is "1a", "1b" or "1c". An example of the method of distinction is shown below.

That is, when the data other than "0" is detected by the sense amplifier when the word line potential during reading is set to [2a] (+ 3V), the multi-valued data stored in the cell is It is "1a".

When the word line potential during reading is set to [2a] (+ 3V), data other than "0" is not detected by the sense amplifier, but when the word line potential during reading is [2b] (+ 4V) ) When set to "
If data other than 0 "is detected by the sense amplifier, the multi-valued data stored in the cell is" 1b ".

When the word line potential during reading is set to [2a] and [2b] (+ 3V and + 4V), data other than "0" is not detected by the sense amplifier in either case. If the data other than "0" is detected by the sense amplifier when the word line potential is set to [2c] (+ 5V), the multi-valued data stored in the cell is "1c".

If the data detected by the sense amplifier is "0" regardless of whether the word line potential at the time of reading is [2a] to [2c] (+ 3V to + 5V), the data stored in the cell is determined. The value data is “0”.

Although the charge extraction completion detection circuits (4a, 4b) are individually provided to the sub bit lines (BLsa1, BLsb1) in the above-described embodiments (FIG. 1 and the like), these charge extraction completion detections are performed. The circuits (4a, 4b) may be connected to the corresponding main bit line (BLa1, BLb1) side. In this case, it is necessary to control the bit line select transistors (Tsa1 and Tsb1) to be conductive when the charge extraction completion is detected. However, since the number of main bit lines is usually much smaller than that of sub bit lines, if the charge extraction completion detection circuits (4a, 4b) are provided on the main bit line side, the charge extraction completion detection circuit (4a The required number of 4b) can be greatly reduced.

[0176]

As described above, according to the non-volatile semiconductor memory device of the present invention, after the sub-bit line is precharged, a pulse oscillating positively or negatively is applied to the floating gate of the non-volatile memory cell transistor. Since different floating gate voltages of a large number of memory cell transistors can be converged to a predetermined potential, accurate write / erase operations can be performed by an extremely simple means.

Since there is little variation in the writing result, 1
Even if multi-valued levels are stored in one memory cell transistor, they can be reliably distinguished and read.

[Brief description of drawings]

FIG. 1 is a circuit diagram illustrating a configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

2 is a diagram for explaining the circuit operation of a word line drive pulse generation circuit (level shifter) used in the device of FIG.
(A) shows an input signal waveform and (b) shows an output pulse waveform.

3 is a diagram for explaining the circuit operation of a bit line selection transistor and a memory cell transistor in the device of FIG. 1, where (a) shows a voltage waveform of a main part of the circuit and (b) shows a capacitance component and a leakage current on the bit line. An equivalent circuit that allows for the components is shown.

FIG. 4 is a circuit diagram illustrating a configuration of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

5 illustrates two examples of the circuit operation of a word line drive pulse generation circuit (level shifter) used in the device of FIG. 4, where (a) shows a first input signal waveform in the first example (b). Shows the second input signal waveform in the first example (c) shows the output pulse waveform in the first example (d)
Shows the first input signal waveform in the second example, (e) shows the second input signal waveform in the second example, and (f) shows the output pulse waveform in the second example.

6 is an operation of a memory cell forming the nonvolatile semiconductor memory device of FIG. 4 when the word line drive pulse generation circuit (level shifter) of FIG. 4 is operated with the waveforms of FIGS. 5D to 5F. FIG. 5A shows an example of a voltage waveform of a floating gate of a MOS transistor forming each memory cell, FIG. 9B shows an example of voltage change of a bit line to which the MOS transistor is connected, and FIG. M above
An example of the voltage waveform of the control gate of the OS transistor is shown.

FIG. 7 is a diagram for explaining the configuration and operation of a nonvolatile semiconductor memory device according to a third embodiment of the present invention,
(A) shows an example of a main circuit, (b) shows a voltage waveform of a main part of this circuit, and (c) shows an equivalent circuit in which a capacitance component and a leakage current component on a bit line in this circuit example are considered.

FIG. 8 is a diagram for explaining a configuration and an operation of a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention,
(A) shows an example of a main circuit, (b) shows a voltage waveform of a main part of this circuit, and (c) shows an equivalent circuit in which a capacitance component and a leakage current component on a bit line in this circuit example are considered.

9A and 9B are diagrams for explaining the operation of a memory cell included in the nonvolatile semiconductor memory device of FIG. 8, in which FIG. 9A shows an example of a voltage waveform of a floating gate of a MOS transistor included in each memory cell, and FIG. An example of the voltage change of the bit line to which the MOS transistor is connected is shown (c) is the above M
An example of the voltage waveform of the control gate of the OS transistor is shown.

10 is a compensation current supply circuit (Ta,
6 is a semiconductor cross-sectional view illustrating the configuration of a MOS diode with a control gate that can be used as an alternative to Ra1).

FIG. 11 is a view for explaining a known EEPROM cell structure and threshold distributions of those cells, FIG. 11A shows an example of an offset gate type flash EEPROM threshold voltage distribution, and FIG. 11B shows a self-allan type flash EEPROM. An example of the threshold distribution is shown in (c) of FIG.

FIG. 12 is a circuit diagram illustrating a configuration of a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 13 is a circuit diagram illustrating a configuration of a nonvolatile semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 14 is a circuit diagram illustrating a configuration of a nonvolatile semiconductor memory device according to a seventh embodiment of the present invention.

FIG. 15 is a circuit diagram illustrating a method of generating a multilevel program level applied to each embodiment of the present invention.

[Explanation of symbols]

1 ... Memory cell array; 1a, 1b ... Memory cell block; 2, 2a ... Word line drive pulse generation circuit (level shifter; drive signal means); 3, 31, 32, 3a, 3b ...
Word line switch circuit; 4a, 4b ... Charge extraction completion detection circuit (CMOS inverter); 5a, 5b ... Switch circuit; 6, 7, 8 ... CMOS inverter; 9 ... Speed-up circuit; 10 ... N well; 11 ... P well 12S ...
N + source region; 12D ... N + drain region; 13 ... Gate electrode; ST1 ... Bit line selection gate line (conduction means); SL1 ... Source side selection gate line; BLa1, BL
b1 ... Main bit line; BLsa1, BLsb1 ... Sub bit line; W1, W2 ... Word line; WDSIN ... Word line drive signal input; WDPOUT ... Word line drive pulse output; T
sa1, Tsb1 ... Bit line selection transistor; Trs
1 ... Source side selection transistors; Ma1, Mb1, Ma
2, Mb2 ... Non-volatile memory cell transistor (N-channel MOS transistor having control gate and floating gate); Ca1, Cb1 ... Bit line capacitor; C1 ... Capacitor; Co ... Sub bit line equivalent capacitance; Ro ... Sub bit line leakage current Component equivalent resistance; Ra1,
Rb1 ... Leakage current compensation resistance (resistor); I1, I2 ... Inverter; T2, T4, T6, T8, T10, T12,
T14 ... P-channel transistor; T3, T5, T7,
T9, T11, T13, T15, TS1, TS2, TS
3 ... N-channel transistor; Ta, Tb ... Resistor connection transistor; Tab ... Third MOS transistor; 2
0 ... Multivalued program level generation circuit; Vs ... Multivalued level generation power supply; Is ... Multivalued level generation variable current source; R
1, R2, R3 ... Resistors for generating multilevel levels; PLC ... Program level change signal; PLS ... Program level selection signal; E20 ... Program signal.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location // H01L 27/115

Claims (9)

[Claims] 1. A memory cell array having a plurality of word lines and a plurality of bit lines, in which memory cells are arranged at intersections of the word lines and the bit lines; a floating gate for holding nonvolatile information; A memory cell transistor for controlling writing, erasing or reading of information held in the floating gate, which has a control gate connected to the word line and constitutes the memory cell; a first potential and Drive signal means for applying a drive signal, in which a second potential different from the first potential is alternately repeated, to the control gate of the memory cell transistor. 2. A memory cell array having a plurality of word lines and a plurality of bit lines, in which memory cells are arranged at intersections of the word lines and the bit lines; a floating gate holding nonvolatile information; A memory cell transistor for controlling writing, erasing or reading of information held in the floating gate, which has a control gate connected to the word line and constitutes the memory cell; a first potential and A non-volatile semiconductor memory device, comprising: a drive signal means for simultaneously applying to the control gates of the plurality of memory cell transistors a drive signal in which a second potential different from the first potential is alternately repeated. 3. A memory cell array having a plurality of word lines and a plurality of bit lines, in which memory cells are arranged at intersections between the word lines and the bit lines; a floating gate for holding nonvolatile information; A memory cell transistor for controlling writing, erasing or reading of information held in the floating gate, which has a control gate connected to the word line and constitutes the memory cell; a first potential and And a drive signal means for sequentially applying a drive signal in which a second potential different from the first potential is alternately repeated to the control gates of the plurality of memory cell transistors. 4. A memory cell array having a plurality of word lines and a plurality of bit lines, in which memory cells are arranged at intersections of the word lines and the bit lines; a floating gate for holding nonvolatile information; A memory cell transistor for controlling writing, erasing or reading of information held in the floating gate, the memory cell transistor having a control gate connected to the word line, and constituting the memory cell; A non-volatile semiconductor memory device, comprising: a drive signal means for applying a drive signal in which a potential and a second potential different from the first potential are alternately repeated to the control gate of the memory cell transistor. 5. A memory cell array having a plurality of word lines and a plurality of bit lines, in which memory cells are arranged at intersections of each word line and each bit line; a floating gate holding nonvolatile information; A memory cell transistor for controlling writing, erasing or reading of information held in the floating gate, the memory cell transistor having a control gate connected to the word line, and constituting the memory cell; Drive signal means for simultaneously applying to the control gates of the plurality of memory cell transistors a drive signal in which a potential and a second potential different from the first potential are alternately repeated; . 6. A memory cell array having a plurality of word lines and a plurality of bit lines, in which memory cells are arranged at intersections of the word lines and the bit lines; a floating gate for holding nonvolatile information; A memory cell transistor for controlling writing, erasing or reading of information held in the floating gate, the memory cell transistor having a control gate connected to the word line, and constituting the memory cell; A non-volatile semiconductor memory device, the drive signal means sequentially applying a drive signal in which a potential and a second potential different from the first potential are alternately repeated to the control gates of the plurality of memory cell transistors. . 7. The multilevel program level generating circuit, wherein the drive signal means generates a program signal having a multilevel level corresponding to program data to be stored in the memory cell transistor, and the multilevel program level generating circuit. A word line drive pulse generation circuit for generating, as the drive signal, a pulse in which the first potential corresponding to one of the multi-valued levels of the generated program signal and a second potential different from the first potential are alternately repeated. 7. The nonvolatile semiconductor memory device according to claim 4, further comprising: 8. A main bit line; a sub bit line having a capacitance component; and a capacitance component of the sub bit line being set to a potential of the main bit line by selectively connecting the sub bit line to the main bit line. A bit line selection transistor for precharging;
It has a floating gate for holding non-volatile information and a control gate for controlling writing, erasing or reading of information held in the floating gate, and information of potential precharged on the sub-bit line is written in the floating gate. And a drive signal means for simultaneously applying to the control gates of the plurality of memory cell transistors a drive signal in which a plurality of types of first potentials and a second potential different from these first potentials are alternately repeated. A nonvolatile semiconductor memory device characterized by the above. 9. A bit line that can be precharged to a first predetermined potential; a floating gate that holds non-volatile information, and a control gate that controls writing, erasing or reading of information held by this floating gate. A memory cell transistor having a drain connected to the bit line and a source connected to a predetermined source circuit, in which information of the potential precharged to the bit line is written to its floating gate; A select transistor selectively connected to a circuit of a second predetermined potential; a plurality of kinds of first potentials and a drive signal in which a second potential different from the first potentials is alternately repeated to control the plurality of memory cell transistors A non-volatile semiconductor, characterized by comprising: Storage device.