JPH08235853A - Semiconductor storage device - Google Patents

Abstract

PURPOSE: To use a dummy cell system even though a crossing is included in bit line pairs by selecting a dummy word line in accordance with the selected word line. CONSTITUTION: Dummy word line DWL0 to DWL3 are decoded by the position of selected word lines WL0 to WL3 and one out of every four lines becomes a selected condition. For each dummy word line, a dummy cell is provided and these dummy word lines DWL0 to DWL3 are placed two of each on the both sides of a crossing CP4 . Moreover, by row addresses RAi and RAj, each block 'a' through 'd' is being corresponded to block a: RAi=RAj=0, block b: RAi=0, RAJ=1, block c: RAi=1, RAj=0 and block d: RAi=RAJ=0. Furthermore, by a row address RAk, word lines WL0 , WL1 , ... are decoded as WL0 , WL1 , ... RAk=0, WL'0 , WL'1 ,...RAK=1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device, and more particularly to signal read error prevention.

[0002]

2. Description of the Related Art FIG. 4 shows a structure of a bit line pair of a conventional dynamic semiconductor memory device. Bit line pair BL, BL
A plurality of memory cells (Cs) is connected to the bar, and a word line signal (W
Transfer gates TG for receiving L ₀ , WL ₁ ...) Are connected. In addition, dummy cells (DC ₀ , DC ₁ ) for generating a reference level are provided on each bit line, and dummy word lines (DWL ₁ , DWL) connecting the dummy cells (DC ₀ , DC ₁ ) to the bit lines.
₁ ) is connected, the word line and the dummy word line rise, and after a signal voltage difference appears on the bit line pair, a sense amplifier (S
A) is connected. In addition, the bit line pair selected according to the column address is connected to the data input / output line pair (I / O, I
/ O bar), and transfer gates Q ₁ and Q ₁ are connected to this gate, and the output of the column decoder 1 is input to these gates.

Next, consider the signal voltage appearing on each bit line pair during signal reading. As shown in FIG. 5, each bit line is C ₁ with respect to the ground potential (fixed potential) via the cell plate or substrate, C ₂ with respect to the paired bit line, and the bit line of the adjacent bit line pair. It has a capacity of C ₃ . The bit line length is 1, and the memory cell capacity is Cs. "H" level: CsV _CC (V _CC write) "L" level: 0 (0 V write) in the memory cell. 1/2 CsV _CC (1/2 in Cs capacity) in the dummy cell.
V _CC writing, etc.) is stored.

When the bit line precharge level is V _CC , for example, when a memory cell connected to the bit line BL ₁ is selected and a dummy cell is connected to the bit line BL ₁ bar, the bit lines BL ₁ and BL ₁ are connected. Bar potential V _BL1 , V
_{/ BL1} (/ BL1 indicates BL1 bar)

[Equation 1]

From equations (1) to (3), the bit lines BL ₁ and BL
₁ bar thinking precharge level is equal both
The potential difference between the bit line pair is as follows from the equations (1)-(2) and (1)-(3).

[Equation 2]

The first term on the right side of the equation (4) is the original read voltage difference, and the second term is the noise component via the coupling capacitance from the bit lines BL ₀ bar and BL ₂ of the adjacent bit line pair.

By the way, as the degree of integration of the memory increases and the bit line pitch decreases, the capacitance C ₃ between the bit line pair increases, and the second term of the equation (4) becomes larger. Therefore, this causes a problem that the read voltage is remarkably impaired, the read margin is reduced, the soft error rate is deteriorated, and a malfunction finally occurs.

The following example is a device devised by the present inventors, in which the problems of the above device are solved, and the read voltage amplitude is reduced due to noise between adjacent bit line pairs due to the capacitance between bit lines. 2 shows a semiconductor memory device capable of completely reducing the value of zero to zero. In the semiconductor memory device according to this example, by providing an intersecting portion at one place or a plurality of places on the bit line pair, each pair of bit lines receives exactly the same capacitive coupling noise from the adjacent bit line pair, and reading is performed. The voltage difference is not reduced.

Next, a semiconductor memory device according to this conventional improvement will be described with reference to FIG. In this improved example, as shown in the figure, each bit line pair (BL ₀ , BL ₀ bar, B
L ₁ , BL ₁ bar, ...) are divided into four equal parts a, b,
divided into c and d, and these equal points CP ₁ , CP ₂ and CP
_{At 3} , they intersect as follows. BL _0, BL ₀ bar, intersect at CP _2, BL _1, BL ₁ bar, intersect at CP ₁ and CP _{3,'BL 2,} BL ₂ bars intersect at CP _{2,'BL 3,} BL ₃ bar Intersect at CP ₁ and CP ₃ , that is, the odd-numbered bit line pairs intersect at CP ₂ and the even-numbered bit line pairs CP ₁ and CP ₃ counting from the bit line pair BL ₀ , BL ₀ bar. Cross at. This allows
The capacitive coupling noise that each bit line pair receives from the adjacent bit line pair is as follows when considered in the same manner as the above-mentioned conventional example.

The capacitive coupling noise ΔV _BL1 ′, V received by the bit lines BL ₁ and BL ₁ bar from the adjacent bit line pair.
_{/ BL1} '(/ BL1 indicates BL1 bar)

(Equation 3) And both are exactly the same.

The capacitive coupling noise ΔV _BL2 ′, V that the bit lines BL ₂ and BL ₂ bar receive from the adjacent bit line pair.
_{/ BL2} '(/ BL2 indicates BL2 bar)

[Equation 4] And both are exactly the same.

Similarly, for all bit line pairs, the bit lines forming each pair receive the same capacitive coupling noise from the adjacent bit line pairs. The bit line pair BL ₀ , BL ₀ bar at the end of the memory array is also

(Equation 5) And both are exactly the same.

As described above, in this improved example, the capacitive coupling noises received by the bit line pairs adjacent to each other when the signals are read from the pair of bit lines are completely equal.
The reduction of the read voltage difference due to this noise can be completely eliminated, and the read margin can be expanded and the soft error rate can be improved.

FIG. 7 shows a second conventional improvement example. This modified example is different from the modified example of FIG. 6 in that odd-numbered bit line pairs (BL ₀ , BL ₀ bar, BL ₂ , BL ₂ bar, ...).
In addition, a crossing is added at the bit line end CP ₄ . Intersections CP ₁ , CP ₂ , CP ₃ provided by this improvement
In both cases, it is impossible to lay them out completely symmetrically with respect to the bit line pair. In the case of the improved example of FIG. 6, even-numbered bit line pairs (BL ₁ , BL ₁ bar,
BL _3, BL ₃ bars, ...) for each because crossing is 2 places, for the entire bit line pair can be balanced layout. For example, if the bit line is Al
If a wiring layer that can intersect with this layer is a poly-Si layer, C
In P ₁ , BL ₁ is Al, BL ₁ bar is poly Si, CP
_{In the case of 3} , BL ₁ may be made of poly-Si and BL ₁ bar may be made of Al, so that the imbalance of the stray capacitance of the bit line pair can be avoided. The improvement of FIG. 7 has a similar effect to this, in that a dummy crossing CP ₄ is added so as to balance even the odd-numbered bit line pairs, whereby the capacitance is balanced for all the bit line pairs. The state can be realized.

In the above-mentioned improved example, the bit line pair is divided into four sections and intersected at appropriate places, but this section is the same even if it is an integral multiple of 8 sections, 12 sections and the like. Produce the effect of. FIG. 8 shows an example in the case of 8 sections, which is a shape obtained by repeating the shape of FIG. 7 twice.
It is clear that the same effect as in the above example can be obtained.

Next, problems of such a conventional improved example will be described. Consider the case where the dummy cell method is applied when the bit line pair includes a cross as in the above-described improved example. Figure 9
Shows an example of the configuration when the conventional dummy cell system is applied to the device of FIG. In this figure, word lines (WL ₀ , WL
₀ ′, WL ₁ , WL ₁ ′, ...) And the intersection of the bit line indicates that a memory cell is arranged, and
The ∘ mark at the intersection of the dummy word lines (DWL ₀ , DWL ₁ ) and the bit line indicates that dummy cells are arranged.
As shown in the figure, the memory cell arrangement is such that the memory cell selected by the word line WL ₀ is the bit line BL.
_{0, BL 1, BL 2,} BL 3, is connected to ..., the memory cells selected by the word line WL ₀ next to the word line WL ₀ ', the bit lines BL ₀ bar, BL ₁ bar, BL ₂
They are arranged alternately, such as being connected to a bar, BL ₃ bar, .... This also applies to the dummy cell layout,
For example, the dummy cells selected by the dummy word line DWL ₀ are the bit lines BL ₀ , BL ₁ , BL ₂ , BL ₃ ,
The dummy cells connected to ... And selected by the dummy word line DWL ₁ are the bit lines BL ₀ bar, BL ₁ bar,
Connected to BL ₂ bar, BL ₃ bar, ....

Considering that the dummy cell needs to be connected to the bit line on the side opposite to the bit line to which the memory cell is connected (bit line on the reference side), FIG.
, If word lines WL ₀ and WL ₀ ′ in block a are selected, if WL ₀ is selected, DWL ₁ is selected, and if WL ₀ ′ is selected, DWL ₀ is selected. Good. When the word lines WL ₁ and WL ₁ ′ in the block b are selected, even if either DWL ₀ or DWL ₁ is selected, only half of the total number of bit line pairs are incompatible. If the word lines WL ₂ and WL ₂ ′ in block c are selected, and if WL ₂ is selected as well, DWL
_{When 0} is selected and WL ₂ ′ is selected, DWL ₁ may be selected. The same situation occurs when the word lines WL ₃ , WL ₃ ′ in block d are selected. As described above, the conventional dummy cell method cannot be applied when such a bit line pair includes a cross.

[0018]

Since the conventional semiconductor memory device is constructed as described above, when the bit line pair includes a crossing bit, the dummy cell is not connected to the bit line on the reference side in the normal dummy cell system. There was a problem that a line pair appeared and did not conform to that method.

The present invention has been made to solve the above problems, and an object thereof is to obtain a semiconductor memory device to which the dummy cell system can be applied even when the bit line pair includes a cross.

[0020]

A semiconductor memory device according to the present invention includes a first bit line to which half of a plurality of memory cells arranged in corresponding columns are connected and a remaining bit line, respectively. Of a plurality of bit line pairs each of which is connected to a second bit line, and a first bit line and a second bit line of a bit line pair of a corresponding column are arranged. Multiple sense amplifiers that detect the potential difference between
A plurality of first words each connected to a memory cell connected to the first bit line of the bit line pair in the odd column and a memory cell connected to the first bit line of the bit line pair in the even column A plurality of second lines each connected to a memory cell connected to a first bit line of a bit line pair in an odd column and a memory cell connected to a second bit line of a bit line pair in an even column. A plurality of word lines, each of which is connected to a memory cell connected to the second bit line of the bit line pair in the odd column and a memory cell connected to the first bit line of the bit line pair in the even column. A third word line, each connected to a memory cell connected to a second bit line of an odd column bit line pair and a memory cell connected to a second bit line of an even column bit line pair. A plurality of fourth word lines, bit lines of each of the above bit line pairs A reference potential generating means for generating a reference potential for giving and a reference potential generating means for connecting the reference potential generating means to a first bit line of a bit line pair in an odd column and a first bit line of a bit line pair in an even column. 1
Second reference word line and reference potential generating means for connecting the reference word line and the reference potential generating means to the first bit line of the bit line pair in the odd column and the second bit line of the bit line pair in the even column A third reference word line for connecting the generating means to the second bit line of the odd-numbered bit line pairs and the first bit line of the even-numbered bit line pairs, and the reference potential generating means to the odd-numbered column A fourth reference word line for connecting to the second bit line of the bit line pair and the second bit line of the bit line pair in the even-numbered column, and the selected word line is one of the first to fourth The reference word line decoding means for selecting any one of the first to fourth reference word lines is provided.

The semiconductor memory device according to the present invention is
A plurality of memory cells arranged in a plurality of columns and a plurality of rows; a first bit line connected to a half of a plurality of memory cells arranged in a plurality of columns, each of which is arranged in a corresponding column; A plurality of bit line pairs consisting of a second bit line to which the remaining half are connected, arranged in a plurality of columns, and a first bit line and a second bit line of the bit line pairs of the corresponding columns, respectively. A plurality of sense amplifiers for detecting the potential difference between the plurality of rows, each of which is connected to a first bit line of a bit line pair arranged in a corresponding row and arranged in an odd column A plurality of first word lines connected to a plurality of memory cells and a plurality of memory cells connected to a first bit line of a bit line pair arranged in an even number column, arranged in a plurality of rows,
A plurality of memory cells connected to a first bit line of a bit line pair arranged in a corresponding row and arranged in an odd column and a second bit line pair arranged in an even column, respectively.
A plurality of second word lines connected to a plurality of memory cells connected to the bit lines, arranged in a plurality of rows, arranged in corresponding rows and arranged in odd columns A plurality of memory cells connected to the second bit line of the bit line pair and a plurality of memory cells connected to the first bit line of the bit line pair arranged in an even column are connected. A plurality of memory cells connected to a second bit line of a bit line pair arranged in a corresponding row and arranged in a corresponding row and an even number; A plurality of fourth word lines connected to a plurality of memory cells connected to a second bit line of a bit line pair arranged in a column, arranged in a plurality of columns and four rows, and providing a reference potential Reference potential supply means for corresponding rows and odd columns The reference potential of the arranged reference potential supply means is applied to the first bit line of the bit line pair arranged in the odd-numbered columns, and the reference potential supply means of the corresponding row and the even-numbered column are arranged. The first of the bit line pairs in which the reference potentials are arranged in even columns
Reference word line for applying to the bit line of the first bit, the first bit of the bit line pair arranged in the odd column with the reference potential of the reference potential supply means arranged in the corresponding row and in the odd column And give it to the line,
A second reference word line for applying the reference potential of the reference potential supply means arranged in the corresponding row and in the even column to the second bit line of the bit line pair arranged in the even column. The reference potentials of the reference potential supply means arranged in rows and odd columns are applied to the second bit lines of the bit line pairs arranged in odd columns, and the reference potentials are arranged in corresponding rows and even columns. A third reference word line for applying the reference potential of the reference potential supply means to the first bit line of the bit line pair arranged in the even columns, and the reference arranged in the corresponding row and in the odd column. The reference potential of the potential supply means is applied to the second bit lines of the bit line pairs arranged in odd columns, and the reference lines arranged in corresponding rows and even columns are provided. The reference potential of the ground potential supply means those having a fourth reference word line for causing applied to a second bit line of the bit line pairs disposed in the even columns.

Further, the semiconductor memory device according to the present invention is
A memory cell array having a plurality of memory cells arranged in a plurality of columns and a plurality of rows, and half of the plurality of memory cells arranged in a plurality of columns of the memory cell array connected to each other are connected. A plurality of bit line pairs each including a first bit line and a second bit line to which the remaining half are connected, the bit line pairs being arranged in a plurality of rows of the memory cell array,
In a semiconductor memory device including a plurality of word lines connected to a plurality of memory cells arranged in corresponding rows, the memory cell array is divided into a plurality of blocks in a column direction, The blocks are connected to memory cells whose odd-numbered row word lines in the block are connected to either the first bit line or the second bit line of the plurality of bit line pairs, and the even-row word lines in the block are connected. The combinations of whether the lines are connected to the memory cells connected to the first bit line or the second bit line of the plurality of bit line pairs are different from each other. A reference potential generating means for generating a reference potential for reading the memory cell potential, and the reference potential generating means for each of a plurality of bit line pairs. A plurality of reference word lines for connecting to either of the first and second bit lines of the bit line pair, wherein the first and second bit lines of the bit line pair are provided in each of the plurality of bit line pairs. Of the plurality of reference word lines and the selected word line which are different from each other, and which word line of which of the plurality of blocks the word line of which is odd or even A reference word line decoding means for selecting one of the plurality of reference word lines based on the information on whether the line is a line.

The semiconductor memory device according to the present invention is
Having a plurality of memory cells arranged in a plurality of columns and a plurality of rows,
A memory cell array divided into a plurality of blocks in the column direction, a first bit arranged in a plurality of columns of the memory cell array, to which half of the plurality of memory cells arranged in a corresponding column are connected A plurality of bit line pairs each consisting of a line and a second bit line to which the other half is connected, arranged in a plurality of rows of the memory cell array, each connected to a plurality of memory cells arranged in a corresponding row A plurality of word lines, which are divided into blocks corresponding to the plurality of blocks, and the memory cells to which the memory cells to which the odd-numbered rows of word lines are connected are connected for each block. The combination of the first or second bit line and the first or second bit line of the bit line pair to which the memory cells to which the even-numbered word lines are connected is different, and further A plurality of reference potential supply means for providing a reference potential and a plurality of reference potential supplying means for providing a reference potential, and a plurality of reference potential supplying means for providing a reference potential, respectively, and each of the plurality of blocks is provided with an odd number of columns. A combination of the first or second bit line of the bit line pair and the first or second bit line of the bit line pair of the even column is different, and the reference potential of the reference potential supply means of the corresponding column is based on the combination. And a plurality of reference word lines to be applied to the bit lines.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. FIG. 1 shows a semiconductor memory device according to the first embodiment of the present invention. In this embodiment, the configuration of the dummy cell is different from that of the conventional one shown in FIG. The dummy word lines DWL _{0 to} DWL ₃ are decoded according to the position of the selected word line, and one of the four word lines is selected. Dummy cells are arranged on each dummy word line as shown in the figure,
Further, two dummy word lines DWL _{0 to} DWL ₃ are arranged on both sides of the crossing CP ₄ . In addition, each of the blocks a to d has row addresses RA _i and RA _j (i ≠
j), block a: RA _i = RA _j = 0 block b: RA _i = 0, RA _j = 1 block c: RA _i = 1 and RA _j = 0 block d: RA _i = RA _j = 1 Corresponding to the word lines WL ₀ , WL ₀ ′, W
L ₁ , WL ₁ ′, ... Are row addresses RA _k (k ≠
i, k ≠ j), WL ₀ , WL ₁ , WL ₂ , WL ₃ , ...: RA _k = 0 WL ₀ ′, WL ₁ ′, WL ₂ ′, WL ₃ ′, ...: RA
It is assumed that decoding is performed as in _k = 1.

In this embodiment, the dummy word lines DWL _{0 to} DWL ₃ are set according to the selected word line.
You can select as follows. If WL _{0 in} block a is selected: DWL ₀ WL ₀ ′ is selected: DWL ₁ If WL _{1 in} block b is selected: DWL ₂ WL ₁ ′ is selected: DWL ₃ If WL _{2 in} block c is selected: DWL ₁ WL ₂ ′ is selected: DWL ₀ If WL _{3 in} block d is selected: DWL ₃ WL ₃ ′ is selected: DWL ₂

These are row addresses RA _i and RA in the previous period.
_This means selecting the selected dummy word line for the values of _j and RA _k as follows.

[Table 1]

An example of realizing such an operation is shown in FIG. As a result, one of the dummy word line drive transistors T _{0 to} T ₃ is set to the “H” level by the decoding according to the above table, and the dummy word line rising signal φ _R
The corresponding dummy word line rises at the same time as the rising of, and the selected state is set.

As described above, according to this embodiment, one set of dummy cells and dummy word lines (for two dummy word lines), which is exactly the same as the conventional dummy cell system, crosses CP ₄
By additionally arranging with the bit line interposed, it is possible to easily realize the dummy cell method applicable to the bit line method including the intersection.

In the above description, the word lines WL ₀ ,
WL ₀ ′ is shown as a representative of the word lines in the block a, and this is exactly the same for the other word lines in the block a and the same for the other blocks. Further, the arrangement position of the dummy word line is not limited to the position of the above-mentioned embodiment, but may be on both sides of another intersection. Further, in the above-mentioned embodiment, the case where the present invention is applied to the conventional device shown in FIG. 7 is shown, but the present invention can be applied to other devices shown in FIGS. 6 and 8 as well.

FIG. 3 shows a semiconductor memory device according to the second embodiment of the present invention. In this case, the dummy word line DW
With respect to L ₂ and DWL ₃ , every two bit lines intersecting with each other are consecutive with respect to adjacent bit lines, and
One dummy cell is arranged per bit line pair. By changing the dummy cell arrangement for some dummy word lines in this way, the dummy cell system can be realized without any problem even if four dummy word lines DWL _{0 to} DWL ₃ are arranged on one side of the intersection. In this case, too,
The dummy word lines DWL _{0 to} DWL ₃ may be decoded by using exactly the same decoding as in FIG.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing dummy word line decoding according to the present invention.

FIG. 3 is a configuration diagram showing a semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a conventional semiconductor memory device.

FIG. 5 is a diagram for explaining a memory cell capacity of a conventional semiconductor memory device.

FIG. 6 is a configuration diagram of a conventional semiconductor memory device having a bit line pair intersection.

FIG. 7 is a configuration diagram of a conventional semiconductor memory device having a bit line pair intersection.

FIG. 8 is a configuration diagram of a conventional semiconductor memory device having a bit line pair intersection.

FIG. 9 is a configuration diagram when a dummy cell method is applied to a conventional semiconductor memory device having a bit line pair intersection.

[Explanation of symbols]

SA sense amplifier, CP ₁ , CP ₂ , CP ₃ intersection, CP ₄ bit line end intersection, a, b, c, d block, BL ₀ , ... Bit line, WL ₀ , ... Word line,
DWL ₀ , ... Dummy word line.

Claims (4)

[Claims] 1. A first bit line connected to half of a plurality of memory cells arranged in corresponding columns and a second bit line connected to the remaining half of the memory cells, respectively. A plurality of bit line pairs, a plurality of sense amplifiers arranged in a plurality of columns, each of which senses a potential difference between the first bit line and the second bit line of the bit line pair of the corresponding column, A plurality of first word lines connected to the memory cells connected to the first bit lines of the bit line pairs in the odd columns and the memory cells connected to the first bit lines of the bit line pairs in the even columns; A plurality of second words each connected to the memory cell connected to the first bit line of the bit line pair in the odd column and the memory cell connected to the second bit line of the bit line pair in the even column A second bit of each bit line pair in an odd column A plurality of third word lines connected to the memory cells connected to the lines and the memory cells connected to the first bit lines of the bit line pairs in the even columns, each of the second word lines of the bit line pairs in the odd columns. A plurality of fourth word lines connected to the memory cells connected to the bit lines and the memory cells connected to the second bit lines of the bit line pairs in the even columns, to the bit lines of each of the bit line pairs. A reference potential generating means for generating a reference potential for giving, a reference potential generating means for connecting the reference potential generating means to the first bit lines of the bit line pairs in the odd columns and the first bit lines of the bit line pairs in the even columns. A second reference word line for connecting the reference word line of 1 and the reference potential generating means to the first bit line of the bit line pair of the odd column and the second bit line of the bit line pair of the even column The third reference word line for connecting the second potential line of the odd-numbered bit line pair and the first bit line of the even-numbered bit line pair, and the reference potential generation means A fourth reference word line for connecting to the second bit line of the column bit line pair and the second bit line of the even column bit line pair, the selected word line being one of the first to fourth The semiconductor memory device is provided with a reference word line decoding means for selecting any one of the first to fourth reference word lines according to the above. 2. A plurality of memory cells arranged in a plurality of columns and a plurality of rows, a plurality of memory cells arranged in a plurality of columns, and half of the plurality of memory cells arranged in corresponding columns are connected. A plurality of bit line pairs each consisting of one bit line and a second bit line to which the remaining half of the bit lines are connected; arranged in a plurality of columns; A plurality of sense amplifiers for detecting a potential difference between the two bit lines, the sense amplifiers being arranged in a plurality of rows, each of which is arranged in a corresponding row and arranged in an odd-numbered column. A plurality of first word lines connected to a plurality of memory cells connected to a bit line and a plurality of memory cells connected to a first bit line of a bit line pair arranged in an even column, a plurality of rows Are arranged in the corresponding rows and in the odd columns. A plurality of memory cells connected to the first bit line of the provided bit line pair and a plurality of memory cells connected to the second bit line of the bit line pair arranged in the even column are connected. A plurality of second word lines, a plurality of memories arranged in a plurality of rows, each of which is arranged in a corresponding row and connected to a second bit line of a bit line pair arranged in an odd column A plurality of third word lines connected to the cells and a plurality of memory cells connected to the first bit lines of the bit line pairs arranged in even columns; arranged in a plurality of rows; A plurality of memory cells connected to the second bit line of the bit line pair arranged in the odd row and the odd bit column and the second bit line of the bit line pair arranged in the even column. A plurality of fourth word lines connected to a plurality of connected memory cells, a plurality of columns, A plurality of reference potential supply means arranged in four rows for giving a reference potential, and a bit line pair in which the reference potentials of the reference potential supply means arranged in corresponding rows and in odd columns are arranged in odd columns And the reference potential of the reference potential supply means arranged in the corresponding row and in the even numbered column is applied to the first bit line of the bit line pair disposed in the even numbered column. A first reference word line for applying the reference potential of the reference potential supply means arranged in the corresponding row and in the odd column to the first bit line of the bit line pair arranged in the odd column, The reference potential of the reference potential supply means arranged in the corresponding row and the even column is applied to the second bit line of the bit line pair arranged in the even column. And a second reference word line for applying the reference potential of the reference potential supply means arranged in the corresponding row and in the odd column to the second bit line of the bit line pair arranged in the odd column. A third reference word line for applying the reference potential of the reference potential supply means arranged in the corresponding row and the even column to the first bit line of the bit line pair arranged in the even column, The reference potentials of the reference potential supply means arranged in the same row and in the odd columns are applied to the second bit lines of the bit line pairs arranged in the odd columns, and are arranged in the corresponding rows and the even columns. A fourth reference word line for applying the reference potential of the reference potential supply means to the second bit line of the bit line pair arranged in the even columns. The semiconductor memory device, characterized in that. 3. A memory cell array having a plurality of memory cells arranged in a plurality of columns and a plurality of rows, and a plurality of memory cells arranged in a plurality of columns of the memory cell array and corresponding to each other. A plurality of bit line pairs consisting of a first bit line to which half of them are connected and a second bit line to which the remaining half of them are connected, are arranged in a plurality of rows of the memory cell array, and the respective rows correspond to each other. In a semiconductor memory device having a plurality of word lines connected to a plurality of memory cells arranged in, the memory cell array is divided into a plurality of blocks in a column direction, and the plurality of blocks are in blocks. Is connected to the memory cell connected to either the first bit line or the second bit line of the plurality of bit line pairs, and the word line of the even number row of The bit line pairs 1
Of the bit line and the second bit line connected to each other are different from each other, and the reference for reading out the memory cell potential is provided on each bit line pair. Reference potential generating means for generating a potential, and a plurality of reference potential generating means for connecting each of the plurality of bit line pairs to one of the first and second bit lines of the bit line pair. A plurality of reference word lines, which are different from each other in each of the plurality of bit line pairs, and which are different from each other in connection with either the first bit line or the second bit line of the bit line pair; Based on the information of which of the plurality of blocks the word line belongs to, and whether the line is an odd row or an even row. There, the semiconductor memory device is characterized in that a reference word line decode means for selecting one of the plurality of reference word lines. 4. A memory cell array having a plurality of memory cells arranged in a plurality of columns and a plurality of rows, divided into a plurality of blocks in a column direction, and arranged in a plurality of columns of the memory cell array, each corresponding. A plurality of bit lines paired with a first bit line to which half of the plurality of memory cells arranged in the column are connected and a second bit line to which the remaining half is connected, A plurality of word lines connected to a plurality of memory cells arranged in a plurality of rows, each of which is divided into blocks corresponding to the plurality of blocks; For each block, a first or second bit line of a bit line pair to which memory cells to which odd-numbered row word lines are connected is connected, and a bit line pair to which memory cells to which even-row word lines are connected are connected. First of Alternatively, a combination with a second bit line is different, and further, a plurality of reference potential supply means for providing a reference potential, which are arranged in a plurality of columns of the memory cell array corresponding to each of the plurality of blocks, and a plurality of the plurality of reference potential supply means. Of the odd-numbered column bit line pairs and the first or second bit line pair of the even-numbered column pairs are different from each other. , A plurality of reference word lines for applying the reference potentials of the reference potential supply means of the corresponding columns to the bit lines based on the combination, and a semiconductor memory device.