JPH08235137A - Multiprocessor system - Google Patents

Abstract

PURPOSE: To speed up synchronous communication control that is performed through a communication register by reducing buffering between processors accompanying reference to the communication register. CONSTITUTION: This multiprocessor system has (n) processors 100 which process data, a storage device 400 which stores data, and a communication register device 300 for communication synchronization among the processors. Those devices are mutually coupled together through a mutually coupling network 200. The communication register device 300 is further divided into (n) communication register modules which store the same contents. Each communication register module is occupied by one processor 101 one to one and referred to at the same time. When data is written in one communication register module, its contents are broadcast to other communication register modules.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous communication control mechanism, and more particularly to a synchronous communication control mechanism in a multiprocessor system.

[0002]

2. Description of the Related Art In a multiprocessor system,
A high-speed shared register called a communication register may be used to hold a shared variable for synchronous control, exclusive control, or communication control between processors.
This communication register is required to have a short access time or a high throughput as compared with a storage device. Each processor can speed up the process by communicating via this communication register. In the synchronous control, the exclusive control, or the communication control, it is difficult for the multiprocessor system to obtain a sufficient degree of parallelism, so that the higher the degree of parallelism, the greater the effect on the overall performance of these controls. Therefore, the communication register configuration has a great effect on improving the performance of the multiprocessor system.

Barrier synchronization will be described as an example of synchronization control. Barrier synchronization is a process in which each processor waits in this routine until all the processors execute the barrier synchronization routine. FIG. 9 shows the routine. However, as the initial value, the communication register of word # 0 stores the number of processors that perform barrier synchronization, the communication register of word # 1 has a non-zero value, and a scalar register.
It is assumed that 0 value is stored in S0 and S1.

The meaning of each instruction is as follows.

FDCR S0, CR # 0: The value of the # 0 word of the communication register is stored in the scalar register S0 and then the # 0 of the communication register
Decrement the word value by -1.

BL S0, loop1: The value of the scalar register S0 is 0
If it exceeds the value, it branches to loop1.

SCR S1, CR # 1: The value of the scalar register S1 is stored in the # 1 word of the communication register.

B loopend: Unconditionally jump to loopend.

LCR S2, CR # 1: The value of the # 1 word of the communication register is stored in the scalar register S2.

BNE S2, loop1: The value of scalar register S0 is 0
If it is not a value, branch to loop1.

When each processor enters the barrier routine,
First, the value of communication register word # 0 is saved in S0 and decremented. The # 0 word of the communication register contains the number of processors as an initial value, so if all the processors enter this routine, the value of the # 0 word of the communication register will be zero. Lo except for the processor that last entered this routine
jump to op1 and until the last processor enters the routine,
You'll be waiting in a loop here. Whether or not it is the last processor can be determined by looking at the value of the # 0 word of the communication register that the FDCR instruction has read, and if it is the last processor, write a zero value to the # 1 word of the communication register to make it the other processor. To notify.

[0012]

In the above-described conventional multiprocessor system, the number of requests that can access the communication register device is one at a time among the plurality of communication register access requests issued by the plurality of processors. Limited This can cause a large overhead in synchronization, exclusion, and communication control using the communication register.

In this case, the processors other than the last processor execute the FDCR instruction, and then the last processor becomes # 1.
The LCR instruction in loop1 will be repeatedly executed until the word value becomes zero. This repeated execution is called a spin lock. Since the spin lock is executed by all the processors that have entered the routine, the communication register access is concentrated and a large access conflict occurs. Due to this access conflict, the FDCR instruction access executed by the processor newly entering the barrier synchronization routine is
In the worst case, the spin-locked processors will be kept waiting for the processors already waiting for the barrier synchronization.

Referring to FIG. 10, when the above-mentioned barrier synchronization is performed by four processors, first, each processor sequentially decreases the # 0 word of the communication register, and then it is checked whether or not each processor has ended. To do. Therefore, in the case of using these four processors, it takes eight cycles to complete the synchronization. That is, N processors require (2 × N) cycles.

An object of the present invention is to solve the above-mentioned problems and to speed up synchronous communication control via a communication register.

Another object of the present invention is to reduce the buffering between processors due to the reference of the communication register.

[0017]

In order to solve the above-mentioned problems, a multiprocessor system according to the present invention comprises N (N is an integer) processors, a memory device, a communication register device, and these processors and memory devices. In a multiprocessor system including an interconnected network for interconnecting communication register devices, said communication register device comprises:
It includes N communication register modules, each of which is controlled such that each word stores the same content, and is referenced exclusively by one particular processor.

Further, in another multiprocessor system of the present invention, the mutual coupling network transfers a write request from the processor to all of the N communication register modules.

Further, in another multiprocessor system of the present invention, the communication register device further includes a network interface circuit, and the network interface circuit sends a write request from the processor to all of the N communication register modules. Forward.

Further, in another multiprocessor system of the present invention, the communication register device further includes a communication register network, and the communication register network is provided when a write request is issued from the processor to a communication register module. The write request is transferred to all communication register modules of.

Further, in another multiprocessor system of the present invention, each of the communication register modules is
Furthermore, when the request from the processor is divided into N sets of M words (M is an integer), a read access occurs in the communication register module that the processor owns, and If the request is a write, the request is broadcast to all communication register modules, write access occurs in all the communication register modules, and if the request from the processor is test and set, A test operation is performed on a communication register module including a set in which the module numbers assigned to the communication register module in ascending order from 1 and the set numbers assigned to the set in ascending order from 1 match, and The result of the test is "Lock acquisition failure" If the test results are returned to the processor, the lock write access for all communication registers module "lock ensuring successful" if the same address is generated.

Further, in another multiprocessor system of the present invention, the communication register module has a plurality of ports that can be accessed at the same time, and the read access from the processor and the write access via the communication register network are simultaneously performed. Allow access.

[0023]

An embodiment of the present invention will now be described in detail with reference to the drawings.

Referring to FIG. 1, a multiprocessor system according to an embodiment of the present invention includes n processors 100 for processing data and a storage device 400 for storing the data.
And a communication register device 300 for communication synchronization between processors, which are connected to each other by the interconnection network 200.
Are connected to each other via.

The processor 100 has one access port each for the interconnection network. The storage device 400 is assumed to have an access port of 1 port as a whole.

Referring to FIG. 2, the communication register device 30.
0 is further divided into n communication register modules 320. Each of these communication register modules 320 is provided with an identifier called a module number that can uniquely identify each other. In the figure, change this module number to #
Expressed as 1 mag. The communication register modules 320 each have one access port for the interconnection network.

Referring to FIG. 1, the interconnection network 200 has a total of n ports for each processor, a total of n ports for each communication register device, and one for main memory.
Have a port access port. An access path is set up between the access ports, and an access request flows on this access path. Further, as another configuration, a configuration having multiple access ports and access paths for the purpose of improving access throughput can be considered. For example, there is a configuration in which n access paths are set up between the main storage device and the mutual connection network.

When the processor 100 accesses the storage device 400 or the communication register device 300, the processor 100 generates a request packet and sends it to the interconnection network 200 through the access path. The interconnection network 200 arbitrates the competition between a plurality of request packets sent from a plurality of processors 100, routes the request packets to the storage device 400 or the communication register device 300, which is the destination of each request packet, and provides an access path to each. To send the request packet. The request packet arriving at the storage device 400 or the communication register device 300 is read-accessed or write-accessed in each device. Further, in the case of read access, read data is returned to the processor via the mutual coupling network again.

Referring to FIG. 4, the format of the request packet flowing through the interconnection network 200 is as follows.
Whether the access destination is the storage device 400 or the communication register device 3
Access type field 801 indicating whether it is 00, a code field 802 indicating whether the access is a load or a store, an address field 803 indicating an address in the storage device 400 or an address in the communication register 300, and a write data Data field 804
It consists of and. In the case of load access, the read data is held in the data field and returned to the processor 100 via the interconnection network 200.

Various network configurations can be applied to the interconnection network 200, but a request from the processor 100 to the communication register device 300 and another processor 100 to another communication register device 300.
It is desirable to have a network configuration in which blocking does not occur when requests to the access port arrive at the access port at the same time. For example, a non-blocking type crossbar switch or the like is one of the desirable configurations.

Referring to FIG. 3, the communication register device 30.
Each communication register module 320 in 0 has a communication register memory 301 composed of a plurality of words, a write register 302 for supplying write data to the communication register memory 301, and an address register for supplying an address to the communication register memory 301. 303, a read register 304 that holds the data read from the communication register memory 301, a write instruction register 305 that instructs the communication register memory 301 to write, and a read instruction register 3 that instructs the communication register memory 301 to read.
06, a request packet control circuit 311 for decomposing request packets from the mutual connection network 200 and distributing them to each unit, a communication register control circuit 310 for controlling access to the communication register memory 301, and a reply to the mutual connection network 200. And a reply packet control circuit 312 for generating a packet.

Address numbers are continuously assigned to the communication register memory 301 from address 0. Processor 100
In the communication register access from, the word position of the communication register to be accessed is determined by designating this communication register address.

The contents of the data stored in each word of the communication register memory 301 can be freely determined. If only used for synchronization, some or all of the bits of the word may be used as a synchronization flag. Alternatively, only the most significant bit may be used as a synchronization flag and the remaining bits may be used for storing data to be transferred between processors.

When writing to the communication register memory 301, the write instruction register 305 is set to one value and the address of the word to be written is set to the address register 3.
03, write data to be written to the write register 30
Set to 2. At the next timing, the write register 30
The value of 2 is written in the word specified by the address register 303 in the communication register memory 301.

When reading from the communication register memory 301, the read instruction register 306 is set to one value, and the address of the word to be read is set in the address register 3.
Set to 03. At the next timing, data is read from the word designated by the address register 303 in the communication register memory 301 and held in the read register 304.

These registers around the communication register memory 301 are controlled by the communication register control circuit 310.

The request packet control circuit 311 processes a request packet arriving from the mutual coupling network 200. Interconnection network 200
When the request packet is received, the request code field 802 is decoded and it is also determined whether it is a load access or a store access. The decoding result is sent to the communication register control circuit 310. The reply packet control circuit 312 stores the data held in the read register in the data field 804 of the packet and configures it as a reply packet for the mutual coupling network 200.

Next, the processing in the communication register module 320 in the communication register access will be described.

In the case of store access, the data in the data field 804 is written in the word of the address indicated by the address field 803 in the communication register memory 301. That is, at the write timing, the communication register address in the address field 803 is put into the address register 303. Also, the write data in the data field 804 is put into the write register 302. At the same time, by setting the write instruction register 305 to 1 value, the write access is completed at the next timing.

In the case of load access, the communication register memory 301 reads data from the word of the address indicated by the address field 803. That is, at the read timing, the communication register address in the address field 803 is put into the address register 303, and at the same time, the read instruction register 306 is set to 1 value. The read data is held in the read register 304 at the next timing. The data held by the read register 304 is stored in the data field 804 of the packet to form a reply packet for the interconnection network. This reply packet is sent to the interconnection network 200.

Referring to FIG. 2, the communication register device 30.
Each communication register module 320 in 0 has n
It is divided into equal parts. Each of these equally divided registers is called a set. This set consists of m words each. That is, each communication register module 320
Has n sets of m words each. A set number is given to this set as a number that can be uniquely identified from each other. In the figure, this set number is represented as% 1 and the like.

Here, each communication register module 320
In the above, a set having the same set number as the module number is called an actual set, and a communication register in the actual set is called an actual communication register. The other (n-1) sets are called copy sets, and the communication registers in the set are called communication register copies. The sets with the same set number are
It is controlled to store the same contents. For example, in the communication register module # 1, the set of% 1 is a real set and the other sets are copy sets.

When data is written to a certain communication register module 320, data of the same content is written to the corresponding word in another communication register module in that cycle. In this embodiment, the interconnection network 200 controls the writing. In addition, in each communication register module 320, when the decrement by broadcast and the check process conflict with each other, the mutual connection network 200 controls the broadcast to give priority to the broadcast.

Referring to FIG. 5, when four processors are synchronized in this embodiment, decrement occurs in the communication register module # 1 in the first cycle,
As a result, writing by broadcasting occurs in another communication register module. Further, in the second cycle, decrement occurs in the communication register module # 2, which causes writing by broadcasting to other communication register modules. After that, in the third cycle, communication register module # 3,
In the fourth cycle, the same processing is performed on the communication register module # 4. Then, in the fifth cycle, a check is performed in each communication register module, and as a result, it is confirmed that all the processors are synchronized. That is, the check phase, which requires the number of processors in the conventional technique, is completed in one cycle in this embodiment.

With the above configuration, in this embodiment, the communication register access is processed as follows. In the case of read access, read access is performed to the communication register module having the same module number as the processor that issued the access. At this time, each communication register is accessed regardless of whether it is a real set or a copy set.

In the case of write access, after being broadcast by the interconnection network 200, it is written in each communication register module 320 having the same address.

In the case of the test & set instruction, the test process is performed on the communication register module having the actual communication register corresponding to the communication register address to be tested. If the lock is unsuccessful as a result of the test, the test result is returned to the processor. If the lock is successfully secured, the write operation of the lock bit is performed on the actual communication register, and for all communication register copies of the same address,
The lock bit write processing is performed via the mutual connection network 200.

As described above, according to the first embodiment of the present invention, the communication register module 32 dedicated to each processor is provided.
By providing 0, and when a write occurs in them, the write is broadcast via the mutual coupling network 200, so that the check operation can be performed simultaneously from each processor 100, and the time required for this check operation is shortened. can do.

Next, a second embodiment of the present invention will be described. The second embodiment has the same configuration as that of the first embodiment except that the internal configuration of the communication register device 300 is different as follows.

Referring to FIG. 6, the communication register device 300 in the second embodiment of the present invention is similar to the first embodiment in that it has n communication register modules 320. It differs from the first embodiment in that a network interface circuit 330 is provided between the communication register module 320 and the interconnection network 200.

Network interface circuit 330
Has an interface mechanism between the interconnection network 200 and each communication register module 320.
At the time of read access, the request sent from the mutual coupling network 200 is passed to the same output port as the input port. At the time of write access, the request is broadcast to all communication register modules 320. At this time, the request format is sent to each communication register module 320 without being changed.
At the time of test & set access, the request is routed to the communication register module in which the actual communication register corresponding to the communication register address to be tested exists. In addition, as a result of test & set access,
If the lock is successfully secured, the result is broadcast to all communication register modules 320.

Each communication register module 320 accesses the request received from the network interface circuit 330 to the processing contents shown in the request code field 802 and the word of the communication register shown in the address field 803.

In the second embodiment, in each communication register module 320, when the decrement by broadcast and the check process conflict with each other, the network interface circuit 330 controls to give priority to the broadcast.

With the above arrangement, in the second embodiment, the communication register access is processed as follows. In the case of read access, read access is performed to the communication register module having the same module number as the processor that issued the access. At this time, each communication register is accessed regardless of whether it is a real set or a copy set.

In the case of a write access, after being broadcast by the network interface circuit 330, it is written in each communication register module 320 of the same address.

In the case of the test & set instruction, the test process is performed on the communication register module having the actual communication register corresponding to the communication register address to be tested. If the lock is unsuccessful as a result of the test, the test result is returned to the processor. If the lock is successfully secured, the write operation of the lock bit is performed on the actual communication register, and for all communication register copies of the same address,
The lock bit write processing is performed via the network interface circuit 330.

As described above, according to the second embodiment of the present invention, the communication register module 32 dedicated to each processor is used.
0 is provided, and when a write occurs in them, the write is broadcast via the network interface circuit 330, so that each processor 10
The check operation can be performed simultaneously from 0, and the time required for this check operation can be shortened.

Next, a third embodiment of the present invention will be described. The third embodiment has the same configuration as the other embodiments described above, except that the internal configuration of the communication register device 300 is different as follows.

Referring to FIG. 7, the communication register device 300 according to the third embodiment of the present invention is similar to the other embodiments in that it has n communication register modules 320. It differs from the other embodiments in having a communication register network 340 that couples the register modules 320 together.

In this third embodiment, the communication register modules 320 each have two ports, and can simultaneously allow up to two accesses.

When data is written to a certain communication register module 320, data of the same content is written to the corresponding word in another communication register module in that cycle. In this embodiment, the communication register network 340 controls the writing. In each communication register module 320,
If there is a conflict between the decrement by broadcast and the check processing, the communication register network 340
Controls that the broadcast has priority.

Referring to FIG. 8, in the third embodiment of the present invention, one decrement and one or more checks are permitted in the same cycle. That is, the communication register module # that has been decremented in the first cycle
1 is accessed for check processing in the second and subsequent cycles. When all the communication register modules are decremented after that, all the processors have completed the synchronization. Therefore, in the fifth cycle, all the communication register modules are checked at the same time, and as a result, it can be confirmed that all the processors have completed the synchronization.

With the above configuration, in the third embodiment, the communication register access is processed as follows. In the case of read access, read access is performed to the communication register module having the same module number as the processor that issued the access. At this time, each communication register is accessed regardless of whether it is a real set or a copy set.

In the case of write access, after being broadcast by the communication register network 340, it is written to each communication register module 320 having the same address.

In the case of the test & set instruction, the test process is performed on the communication register module having the actual communication register corresponding to the communication register address to be tested. If the lock is unsuccessful as a result of the test, the test result is returned to the processor. If the lock is successfully secured, the write operation of the lock bit is performed on the actual communication register, and for all communication register copies of the same address,
The lock bit write processing is performed via the communication register network 340.

As described above, according to the third embodiment of the present invention, the communication register module 32 dedicated to each processor is used.
By providing 0, and when writing to them occurs, the writing is broadcast via the communication register network 340, so that each processor 100 can simultaneously perform the checking operation, and the time required for this checking operation is shortened. can do.

[0067]

As described above, according to the present invention, it is possible to reduce the buffering between processors due to the reference of the communication register. Further, this makes it possible to speed up the synchronous control, the exclusive control, or the communication control via the communication register.

[Brief description of drawings]

FIG. 1 is a diagram showing an overall configuration of a multiprocessor system of the present invention.

FIG. 2 is a diagram showing a configuration of a communication register device according to an embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a communication register module in the communication register device in the embodiment of the present invention.

FIG. 4 is a diagram showing a format of a request passing through an interconnection network according to an embodiment of the present invention.

FIG. 5 is a time chart in the first and second embodiments of the present invention.

FIG. 6 is a diagram showing a configuration of a communication register device according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a communication register device according to a third embodiment of the present invention.

FIG. 8 is a time chart in the third embodiment of the present invention.

FIG. 9 is an example of a program that realizes barrier synchronization.

FIG. 10 is a time chart of a conventional multiprocessor system.

[Explanation of symbols]

 100 processor 200 mutual coupling network 300 communication register device 301 communication register memory 302 write register 303 address register 304 read register 305 write instruction register 306 read instruction register 310 communication register control circuit 311 request packet control circuit 312 reply packet control circuit 320 communication register module 330 network interface circuit 340 communication register network 400 storage device

Claims (6)

[Claims] 1. A multiprocessor system including N (N is an integer) processors, a storage device, a communication register device, and an interconnection network interconnecting the processors, the storage device, and the communication register device with each other. The communication register device includes N communication register modules, each of the communication register modules is controlled so that each word stores the same contents, and is exclusively referred to by one specific processor. A multiprocessor system characterized by. 2. The multiprocessor system according to claim 1, wherein the interconnection network transfers a write request from the processor to all of the N communication register modules. 3. The communication register device further includes a network interface circuit, and the network interface circuit transfers a write request from the processor to all of the N communication register modules. The described multiprocessor system. 4. The communication register device further includes a communication register network, and when the communication register network issues a write request from a processor to a communication register module, the communication register network sends a write request to all other communication register modules. The multiprocessor system according to claim 1, wherein the multiprocessor system transfers. 5. Each of the communication register modules comprises:
Further, when the request from the processor is a read, the read access is generated in the communication register module that the processor exclusively uses, and the read access is generated by dividing the set into N sets of M words (M is an integer). If the request is a write, the request is broadcast to all the communication register modules, write access occurs in all the communication register modules, and if the request from the processor is test and set, Module numbers assigned to the communication register module in ascending order from 1 and 1 in the set
The test operation is performed on the communication register module including the set with the set number added in ascending order from the test result. If the test result is "lock acquisition failure", the test result is returned to the processor. 2. The multiprocessor system according to claim 1, wherein a write access to the lock occurs in all the communication register modules having the same address if the "lock is successfully secured". 6. The communication register module has a plurality of ports that can be accessed at the same time, and allows simultaneous read access from a processor and write access via a communication register network. Item 4. The multiprocessor system according to Item 4.