JPH08233602A - Absolute encoder - Google Patents

Abstract

PURPOSE: To provide an absolute encoder securing high speed follow-up of data display by combining a capacitance type detector with a photoelectric detector so as to be able to obtain absolute data of high resolution, in a wide length measuring range with a small number of tracks, and moreover having preset error compensating function. CONSTITUTION: Capacitance type absolute data CAPDATA indicating upper digits, and photoelectric absolute data OPDATA indicating lower digits are synthesized in a shift register 110 and outputted. The data CAPDATA is preset to a first counter 90 and corrected therein by a carry signal from the data OPDATA, but when the correction becomes large, the data CAPDATA is preset again by the instruction of a comparing circuit 100. A second counter 140 counts the moving quantity of a scale at the preset time of the first counter 90 and compensates a preset error.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an absolute encoder capable of obtaining high-resolution absolute position data over a wide measuring range by synthesizing detection values of a capacitance type encoder and a photoelectric type encoder.

[0002]

2. Description of the Related Art As a method for recognizing the position of a tool of a machine tool or a mechanically movable portion of a table, there are an incremental method and an absolute method. The incremental method is provided with a pulse generator that generates one pulse each time a motor or mechanically movable part moves or rotates by a predetermined amount, and counts the pulses obtained from this pulse generator to obtain the current position. The absolute method is a method of detecting and displaying the position of the mechanical movable portion by a unique code using an absolute code pattern.

In the incremental method, the current position data of the mechanically movable portion is lost when the power is turned off. For this reason, it is necessary to return the mechanical movable part to the origin after turning on the power, clear the contents of the current position counter to zero, match the current position of the mechanical movable part with the contents of the current position counter, and then perform position control. Is. On the other hand, in the absolute method, the current position of the mechanically movable part does not disappear even when the power is turned off, and the home-return operation after turning on the power is unnecessary.

However, in the absolute system,
If, for example, a 24-bit code pattern is used as an encoder, not only the scale for forming this code pattern becomes large, but also the number of detectors for reading this code pattern and the number of signal lines become enormous. In order to solve such a problem, the applicant has already made it possible to obtain absolute data over a wide measuring range with a small number of tracks without using a large number of code patterns such as an optical encoder. A type encoder is proposed (for example, Japanese Patent Application No. 2-132434, Japanese Patent Application No. 2-169454, etc.).

However, in the absolute type electrostatic capacity encoder, it takes a considerable amount of time to update the data, and the data display may not follow the high-speed movement of the scale. In addition, there was a limit to the measuring range and the dynamic range in order to obtain absolute data only with the capacitance encoder. On the other hand, it is conceivable to provide different detectors on the same shaft as in an absolute rotary encoder that combines a resolver and a photoelectric detector. However, if different detectors are attached and the respective detection data are output independently, the communication partner side has to combine the data, etc., which increases the burden on the communication partner side.

On the other hand, as a method of combining absolute data and incremental data, absolute position data obtained by a photoelectric absolute code pattern is preset, incremental pulses obtained by the photoelectric incremental code pattern are counted, and the absolute data is output. A system has been proposed (JP-A-1-116409).

[0007]

However, in the method in which both the absolute encoder and the incremental encoder are photoelectric type, a large number of code patterns are formed in the scale width direction as in the case where the photoelectric absolute encoder is constituted independently. There is a problem that the scale must be increased.

The present invention has been made to solve the above-mentioned problems, and combines an electrostatic capacity type detector and a photoelectric type detector to ensure high-speed follow-up of data display, high resolution and wide range with a small number of tracks. It is an object of the present invention to provide an absolute encoder capable of obtaining absolute data in the length measuring range and further having a preset error compensation function.

[0009]

In the absolute encoder according to the present invention, firstly, a scale on which a capacitance type absolute code pattern and a photoelectric type incremental code pattern are formed, and the capacitance type absolute code pattern are provided. Capacitive detection means for reading to obtain absolute position data, photoelectric detection means for reading the photoelectric incremental code pattern to obtain relative displacement amount data of the scale, and absolute position from the capacitance detection means Data is preset, first count means for correcting and outputting the preset absolute position data based on relative displacement amount data output from the photoelectric detection means, and absolute position output by the first count means Data and absolute position data output by the capacitance type detection means, In comparison, when the difference exceeds a predetermined value, the first counting means re-presets the absolute position data from the electrostatic capacitance type detection means again, and the first counting means is preset. In the second counting means for counting the relative movement amount of the scale and compensating the preset value of the first counting means based on the count value.

Secondly, the absolute encoder according to the present invention comprises a capacitance type absolute code pattern, a scale on which a high resolution photoelectric incremental code pattern having a shorter spatial wavelength is formed, and the capacitance type absolute code. Capacitive detection means for reading the code pattern to obtain upper digit data of absolute position, photoelectric detection means for reading the photoelectric incremental code pattern to obtain lower digit data of absolute position, and lower digit data Carry generating means for generating a carry signal to the least significant digit of the upper digit data based on the above, and upper digit data from the electrostatic capacitance type detecting means is preset, and the upper digit data is generated by the carry signal. A first counting means for correcting and outputting and a higher order output by the first counting means The data is compared with the upper digit data output by the capacitance type detection means, and when the difference exceeds a predetermined value, the first digit counting means outputs the upper digit data from the capacitance type detection means. Of the first counting means, an output means for synthesizing and outputting the upper digit data output from the first counting means and the lower digit data obtained from the photoelectric detection means, The present invention is characterized by further comprising second counting means for counting the relative movement amount of the scale at the time of presetting and compensating the preset value of the first counting means based on the count value.

Thirdly, the absolute encoder according to the present invention comprises a capacitance type absolute code pattern and a scale on which a photoelectric type absolute code pattern having a shorter spatial wavelength and a higher resolution is formed, and the capacitance type absolute code. Read the code pattern,
Capacitive detection means for obtaining upper digit data of absolute position,
Photoelectric detection means for reading the photoelectric absolute code pattern to obtain lower digit data of absolute position,
Carry generation means for generating a carry signal to the least significant digit in the upper digit data based on the most significant digit in the lower digit data, and upper digit data from the capacitance type detection means. First counting means which is preset and corrects and outputs the upper digit data by the carry signal; upper digit data output by the first counting means and upper digit output by the capacitance detecting means Compare with the data,
Comparing means for presetting the upper digit data from the capacitance type detecting means to the first counting means again when the difference exceeds a predetermined value, and upper digit data output from the first counting means. And an output means for synthesizing and outputting lower digit data obtained from the photoelectric detection means, and a relative movement amount of the scale at the time of presetting of the first counting means, and counting the relative movement amount based on the count value. And a second counting means for compensating the preset value of the first counting means.

In the present invention, preferably, the output of the electrostatic capacitance type detection means is provided with a register for temporarily accumulating the obtained upper digit data, and the second counting means is the first counting means. It is characterized in that it is provided with an addition means which is provided side by side and which adds and subtracts the count value of the second counting means to the output data of the register and outputs it as a compensated preset value to the first counting means. .

In the present invention, further, a register for temporarily accumulating the obtained upper digit data is provided at the output of the capacitance type detecting means, and the second counting means is provided with the first counting means and the above-mentioned first counting means. The second counting means is interposed between the carry generating means, and the second counting means is controlled by the first counting means to count the relative movement amount of the scale at the preset time to preset the preset value of the first counting means. Is compensated.

[0014]

In the present invention, the upper digit of the absolute position data is made by the electrostatic capacitance type detector, and the lower digit is made by the photoelectric type detector to synthesize them. If the absolute position data is obtained only by the capacitance type detector, the followability of the lower digit of the display data cannot be guaranteed especially when the scale moves at a high speed, but in the present invention, the lower digit data is excellent in high speed performance. Since it is obtained by the photoelectric detector, it is excellent in high-speed followability as a whole. Since the upper digit of the display data changes more slowly when moving the scale than the lower digit, a capacitance type detector can be used in this part, which ensures a wide measuring range with a small number of tracks. be able to.

Further, in the present invention, an up-down counter with a preset input is provided as the first counting means, and the preset absolute position data is updated by the output of the photoelectric detector as the scale moves. . At this time, if the photoelectric type detector is of the incremental type, the output originally has no absolute position information, so the data corrected by that output will deviate from the correct absolute position data by the capacitance type detector. When the level is exceeded, a process of presetting correct upper digit data which is the output from the capacitance type detector and initializing the data is performed again. This makes it possible to obtain absolute position data with high resolution and a wide measurement range without error.

Further, the presetting of the first counting means is not always performed with the scale stopped. If the first counting means is preset by the output of the capacitance type detector as it is, if the scale is moving, the absolute position data which is initialized by the preset instruction is given. Due to the delay in the output signal processing of the capacitive detector, the data will be displaced from the actual position. Therefore, in the present invention, the second counting means is provided in order to compensate for the preset error caused by the scale movement at the preset time. By this second counting means,
It is possible to detect the amount of scale movement from the start to the end of presetting, correct the delayed absolute position data obtained from the capacitance type detector, and give correct preset data to the first counting means. As described above, the preset error is compensated.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. 1 shows the overall configuration of an absolute encoder according to an embodiment of the present invention, and FIG. 2 shows the scale and detector configuration used in this embodiment. The scale 10 includes electrostatic capacity type absolute code patterns 11 to 13, 15 and 16 having a low resolution and a long spatial wavelength, and a photoelectric type incremental code pattern 14 having a high resolution and a short wavelength.
Are formed in the position detection direction.

Specifically, the capacitance type absolute code pattern of the scale 10 is, as shown in enlarged form in FIG.
1, a second track 12 for measuring intermediate precision, and a third track 13 for measuring fine precision. The third track 13 is further finely divided inside thereof to form a photoelectric incremental code pattern 14 for ultrafine precision measurement. The capacitance type code patterns 15 and 16 are transmission electrodes for the second track 12 and the third track 13, respectively.

As described above, in this embodiment, the capacitance-type third track and the photoelectric-type fourth track physically share the same track, and as a result, the width of the scale 10 is reduced as a whole. be able to. However, it is also possible to independently form the electrostatic capacitance type third track and the photoelectric type third track.

In order to read the above-mentioned electrostatic absolute code pattern, a capacitance type detector 20 and a detection circuit 30 are provided, and the output of the position data for three tracks is subjected to synthesis processing to obtain the absolute position. A register 40 for holding the capacitance type absolute signal CAPDATA (for example, 8-bit data) which is upper digit data is provided.

Similarly, in order to read the photoelectric incremental code pattern, a photoelectric detector 50 and a photoelectric detection circuit 60 for processing the output of the photoelectric detector 50 to generate a photoelectric incremental signal are provided. An interpolating circuit 70 for interpolating the incremental signal to obtain a photoelectric absolute signal OPDATA is provided. Photoelectric absolute signal OP obtained from the interpolation circuit 70
DATA (for example, 4-bit data) does not include absolute position information itself, but is used as lower digit data of absolute position to be combined with absolute position information of higher digit obtained from the capacitance type detector 20 as described later. To be

The capacitance type absolute signal CAPDATA stored in the register 40 is fetched as upper digit data of absolute position into the first counter 90 which is an up / down counter with preset input at a predetermined timing through the adder 150. Be done. The high-order digit data of the absolute position fetched by the first counter 90 and the interpolation circuit 70
The lower digit data of the photoelectric absolute signal OPDATA obtained from the above is combined by the parallel input and serial output shift register 110, and is output to the outside as a serial signal indicating the final absolute position information.

The photoelectric absolute signal OPDATA obtained from the interpolation circuit 70 is input to the carry generator 80 to generate a carry signal. Then, this carry signal is supplied to the first counter 90, and the lower digit of the preset upper digit data is corrected.

Since the photoelectric absolute signal OPDATA originally has no absolute position information, when the preset data of the first counter 90 is corrected based on this, the deviation from the correct absolute position may be large. Therefore, when the deviation of the absolute position data output from the first counter 90 from the correct absolute position becomes larger than a certain amount, the capacitance type absolute signal CAPD is re-established.
It is necessary to preset the correct absolute position information by ATA. Therefore, the capacitance type absolute signal CAPDATA stored in the register 40,
To detect the difference between the output signals corrected based on the photoelectric absolute signal of the first counter 90, generate an NG signal when the difference is a certain value or more, and reset the first counter 90 again. The comparison circuit 100 of FIG.

The RS flip-flop 120 is provided to temporarily store the NG signal from the comparison circuit 100 as external transmission data. This flip-flop 1
The NG signal fetched by 20 is transferred to the shift register 110.
Is taken in and is transmitted to the outside as a serial signal together with the measured position data. The output of the interpolation circuit 70 is, for example, among the 4-bit data b3 to b0,
Two-phase square wave signals A0, B0 by 2 bits b0, b1
An EOR gate 130 for generating

Further, in this embodiment, the scale 20 is preset when the first counter 90 is preset (initialized).
In order to compensate for the error in the preset data of the first counter 90 when the second counter 140 is moving, the second counter 140 is provided side by side with the first counter 90 with a common input. The second counter 140 is zero-cleared at the rising edge of the NG signal from the comparison circuit 100 and counts up or down by the output from the carry generator 80 to move the scale during the preset operation of the first counter 90. It is to detect the quantity. Then, the capacitance type absolute signal CAPDATA which is the output of the register 40
Is added and subtracted by the adder 150 according to the scale moving direction, and the count value of the second counter 140 is given to the first counter 90 as preset data.

Further, the specific configuration and operation of each unit will be described.
As shown in FIG. 2, the capacitance type detector 20 includes a transmission electrode (driving electrode) 24 to which, for example, an 8-phase AC signal is sequentially applied to a pickup 22 that faces the scale 10 and relatively moves in the position detection direction. The receiving electrode 25 facing the transfer electrode 15 for the first track 11 and the receiving electrode 26 facing the transfer electrode 16 for the second track 12 are formed. To receive the signal from the third track 13, two receiving electrodes 25, 26 are used simultaneously.

The detection principle of the capacitance type detector 20 is shown in FIG.
And FIG. 5 will be described. FIG. 4 shows an electrode pattern for one track (third track 13 in the figure) in order to simplify the description. A glass plate or an epoxy plate is used for the scale 10 and the pickup 22, and a conductive film is formed on this and patterned to form an electrode pattern.

The voltage applied to the transmission electrode 24 of the pickup 22 is transmitted to the track electrode 13 on the scale 10 by capacitive coupling. Track electrode 13 and transmission electrode 1
5, the transmission electrode 15 and the reception electrode 25 on the pickup 22 are capacitively coupled. As a result, the receiving electrode 25 receives a signal according to the magnitude of capacitive coupling. The electrode pitch of the tracks 13 on the scale 10 and the pitch of the transmission electrodes 15 are different, and therefore the inclination of the wiring interconnecting them is different depending on the position.

The transmitting electrode 24 is composed of, for example, a group of eight electrodes commonly connected to each other, and the electrical connection between the electrode elements can be freely selected on the circuit board.
The pitch of the reception electrodes 25 is set to a length corresponding to eight transmission electrodes 24, and the length of the reception electrodes 25 in the detection direction is set to a length corresponding to a half wavelength (four transmission electrodes) of the transmission electrodes 24. ing.

Now, the relative positional relationship between the pickup 22 and the scale 10 is fixed, and the interconnections of the transmission electrodes 24 are
1st to 4th, 2nd to 5th, 3rd to 6th, ...
8 types are changed in sequence as shown. When the capacitance between the transmission electrode 24 and the reception electrode 25 is measured in each case, the capacitance is equivalent to each phase point which is out of phase by 45 ° on one cycle of the sine wave. On the contrary, when the relative position between the pickup 22 and the scale 10 is moved by specifying the mutual connection relationship of the transmission electrodes 24, the pickup signal 22 is picked up on the same sine wave.
It moves according to the amount of relative movement with the scale 10. The movement direction is determined by changing the combination of the transmitting electrodes 24 and confirming the direction of phase change.

By changing the interconnection of the transmitting electrodes 24 as described above, the sin wave and cos as shown in FIG.
Waves capacity waveform is obtained by capacitive detection circuit 30, tan ^- 1 by performing (sinX / cosX) becomes operational, it is possible to obtain the absolute position X. The detailed configuration and operation of the capacitance type absolute position measurement described above are described in Japanese Patent Application No. 2-132 filed by the applicant earlier.
434 and Japanese Patent Application No. 2-169654.

According to the above principle, the electrostatic capacitance type detection circuit 30 obtains position data signals of three modes of coarse, intermediate and fine by three tracks, and the register 40 has a function of combining and outputting these data. Have. That is, the data for three tracks obtained from the capacitance type detection circuit 30 is
As shown in FIG. 6, the margin bit portions overlap each other. This is to avoid that the lower track cannot be accurately specified due to the error of each track or the quantization error. The register 40 fetches the data of each track in a time division manner, confirms that the difference between the overlapping bit parts of the data is within a predetermined range, synthesizes and outputs. If the data of the overlapping bit portion is different, the data of the lower track is corrected, for example. When the data in the overlapping bit portion is greatly different, it can be interpreted that an abnormality has occurred and an error signal can be output.

As shown in detail in FIG. 7, the photoelectric detector 50 has a slit plate 52 that moves integrally with the pickup 22 of the electrostatic capacitance detector 20, and an opening 22A formed in the central portion of the pickup 22. The light emitting diode 5 close to a point light source that radiates diffused light to the fourth track 14 (common to the third track 13) on the scale 10 via (see FIG. 2).
4 and four photodiodes 56 for detecting the light reflected by the third track 14 and modulated by the index scale 53 on the slit plate 52.

The photoelectric detection circuit 60 is a photoelectric detector 50.
By processing the output signals obtained by
Generates two-phase sinusoidal signals that are offset. The specific configuration and operation of the photoelectric detection circuit 60 is described in Japanese Patent Laid-Open No. 2-18741.
3 etc. As described above, in this embodiment,
1 light source 4 light receiving elements are used to obtain sinusoidal wave signals having different phases, and a stable sinusoidal wave output signal can be obtained excluding the influence of gap fluctuation between slit plate 52 and scale 10 and temperature fluctuation. However, in principle, a similar two-phase sine wave signal can be obtained with two light receiving elements.

The interpolation circuit 70 generates an incremental signal by a binary code used as a photoelectric absolute signal OPDATA which becomes lower absolute position data from the two-phase AC signal obtained from the photoelectric detection circuit 60. In the embodiment, it is configured as shown in FIG. That is, the preamplifiers 70A and 70B to which the two-phase AC signals A and B are input, the inverting amplifier 71 that inverts the A-phase input, and the resistor chain 72 whose outputs are supplied to a predetermined connection point as shown in the figure. Is provided. And comparators 74A and 74B for detecting the respective zero-cross points of the adjacent nodes of the resistance chain 72,
An analog switch group 73 that selects two adjacent nodes is provided.

Flip-flops 75A to 75C are provided to generate counting pulses and pulses indicating the counting direction based on the outputs of the comparators 74A and 74B.
Based on the outputs of these flip-flops 75A to 75C, the photoelectric absolute signal b which is binary data is output.
A controller 76 is provided to generate the signals 3 to b0 and the signal for feedback controlling the analog switch group 73. The feedback control system includes an up / down counter 77 that counts the output of the controller 76, a decoder 78 that decodes the count value of the counter 77, and a latch 79 that holds the output of the decoder 78 and controls the analog switch group 73. ing.

The detailed structure and operation of the interpolation circuit 70 of this embodiment are shown in Japanese Patent Laid-Open No. 1-212314. By the interpolation circuit 70, for example, as shown in FIG. 9, the BIN code photoelectric absolute signals b3 to b0 are obtained based on the two-phase sine wave signals obtained from the photoelectric detection circuit 60.

The carry generator 80, to which the photoelectric absolute signals b3 to b0 are supplied, has a combination of the delay element 86 and the gate circuit as shown in FIG.
A rising edge detection circuit 82 for detecting the edge of No. 3 and a falling edge detection circuit 84, and a count direction determination signal UP based on the edge data detected by these R
An -S flip-flop 88 and a gate circuit for outputting the count pulse CP based on the edge data and the lower bit data b0 to b2 are provided. FIG. 11 shows an operation timing chart of the carry generator 80.

The counting pulse generated by the carry generator 80 is input to the first counter 90 to scale the lower digit in the capacitance type absolute signal which is the upper digit data of the preset absolute position. Correct according to the moving direction. A comparison circuit 100 for comparing the output data of the first counter 90 corrected by the carry signal with the data held in the register 40 on the electrostatic capacitance detector side that is the correct absolute position information is, for example, as shown in FIG. It is configured.

That is, the comparison circuit 100 includes an adder 102 that takes the difference between the data (input A) of the register 40 and the data (input B) of the first counter 90, a decoder 104 that determines the addition result, and this decoder. 104 output to N
It is composed of an edge detection circuit 106 for generating a G signal. The decoder 104 uses the truth table shown in FIG.
As shown in 3, when the difference between inputs A and B exceeds ± 2, "1" output is output.
A signal is generated.

The edge detection circuit 10 in the subsequent stage of the decoder 104
6 is composed of two D-type flip-flops and an AND gate, and is given to the first counter 90 by N.
It is used to convert the G signal into an appropriate pulse width (the cycle of the clock CK2 in the figure). FIG. 14 is a timing chart showing how the NG signal is generated by the comparison circuit 100. When the NG signal is generated from the comparison circuit 100 in this way, this is given to the first counter 90 as a load (LD) signal, and the first counter 9
The capacitance type absolute signal CAPDATA, which is the correct absolute position data of the register 40, is reset to 0 again. The function of the comparison circuit 100 can be easily realized by software calculation by a microcomputer.

The NG signal obtained from the comparison circuit 100 is simultaneously used as a zero clear signal of the second counter 140 for movement compensation. That is, the second counter 140
Counts the counting pulse from the carry generator 80, which is cleared to zero at the start of presetting of the first counter 90. As a result, the second counter 140 detects the scale movement amount until the preset operation is completed, adds and subtracts the scale movement amount to and from the output from the register 40, and finely adjusts the absolute position data given to the first counter 90. are doing.
That is, the preset error is compensated.

FIG. 15 shows the overall construction of an absolute encoder according to another embodiment of the present invention. Parts corresponding to those in FIG. 1 are assigned the same reference numerals as those in FIG. 1 and detailed description thereof is omitted. In this embodiment, a second scale compensation second
The up / down counter is the first counter 140 of the
Is interposed in series with the counter 90, specifically, between the first counter 90 and the carry generator 80.

The first counter 90 is provided with a preset enable (PE) terminal for notifying the completion of presetting, and the second counter 140 is provided with the first counter 9
CS with 0 output from PE terminal input as select signal
A terminal is provided. When the CS terminal is disabled, that is, when the PE terminal of the first counter is disabled, the second counter 140 outputs the count signal for the count up to that point at the cycle of the external clock CLOCK. It is supplied to the counter 90 of 1 as a correction signal, and the output internal count value is subtracted. When the CS terminal changes from disable to enable, the second counter 140 is cleared to zero and starts counting.

While the CS terminal is enabled, the second counter 140 counts the output of the carry generator 80 without outputting a count signal to the first counter 90.
Then, the first counter 90 is preset and P
The E terminal is disabled (hence the second counter 1
When the CS terminal of 40 is disabled, the count value of the second counter 140 (corresponding to the amount of scale movement from the preset start to the end) during that period is again given to the first counter 90 as correction data. Therefore, also in this embodiment, as in the previous embodiment, the delay of the absolute position data calculation and the preset error due to the scale movement are compensated.

FIG. 16 shows an absolute encoder according to still another embodiment of the present invention. In this embodiment, FIG.
Instead of the interpolation circuit 70 and the carry generator 80 of the embodiment of FIG.
A count pulse generation circuit 200 for directly generating count pulses from A and CB is provided. The output of the count pulse generation circuit 200 is directly input to the first counter 90 and the second counter 140.

In this embodiment, the two-phase square wave signals A0 and B0 for external output are also generated by the EOR gate 130 by using the lower digit data of the first counter 90. Thereby, the two-phase square wave signals A0 and B0 can be synchronized with the serial output S0 obtained from the shift register 110.

In this embodiment, since the interpolation is not performed, the resolution is inferior to that of the previous embodiment, and the capacitance type and photoelectric type count pulses have the same resolution, but the circuit structure is simple. Note that the same count pulse generating means as in FIG. 16 can be applied to the embodiment of FIG. 15 in which the second counter 140 for movement compensation is connected in series with the first counter 90.

FIG. 17 shows an absolute encoder according to another embodiment of the present invention. In this embodiment, the configuration of the photoelectric detector 50 side in the embodiment of FIG. 1 is not an incremental type but an absolute type. In this case, the photoelectric absolute code pattern is formed on, for example, four photoelectric tracks on the scale. Then, a photoelectric detector 301 that reads these code patterns
˜304, photoelectric detection circuits 311 to 314 for processing the output of each photoelectric detector to generate parallel outputs g0 to g3 of the gray code, and these gray code outputs g0 to g3 into a binary (BIN) code. A decoder 320 for converting is provided.

Each photoelectric detector 301 in this embodiment
To 304 analog output waveforms and Gray code output g obtained by processing these with photoelectric detection circuits 311 to 314
The waveforms of 0 to g3 are shown in FIG. Photoelectric detection circuit 311
The decoder 320 can be omitted when the BIN code output is directly obtained by ˜314. According to this embodiment, one measurement with high resolution and wide dynamic range can be performed as in the embodiment of FIG. 1 without using an interpolation circuit. In the embodiment of FIG. 15 in which the second counter 140 for movement compensation is connected in series with the first counter 90, FIG.
It is possible to apply an absolute type photoelectric detection means similar to that of 7.

[0052]

As described above, according to the present invention, a capacitance type detector and a photoelectric type detector are combined to ensure high-speed follow-up of data display, high resolution with a small number of tracks, and wide length measurement. It is possible to obtain absolute data in a range, and further to obtain an absolute encoder having a preset error compensation function.

[Brief description of drawings]

FIG. 1 shows an absolute encoder according to an embodiment of the present invention.

FIG. 2 shows a detector configuration of the same embodiment.

FIG. 3 shows an enlarged view of the scale of FIG.

FIG. 4 is a diagram for explaining the principle of a capacitance type absolute measuring device.

FIG. 5 is a diagram for explaining the principle of a capacitance type absolute measuring device.

FIG. 6 shows how position data is combined in the same embodiment.

FIG. 7 shows a configuration of a photoelectric detector of the same example.

FIG. 8 shows a configuration of an interpolation circuit of the same embodiment.

FIG. 9 is an operation timing chart of the interpolation circuit.

FIG. 10 shows a configuration of a carry generator according to the embodiment.

FIG. 11 is an operation timing chart of the carry carry generator.

FIG. 12 is a configuration of a comparison circuit of the same embodiment.

FIG. 13 shows a truth table of the decoder in the comparison circuit.

FIG. 14 shows a preset operation by the comparison circuit.

FIG. 15 shows an absolute encoder according to another embodiment of the present invention.

FIG. 16 shows an absolute encoder according to still another embodiment of the present invention.

FIG. 17 shows an absolute encoder according to still another embodiment of the present invention.

FIG. 18 is an operation timing chart according to the embodiment.

[Explanation of symbols]

10 ... Scale, 20 ... Capacitance type detector, 30 ... Capacitance type detection circuit, 40 ... Register, 50 ... Photoelectric detector, 60 ... Photoelectric detection circuit, 70 ... Interpolation circuit, 80 ... Carry Generator, 90 ... First counter, 100 ... Comparison circuit, 110 ... Shift register, 120 ... RS flip-flop, 130 ... EOR gate, 140 ... Second counter, 150 ... Adder.

Claims (5)

[Claims] 1. A scale on which a capacitance type absolute code pattern and a photoelectric type incremental code pattern are formed, a capacitance type detection unit for reading the capacitance type absolute code pattern to obtain absolute position data, A photoelectric detection unit that reads a photoelectric incremental code pattern to obtain relative displacement amount data of the scale, absolute position data from the electrostatic capacitance detection unit is preset, and a relative displacement output from the photoelectric detection unit. A first counting means for correcting and outputting the absolute position data based on the quantity data is compared with the absolute position data output by the first counting means and the absolute position data output by the capacitance type detecting means. Then, when the difference exceeds a predetermined value, the capacitance type is added to the first counting means. Comparing means for presetting the absolute position data from the outputting means again; and counting the relative movement amount of the scale at the time of presetting the first counting means, and presetting the first counting means based on the count value. An absolute encoder having a second counting means for compensating the value. 2. A capacitance type absolute code pattern and a scale on which a high resolution photoelectric incremental code pattern having a short spatial wavelength and a high resolution are formed, and the capacitance type absolute code pattern is read to determine a higher absolute position. Capacitive detection means for obtaining digit data, photoelectric detection means for reading the photoelectric incremental code pattern to obtain lower digit data of absolute position, and least significant digit of the upper digit data based on the lower digit data A carry generation means for generating a carry signal to a carry, and a first count for presetting the higher-order digit data from the capacitance type detection means and correcting and outputting the upper-order digit data by the carry signal. Means, upper digit data output by the first counting means, and upper digit data output by the capacitance type detection means Comparing means for comparing the data and comparing means for resetting the upper digit data from the capacitance type detecting means to the first counting means again when the difference exceeds a predetermined value; and the first counting means. Output means for synthesizing and outputting the upper digit data output from the upper digit data and the lower digit data obtained from the photoelectric detection means, and counting the relative movement amount of the scale during presetting of the first counting means, An absolute encoder, comprising: a second count means for compensating the preset value of the first count means based on the count value. 3. A capacitance type absolute code pattern and a scale on which a photoelectric type absolute code pattern having a short spatial wavelength and a high resolution and having a high resolution are formed, and the capacitance type absolute code pattern is read to obtain a higher absolute position. Capacitive detecting means for obtaining digit data, photoelectric sensing means for reading the photoelectric absolute code pattern to obtain lower digit data of absolute position, and among the upper digit data based on the lower digit data A carry generating means for generating a carry signal to the least significant digit, and upper carry data from the capacitance type detecting means are preset, and the first carry data is corrected and output by the carry signal. Counting means, upper digit data output by the first counting means, and upper digit data output by the capacitance type detecting means. Comparing means for comparing the data and comparing means for resetting the upper digit data from the capacitance type detecting means to the first counting means again when the difference exceeds a predetermined value; and the first counting means. Output means for synthesizing and outputting the upper digit data output from the upper digit data and the lower digit data obtained from the photoelectric detection means, and counting the relative movement amount of the scale during presetting of the first counting means, An absolute encoder, comprising: a second count means for compensating the preset value of the first count means based on the count value. 4. A register for temporarily accumulating the obtained upper digit data at the output of said capacitance type detection means is provided, said second counting means is provided in parallel with said first counting means, and The second data is added to the output data of the register.
4. The absolute encoder according to claim 2, further comprising addition means for adding / subtracting the count value of the counting means and outputting it as a preset value compensated to the first counting means. 5. A register for temporarily accumulating the obtained upper digit data is provided at the output of the capacitance type detection means,
The second counting means is interposed between the first counting means and the carry generating means, and the second counting means is controlled by the first counting means so that the relative scales are preset. The absolute encoder according to claim 2 or 3, wherein the amount of movement is counted to compensate the preset value of the first counting means.