JPH0822962A - Manufacture of semiconductor wafer - Google Patents

Abstract

PURPOSE:To improve the growth method itself of a HgCdTe crysral layer, enable flatening the surface of the layer, and improve the quality of the HgCdTe crysral itself. CONSTITUTION:A substratum like a cadmium tellurium layer or a cadmium zinc tellurium layer or a cadmium tellurium selenium layer or a cadmium zinc tellurium selenium layer whose unevenness step-difference of the surface does not exceed 2.0mum is formed on a GaAs substrate. A mercury cadmium tellurium crystal layer is grown on the substratum by applying a thermal decomposition method whose main materials are organic cadmium, organic tellurium and inorganic mercury.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chemical vapor phase epitaxy (organic chemical vapor deposition) using an organic material and an inorganic material on a substrate made of, for example, GaAs having a surface whose surface index is (100) as a main surface.
apodeposition: MOCVD, or metallicorganic vapor phase
e epitaxy (MOVPE) method, and mainly relates to a method for producing a semiconductor wafer on which a crystal layer made of mercury cadmium tellurium (HgCdTe) used for infrared detection is grown.

[0002]

2. Description of the Related Art Generally, when a crystal layer made of HgCdTe is grown by applying, for example, the MOCVD method, protrusions called hillocks are generated as defects on the surface.

FIG. 12 shows HgC formed on a GaAs substrate.
FIG. 13 is a micrograph for explaining hillocks generated in the dTe thin film, and FIG. 13 is an explanatory diagram similarly showing hillocks. In the figure, (A) is a plane, (B) is a side surface,
(C) shows the front, W shows the maximum width of the hillock, L shows the length of the hillock, and H shows the height of the hillock.

As can be seen from the figure, the hillocks are usually elongated and have a width W of about 20 μm, a length L of 80 μm and a height H of 10 μm.
Has dimensions.

Usually, hillocks of the above size are
Density: 1 × 10 ² [pieces / cm ² ] to 3 × 10 ³ [pieces / cm ² ]
cm ² ].

The hillocks described above cause defects in the circuit pattern in the semiconductor device manufacturing process such as resist coating, mask alignment in patterning, ion implantation, etc., and thus deteriorate product yield.
It became necessary to eliminate hillocks in the HgCdTe crystal layer and flatten it.

Therefore, conventionally, the HgCdTe crystal layer is grown and then planarized by mechanical means such as polishing the surface thereof.

[0008]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention As described above, Hg
When the surface of the CdTe crystal layer is polished and planarized by mechanical means, the purpose of reducing defects in the circuit pattern and the like can be achieved fairly well, but when the characteristics of the device are analyzed in detail, , The quality of the semiconductor crystal itself, such as Hg and Cd, at the location where hillocks are formed.
It has been clarified that the composition ratio and the dislocation density, etc. are different from those of the semiconductor crystal in other ordinary parts, which deteriorates the characteristics of the device.

The present invention intends to improve the method of growing the HgCdTe crystal layer itself so that the surface of the HgCdTe crystal layer can be flattened and the HgCdTe crystal itself can be made of high quality.

[0010]

The inventor of the present invention has proposed a conventional MO
Applying the CVD method, the HgCdTe crystal layer, that is, FIG.
A number of experiments were repeated on the growth of the HgCdTe crystal layer described with reference to FIGS. 2 and 13 and the results were examined in detail. As a result, a remarkable phenomenon was confirmed as to the cause of hillock formation.

That is, it was found that hillocks in the HgCdTe crystal layer were generated due to hillocks in the underlying CdTe layer, and the height of hillocks in the CdTe layer was 2.0. It was found that low hillocks less than [μm] do not cause hillocks generated on the surface of the HgCdTe crystal layer.

FIG. 1 shows CdTe formed on a GaAs substrate.
It is a microscope picture for explaining a hillock generated in a layer (thin film).

In FIG. 1, (100) 2 ° off (10-1)
The surface of a CdTe layer grown on a GaAs substrate is shown.

The outline of the steps applied when growing the CdTe layer shown in FIG. 1 is as follows.

(1) Liquid sealing and pulling up method (liqui)
d encapsulation Czochrals
A (100) 2 ° off (10-1) GaAs substrate grown by ki: LEC is prepared.

(2) Heat treatment is carried out at a temperature of 580 [° C.] for a time of 15 [min] while flowing hydrogen gas in the atmospheric pressure MOCVD reactor to remove the oxide film on the GaAs substrate surface.

(3) In the same MOCVD reactor, the temperature was lowered to 450 [° C.] and diethyl zinc (DEZ) was added.
_{n: Zn (C 2 H 5} ) 2) the 8 × 10 ^-6 [atm], diisopropyl tellurium _{(DIPTe: (CH 3) 2} CH-
Te) is supplied so as to be 4 × 10 ⁻⁶ [atm], and the ZnTe layer is grown for 5 minutes.

(4) In the same MOCVD reactor, the temperature was lowered to 410 [° C.] and dimethyl cadmium (D
MCd: Cd (CH ₃ ) ₂ ) at 5 × 10 ⁻⁵ [atm],
DIPTe is supplied so as to be 1.5 × 10 ⁻⁴ [atm], and the CdTe layer is grown for 120 minutes.

FIG. 2 is a diagram showing the results of measuring the unevenness on the surface of the CdTe layer shown in FIG. 1 with a surface roughness meter. The horizontal axis shows the distance [μm] on the surface of the CdTe layer. ,
The vertical axis shows the irregularities [Å] on the surface of the CdTe layer.

The data shown in the figure show a part of the measured results. For example, the height is 4 [μm] or 5
The protrusion of [μm] is clearly observed.

FIG. 3 is a photomicrograph for explaining hillocks generated in the HgCdTe crystal layer (thin film) formed on the CdTe layer shown in FIG.

As shown by the arrow in FIG. 1, hillocks of a rhomboid tetrahedron seen on the surface of the CdTe layer and H as indicated by the arrow in FIG.
The positions correspond to the hillocks found on the surface of the gCdTe crystal layer.

The hillocks in the HgCdTe crystal layer shown in FIG. 3 have a one-to-one correspondence in crystallographic plane orientation with the hillocks shown in FIG.

However, the way of its development differs depending on the growth conditions of the CdTe crystal and the growth condition of the HgCdTe crystal, and therefore the appearance thereof differs, and the crystallographic plane orientation is the same. For example, both can be determined to be the same kind of hillocks.

FIGS. 4 to 6 are tables showing the relationship between the height of CdTe hillocks and the height of HgCdTe hillocks.
The numbers on the left side of FIGS. 4 to 6, that is, No.
1 to No. 80 is the number given to Hillock,
Therefore, in the CdTe layer, No. Hillock 1 is H
No. in the gCdTe crystal layer. You may recognize that it is the base of Hillock of 1.

FIG. 7 is a side sectional view showing a main part of the semiconductor wafer when the data shown in FIGS. 4 to 6 is obtained.

In the figure, 1 is a GaAs substrate and 2 is Cd.
Te layer, 3 is HgCdTe crystal layer, 2A is hillock in CdTe layer, 3A is hillock in HgCdTe crystal layer, No. X indicates the number given to each hillock.

Here, the thickness of the GaAs substrate 1 is 600.
[Μm], the thickness of the flat portion of the CdTe layer 2 is 4.
1 [μm], and the thickness of the flat portion of the HgCdTe crystal layer 3 is 6.5 [μm].

Looking at, for example, hillock No. 3 in FIG. 4, the hillock height of the CdTe layer 2 is 1.5 [μm],
The hillock height of the HgCdTe crystal layer 3 is 0.0 [μ
m], and looking at Hillock No. 4 for example, Cd
The hillock height of the Te layer 2 is 1.0 [μm], HgCdT
It is observed that the hillock height of the e crystal layer 3 is 0.0 [μm].

However, for example, in No. 1 of hillock, the hillock height of the CdTe layer 2 is 6.0 [μm],
The hillock height of the HgCdTe crystal layer 3 is 8.0 [μ
m], and for example, in Hillock No. 5, Cd
The hillock height of the Te layer 2 is 5.0 [μm], HgCdT
It is observed that the hillock height of the e crystal layer 3 is 4.5 [μm].

As described above, when comprehensively examining the data of FIGS. 4 to 6, if the height of the hillock generated in the CdTe layer 2 does not exceed a certain value, the hillock is formed in the HgCdTe crystal layer 3. It turns out that does not occur.

FIG. 8 is a diagram collectively showing the data shown in FIGS. 4 to 6, in which the abscissa represents the height of CdTe hillocks and the ordinate represents the height of HgCdTe hillocks. is there.

As is clear from the figure, as the height of the CdTe hillocks increases, the height of the HgCdTe hillocks also increases, and it can be seen that a positive correlation exists between them.

It should be noted here that the phenomenon in which HgCdTe hillocks do not occur unless the height of CdTe hillocks exceeds 2 [μm] is prominent. Therefore, if the height of the CdTe hillocks can be kept below 2 [μm] at all times, the surface of the HgCdTe crystal layer can be made flat without hillocks.

From the above, in the method of manufacturing a semiconductor wafer according to the present invention, (1) the unevenness of the surface is 2.0 [μ] on the GaAs substrate.
m], a step of forming a cadmium tellurium layer not exceeding
Or a step of growing a mercury cadmium tellurium crystal layer on the cadmium tellurium layer, or,

(2) In the above (1), the GaAs substrate having a main surface with a surface index of (100) is baked in hydrogen gas prior to the formation of the cadmium tellurium layer, or

(3) In the above (1), a GaAs substrate having a main surface with a surface index of (100) is baked in a hydrogen gas containing a gas containing As as a main material prior to the formation of the cadmium tellurium layer. Or

(4) In the above (1), (2) or (3), a thermal decomposition method using organic cadmium and organic tellurium as main raw materials on a GaAs substrate having a main surface with a surface index of (100). Is applied to form a cadmium tellurium layer, the ratio of the organic cadmium and the organic tellurium is selected, or,

(5) In the above (1) or (2) or (3) or (4), G having a major surface with a surface index of (100)
The method is characterized in that the ratio of the organic cadmium and the organic tellurium is changed during the growth when the cadmium tellurium layer is formed by applying the thermal decomposition method using organic cadmium and organic tellurium as the main raw materials on the aAs substrate, or

(6) In the above (1) or (2) or (3) or (4) or (5), a GaAs substrate whose main surface is a surface whose surface index is inclined from (100) Characterized by the use, or

(7) In (1) or (2) or (3) or (4) or (5) or (6), the GaAs substrate manufactured by applying the horizontal Bridgman method is used. Feature or

(8) In the above (1) or (2) or (3) or (4) or (5) or (6) or (7), G
The surface of the cadmium tellurium layer grown on the aAs substrate is flattened by applying a shaping method such as polishing or etching, or

(9) Applying a thermal decomposition method using organic cadmium, organic zinc, and organic tellurium as main raw materials, GaA
s a step of growing a cadmium zinc tellurium layer having a surface unevenness not exceeding 2.0 [μm] on a substrate, and a step of growing a mercury cadmium tellurium crystal layer on the cadmium zinc tellurium layer Or that
Alternatively,

(10) By applying a thermal decomposition method using organic cadmium, organic tellurium and organic selenium as main raw materials, G
The method includes a step of growing a cadmium tellurium selenium layer whose surface unevenness does not exceed 2.0 [μm] on an aAs substrate, and a step of growing a mercury cadmium tellurium crystal layer on the cadmium tellurium selenium layer. Or

(11) By applying the thermal decomposition method using organic cadmium, organic zinc, organic tellurium, and organic selenium as the main raw materials, the unevenness of the surface is 2.0 on the GaAs substrate.
Or a step of growing a cadmium zinc tellurium selenium layer not exceeding [μm], and a step of growing a mercury cadmium tellurium crystal layer on the cadmium zinc tellurium selenium layer, or

(12) A cadmium tellurium layer, a cadmium zinc tellurium layer, a cadmium tellurium selenium layer, or a cadmium zinc tellurium selenium layer is further formed on the GaAs substrate after forming a layer in which the unevenness of the surface does not exceed 2.0 [μm]. The method is characterized by including a step of growing one layer selected from the above, and a step of growing a mercury cadmium tellurium crystal layer on the selected and grown one layer.

[0047]

As described above, the present invention employs a simple means for suppressing the unevenness of the surface of the underlying layer during the growth of the mercury-cadmium tellurium layer to less than 2.0 [μm]. As a result, it became possible to make the surface of the mercury-cadmium-tellurium layer formed on the GaAs substrate, which plays a major role in infrared detection, to be flat without hillocks, thus improving the manufacturing yield of semiconductor devices. ,Also,
The characteristics of the semiconductor device can also be improved.

[0048]

EXAMPLE C on a GaAs substrate according to an example of the present invention
A case of growing an HgCdTe crystal layer through a dTe layer will be described.

(1) Horizontal Bridgeman (HB: hor)
A GaAs substrate grown according to the method of zonal bridgman) is prepared. In this case, the GaAs substrate is preferably (100) 2 ° off (10-1).

(2) In the atmospheric pressure MOCVD reactor, heating is performed at a temperature of 580 [° C.] for 15 [minutes] while flowing hydrogen gas to remove the oxide film on the surface of the GaAs substrate.

(3) In the same MOCVD reactor, the temperature was lowered to 450 [° C.] and diethyl zinc (DEZ) was added.
n: (C ₂ H ₅ ) ₂ Zn) is 8 × 10 ⁻⁶ [atm], diisopropyl tellurium (DIPTe: (C ₃ H ₇ ) ₂ CH
-Te) is supplied so as to be 4 × 10 ⁻⁶ [atm],
The ZnTe layer is grown for 5 minutes.

(4) In the same MOCVD reactor, the temperature was lowered to 410 [° C.], and dimethyl cadmium (D
MCd: (CH ₃ ) ₂ Cd) at 5 × 10 ⁻⁵ [atm],
DIPTe is supplied so as to be 1.5 × 10 ⁻⁴ [atm], and the CdTe layer is grown for 120 minutes. The unevenness on the surface of the CdTe layer thus grown was measured with a surface roughness meter, and it was confirmed to be 1.0 [μm] or less.

(5) In the same MOCVD reactor, the temperature was lowered to 360 [° C.] and the DMCd was set to 1 × 10.
^-4 [atm], DIPTe at 2 × 10 ^-3 [atm], H
g to be 1 × 10 ⁻² [atm], and
The Hg _0.8 Cd _0.2 Te layer is grown for 240 minutes. The surface of the HgCdTe layer grown in this manner is flat.

FIG. 9 shows GaA according to one embodiment of the present invention.
6 is a micrograph for explaining hillocks generated in a CdTe layer (thin film) formed on an s substrate.

In FIG. 9, (100) 2 ° off (10-1)
The surface of a CdTe layer grown on a GaAs substrate is shown.

FIG. 10 is a diagram showing the result of measuring the unevenness on the surface of the CdTe layer shown in FIG. 9 with a surface roughness meter. The horizontal axis shows the distance [μ in the surface of the CdTe layer.
m], and the vertical axis represents the unevenness [Å] on the surface of the CdTe layer.

The data shown in the figure show a part of the measured results, but it is clearly seen that the height of the unevenness is 1 [μm] or less.

This phenomenon is explained for the following reasons. That is, the surface index grown by the HB method is (10
When the GaAs substrate of 0) is heated at a temperature of 580 [° C.] for 15 [min], not only the oxide film on the surface of the GaAs substrate is removed but also some As atoms are dissociated.

Te atoms are contained in the lattice points where As atoms are dissociated, and the (111) B plane is formed in the ZnTe layer. Zn
Since the growth rate of the Te (111) B plane is higher than that of the ZnTe (100) plane, it becomes a protrusion along with the growth. In the subsequent growth of CdTe, the same relationship is maintained,
It is considered that the protruding portion becomes apparent as seen in FIG.

This phenomenon is due to the EPB (etch-pit density) showing the crystallinity of the GaAs substrate by the HB method.
y) is 2 to 6 × 10 ³ [cm ⁻² ], while LEC
(Liquid-encapsulated Czoc
The GaAs substrate produced by the Halski method has an EPD of 3 to 8 × 10 ⁴ [cm ⁻² ] which is one digit higher, and the hillock of the CdTe layer grown on the GaAs substrate by the LEC method is H.
This corresponds to the fact that the number of hillocks in the CdTe layer formed on the GaAs substrate by the B method is larger than that in hillocks.

FIG. 11 is a photomicrograph for explaining the flatness of the surface of the HgCdTe crystal layer (thin film) formed on the CdTe layer shown in FIG.

It is apparent that the surface of the HgCdTe crystal layer shown in FIG. 11 does not have the unevenness shown in FIG.

In the present invention, the height of the protrusions in the irregularities generated in the CdTe layer is suppressed to less than 2 [μm], and therefore, the HgCdTe crystal layer having a flat surface can be obtained. The present invention is not limited to the above embodiment, and many other modifications can be realized, and several examples will be illustrated below.

Select the baking conditions for the GaAs substrate. That is, prior to growing a CdTe layer on a GaAs substrate whose main surface has a surface index of (100), for example, baking is performed in hydrogen gas to increase the height of protrusions in the unevenness of the CdTe layer to 2 It can be suppressed to less than [μm]. In this case, if it is necessary to compensate for the loss of As in GaAs by baking, As in hydrogen gas
It is advisable to mix a gas containing as a main raw material.

The reason why the object can be achieved by such means is that the baking controls the oxide film thickness and As vacancies on the surface of the GaAs substrate. Is there a small number of dissociated vacancies?
Alternatively, if the size of the vacancy block is small, it is difficult to form the ZnTe (111) B surface which is a hillock generation source.

When growing a CdTe layer, organic Cd
And change the ratio of organic Te in the middle. That is, by applying a thermal decomposition method using DMCd and DiPTe as main raw materials on a GaAs substrate having a main surface with a surface index of (100), Cd
DMC for the first 10 minutes when forming the Te layer
d is 1 × 10 ⁻⁵ [atm], and DiPTe is 5 ×
Concentration of 10 ⁻⁵ [atm], that is, DiPTe / DMCd
= 5, and then DMC for 110 [minutes] thereafter.
d is 5 × 10 ⁻⁵ [atm], and DiPTe is 1.
Concentration of 5 × 10 ⁻⁴ [atm], that is, DiPTe / DM
Cd = 3 is flown to grow.

It has been experimentally confirmed that the crystallinity of the grown CdTe layer is improved by doing so.

[0068]

In the method for producing a semiconductor wafer according to the present invention, a thermal decomposition method using organic cadmium and organic tellurium as the main raw materials is applied on a GaAs substrate and the surface unevenness is 2.0 [μm]. A cadmium tellurium crystal layer is formed by forming a cadmium tellurium layer that does not exceed the above temperature and applying a thermal decomposition method using organic cadmium, organic tellurium and inorganic mercury as the main raw materials on the cadmium tellurium layer.

As described above, the present invention employs a simple means for suppressing the unevenness of the surface of the underlying layer during the growth of the mercury-cadmium tellurium layer to less than 2.0 [μm]. As a result, it became possible to make the surface of the mercury-cadmium-tellurium layer formed on the GaAs substrate, which plays a major role in infrared detection, to be flat without hillocks, thus improving the manufacturing yield of semiconductor devices. Also, the characteristics of the semiconductor device can be improved.

[Brief description of drawings]

FIG. 1 CdTe layer (thin film) formed on a GaAs substrate
3 is a photomicrograph for explaining hillocks generated in the.

FIG. 2 is a diagram showing a result of measuring unevenness on the surface of the CdTe layer shown in FIG. 1 with a surface roughness meter.

FIG. 3 is a diagram of HgCd formed on the CdTe layer shown in FIG.
It is a microscope picture for explaining a hillock generated in a Te crystal layer (thin film).

FIG. 4 is a table showing the relationship between the height of CdTe hillocks and the height of HgCdTe hillocks.

FIG. 5 is a table showing the relationship between the height of CdTe hillocks and the height of HgCdTe hillocks.

FIG. 6 is a table showing the relationship between the height of CdTe hillocks and the height of HgCdTe hillocks.

7 is a fragmentary side view showing a semiconductor wafer when the data shown in FIGS. 4 to 6 is obtained. FIG.

FIG. 8 is a diagram collectively showing the data shown in FIGS. 4 to 6;

FIG. 9 is a micrograph for explaining hillocks generated in a CdTe layer (thin film) formed on a GaAs substrate according to an example of the present invention.

FIG. 10 is a diagram showing the results of measuring the unevenness on the surface of the CdTe layer shown in FIG. 9 with a surface roughness meter.

11 is a diagram of HgC formed on the CdTe layer shown in FIG. 9;
It is a microscope picture for explaining the flatness in the surface of a dTe crystal layer (thin film).

FIG. 12 is a micrograph for explaining hillocks generated in a HgCdTe thin film formed on a GaAs substrate.

FIG. 13 is an explanatory diagram showing hillocks generated in a HgCdTe thin film formed on a GaAs substrate.

[Explanation of symbols]

 W Maximum width of hillock L Length of hillock H Height of hillock 1 GaAs substrate 2 CdTe layer 3 HgCdTe crystal layer 2A Hillock in CdTe layer 3A HgCdTe crystal layer hillock No. X The number given to Hillock

Claims (12)

[Claims] 1. A GaAs substrate having a surface unevenness of 2.0 steps.
A method for producing a semiconductor wafer, comprising: a step of forming a cadmium tellurium layer having a thickness not exceeding [μm]; and a step of growing a mercury cadmium tellurium crystal layer on the cadmium tellurium layer. 2. The method for producing a semiconductor wafer according to claim 1, wherein a GaAs substrate having a major surface with a surface index of (100) is baked in hydrogen gas prior to the formation of the cadmium tellurium layer. 3. A GaAs substrate having a main surface with a surface index of (100) is baked in a hydrogen gas containing a gas containing As as a main material prior to the formation of the cadmium tellurium layer. Manufacturing method of semiconductor wafer. 4. A GaAs having a major surface with a surface index of (100).
The ratio of the organic cadmium and the organic tellurium is selected when a cadmium tellurium layer is formed by applying a thermal decomposition method using organic cadmium and the organic tellurium as main materials on a substrate. A method for manufacturing a semiconductor wafer as described above. 5. GaAs having a major surface with a surface index of (100)
3. The ratio of the organic cadmium and the organic tellurium is changed during the growth when the cadmium tellurium layer is formed by applying a thermal decomposition method using organic cadmium and the organic tellurium as the main raw materials on the substrate. Alternatively, the method for manufacturing a semiconductor wafer according to 3 or 4. 6. The method for producing a semiconductor wafer according to claim 1, wherein a GaAs substrate whose main surface is a surface whose surface index is inclined from (100) is used. 7. A G produced by applying a horizontal Bridgman method.
7. The method for producing a semiconductor wafer according to claim 1, wherein an aAs substrate is used. 8. The surface of the cadmium tellurium layer grown on a GaAs substrate is planarized by applying a shaping method such as polishing or etching. Alternatively, the method for manufacturing a semiconductor wafer according to 6 or 7. 9. A cadmium zinc tellurium layer whose surface unevenness does not exceed 2.0 [μm] is grown on a GaAs substrate by applying a thermal decomposition method using organic cadmium, organic zinc and organic tellurium as main raw materials. A method of manufacturing a semiconductor wafer, comprising: a step of growing a mercury cadmium tellurium crystal layer on the cadmium zinc tellurium layer. 10. A thermal decomposition method using organic cadmium, organic tellurium and organic selenium as main raw materials is applied to obtain GaAs.
A step of growing a cadmium tellurium selenium layer having a surface unevenness not exceeding 2.0 [μm] on a substrate, and a step of growing a mercury cadmium tellurium crystal layer on the cadmium tellurium selenium layer. A method for manufacturing a semiconductor wafer, comprising: 11. A thermal decomposition method using organic cadmium, organic zinc, organic tellurium, and organic selenium as main raw materials is applied to obtain a surface unevenness of 2.0 [μm] on a GaAs substrate.
A method for producing a semiconductor wafer, comprising: a step of growing a cadmium zinc tellurium selenium layer that does not exceed the above range; and a step of growing a mercury cadmium tellurium crystal layer on the cadmium zinc tellurium selenium layer. 12. A rugged surface having unevenness on a GaAs substrate.
Forming a layer not exceeding 0 [μm], and then growing one layer selected from a cadmium tellurium layer, a cadmium zinc tellurium layer, a cadmium tellurium selenium layer, and a cadmium zinc tellurium selenium layer, A method of manufacturing a semiconductor wafer, comprising a step of growing a mercury cadmium tellurium crystal layer on a single grown layer.