JPH08221977A - Semiconductor memory - Google Patents

Abstract

PURPOSE: To obtain a technique for enabling to rearrange a function of a semiconductor storage. CONSTITUTION: The functions of respective functional blocks are realized selectively by a CPU 141 according to the contents of a program memory 142. Thus, the revision setting of the function is enabled by rewriting the program memory 142, and re-design such as the re-design, etc., of integration logic of hardware associated with the revision setting of the function is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for facilitating the provision of a semiconductor memory device, and further, a semiconductor memory device having a different function for each user.
(Dynamic Random Access Memory) or S
RAM (Static Random Access Memory)
Related to effective technology.

[0002]

2. Description of the Related Art DRAM as an example of a semiconductor memory device
Is an address buffer, a decoder, as described in "LSI Handbook (Page 486-)" issued by Ohmsha, Ltd. on November 30, 1984.
A peripheral circuit such as a sense amplifier uses a dynamic circuit that operates in synchronization with a clock to reduce power consumption. Therefore, external clocks of one to three phases are required, and internal circuit clocks are generated based on these clocks to control or drive the peripheral circuits. In such a DRAM, random access is mainly performed, and by reading a row address and a column address sequentially for each access,
A memory cell is selected. Each part of the peripheral circuit is controlled by an internal clock so as to follow the procedures of row selection, detection of memory cell information, and column selection in order to prevent information destruction of the memory cell. After the read / write operation is completed, a reset time is required to initialize the internal circuit in preparation for the next operation. Therefore, the cycle time of the memory operation becomes longer than the access time.

By the way, in the semiconductor memory device such as the DRAM, in addition to general-purpose products, chips having different functions may be formed depending on user's request. With respect to relatively general functions, it is possible to selectively realize the functions according to the user's request by developing the types of semiconductor chips by the bonding master method, the master slice method, or the like. For example, development of semiconductor chip types will be described by taking refresh in a DRAM as an example.

RA that basically indicates the validity of the row address
The RAS only refresh operation performed in synchronization with the S (row address strobe) signal and the auto refresh operation by the CBR refresh that is started by asserting CAS (column address strobe) before RAS is asserted are performed. However, the stored information of the dynamic memory cell is held by such a refresh operation. In a byte wide DRAM or the like, the refresh timer mounted in the memory LSI is shifted to the self-refresh operation mode by lengthening the period in which the RAS signal is asserted low during CBR refresh for a predetermined period or longer. By this operation, the refresh operation is repeated at a preset timer cycle.
Depending on the user's request, as a refresh function, a self-refresh function may be mounted in addition to the auto-refresh function or the CBR refresh function, or the self-refresh function may be unnecessary. In order to cope with such a demand, the basic configuration of the semiconductor chip is made common, and the individually required functions are realized by developing the type of the chip. According to the above example, in terms of functional blocks, auto refresh operation,
A circuit related to the CBR refresh operation and a circuit related to the self-refresh operation are formed on one semiconductor chip. Depending on whether or not the circuit related to the self-refresh operation is selectively enabled, the product development of the semiconductor chip is performed. Be seen. Such product development is possible by the bonding master method or the master slice method. For example, in the bonding master method, a plurality of bonding pads for mode switching are formed on a chip, and the operation mode can be selected depending on which bonding pad is used in wire bonding. Further, in the master slice method, the operation mode selection is performed by adding only the wiring design of the basic cells formed on the chip.

[0005]

However, in the above-mentioned bonding master system or master slice system, since the embedded logic is fixed, the functions cannot be recombined without redesign. For example, even if the user wants to change the function, the bonding master method or the master slice method is impossible because the embedded logic is fixed.

Further, in the case of a special-purpose memory or the like which has a very small production amount, it is difficult to deal with the bonding master system or the master slice system, and individual development is unavoidable. , It is not possible to cover the special use requested by the user in detail.

An object of the present invention is to provide a technique for making it possible to rearrange the functions of a semiconductor memory device.

Another object of the present invention is to provide a technique for finely covering a special application requested by a user.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, functional blocks (11, 12, 13, 15, 16, 17) each having a plurality of functions
And a storage unit (142) for storing the function selection information for each functional block and its operation control information, and a central processing unit (141 for controlling the operation of the functional block according to the storage information of the storage unit. ) And a semiconductor memory device.

At this time, in order to easily change the definition of the external pins (P1 to Pn), the plurality of external pins and the signal transmission path to the plurality of external pins are switched under the control of the central processing unit. Switch (13) can be included.

Further, in order to stabilize the fetching of the input signal, it is possible to include a synchronizing circuit (12) for synchronizing the input signal with the clock under the control of the central processing unit.

Further, a memory cell array portion (16) having a plurality of memory cells arranged in an array and a first buffer (WB) capable of storing write data to the memory cell array under the control of the central processing unit. And a second buffer (RB) capable of storing read data from the memory cell array under the control of the central processing unit.

[0015]

According to the above-mentioned means, the central processing unit incorporated in the semiconductor memory device controls the operation of the above-mentioned functional block according to the information stored in the memory means. Therefore, different functions can be realized by changing the stored contents of the storage means. This allows the functions of the semiconductor memory device to be rearranged, and moreover covers the special application required by the user in a finely-tuned manner.

[0016]

FIG. 2 shows a communication control system according to an embodiment of the present invention.

The communication controller 20 includes an SCI controller 201, a DMA controller 202 and the like, and a RAM (random access memory) 21 for storing transmission / reception data and protocol control information, a host processor 22 and other upper layers and a system. The information is interfaced via the bus 23, and the information transmitted / received via the transmission line 24 and the reception line 25 is processed according to a predetermined communication protocol.

The SCI controller 201 is not particularly limited, but for a line control unit connected to another station via the transmission line 24 and the reception line 25, and for protocol processing necessary for data transmission / reception by this line control unit. And a buffer for temporarily storing data to be transmitted / received in a first-in first-out format, and a frame received from the line controller and a transmission packet DMA-transferred by the DMA controller 202 are internally stored. The information is processed and bit-serial information is transmitted / received. Protocol control information is further added to the transmission packet, and the transmission packet is transmitted from the line control unit. For the received frame, the validity / invalidity of the frame is determined based on the protocol control information, and the received packet data in the information field of the valid frame is sequentially stored in the built-in buffer.

The DMA controller 202 is an SCI.
According to the DMA transfer request from the controller 201, S
The packet data received by the CI controller 201 is directly controlled to be transferred to a predetermined area of the DRAM 21,
The packet data to be transmitted stored in a predetermined area 21 is directly transferred to the SCI controller 201 and controlled.

The received packet data transferred to the DRAM 21 is subjected to the upper protocol processing by the host processor 22, and the packet data to be transmitted is generated by the upper protocol processing by the host processor 22. The data main body and the block data of the higher-layer protocol control information distinguished for each packet are stored. Since the transmission / reception packet is stored in the DRAM 21 while distinguishing the upper-layer protocol control information in packet units and the transmission / reception data, the protocol control information buffer 2 divided into blocks is included in the DRAM 21.
12 and a data buffer 213 are formed.

The block lengths of the blocks of the protocol control information buffer 212 and the data buffer 213 are the same, and both buffers are arranged in a continuous address space. A transfer control table 12 is formed in the DRAM 21, for example, as an area for defining each block. This transfer control table 12 is
The first block to the nth block (n means a positive integer) are respectively included in the first descriptor to the nth descriptor, and each descriptor includes a start address, a transfer word number, and a next table start address. Is provided.

The packet received by the SCI controller 201 is transferred by the DMA controller 202 to the protocol control information buffer 212 and the data buffer 21.
In case of block transfer to 3, the DMA controller 2
02 reads the start address indicating the block start address of the protocol control information buffer included in the predetermined descriptor, transfers the predetermined number of bytes of protocol control information at the start of the received packet to the protocol control information buffer 212, and receives the received packet. The remaining data is stored in the data buffer 21.
Transfer to 3. After that, the number of data transfer words is written in the above descriptor, and the transfer control table 2 is prepared for the next received packet.
The top address next to 11 is read.

FIG. 1 shows a configuration example of the DRAM 21.

The DRAM shown in FIG. 1 is not particularly limited, but a clock pulse generator 10, an I / O (input / output) block 11, a synchronizing circuit 1 are provided.
2, switch 13, controller 14, address generator 15,
Includes a memory cell array unit 16 and a buffer memory 17,
It is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

The clock pulse generator 10 has a function of generating the clock pulse CP. Example DR
The clock pulse CP used in the AM 21 is synchronized with that generated by dividing the pulse signal oscillated by the clock pulse generator 10 and the system clock CLK in an external device, for example, a system to which this DRAM is applied. Some are generated by. The clock pulse CP generated by the clock pulse generator 10 is synchronized with the synchronization circuit 12 and the switch 1.
3, the control unit 14, the address generation unit 15, the memory array unit 16, and the buffer memory 17.

The I / O block 11 includes external pins P1 to P1.
Level conversion is performed on a signal which is coupled to n and is exchanged with the outside through the external pins P1 to Pn.

A synchronizing circuit 12 is connected to the I / O block 11. The synchronization circuit 12 has a function of synchronizing a signal input from the outside with a clock. The switch 13 is provided for switching a signal transmission path reaching the plurality of external pins P1 to Pn. By this path switching, the definition of each external pin can be changed.
For example, it is possible to switch an address pin for fetching an address, a data pin for inputting / outputting data, a control signal pin for fetching a control signal, and the like.

Between the switch 13 and the control circuit 14,
A data bus D-BUS for transmitting data, an address bus A-BUS for transmitting an address signal, and a control bus C-BUS for transmitting a control signal are provided. Since it is necessary to transfer the input address signal to the address generator 15, the address bus A-
An address generation unit 15 is coupled to BUS, and a buffer memory 17 is coupled to the data bus D-BUS to enable transmission of read / write data.

The control section 14 has a function of controlling the operation of each functional block in the DRAM 21 of the present embodiment, and has a program memory 14 for storing a function selection information for each functional block and a program including the operation control information.
2, and a CPU for controlling the operation of each functional block according to the program stored in the program memory 142
(Central processing unit) 141 is included. This CPU14
1 includes the data bus D-BUS and the address bus A-
The BUS and the control bus C-BUS are connected. The control signal from the control unit 14 is the I / O block 1
1, synchronization circuit 12, switch 13, address generation unit 1
5, the memory cell array unit 16 and the buffer memory 17.

The program memory 142 is not particularly limited, but it is a page access type programmable R in which the program can be changed in the state of being incorporated in the system.
OM, for example, EEPROM (electrically erasable and programmable read only memory) is applied. Since the operation control of each functional block is performed according to the program stored in the program memory 142, the function of each functional block can be changed by changing the stored contents of the program memory 142. That is, when the function is changed in response to a user request, the program stored in the program memory 142 may be rewritten. When the EEPROM is applied to the program memory 142 as described above, the on-board rewriting of the EEPROM is possible, so that even the shipped DRAM can be changed in function by the user side. Further, even in the case of an extremely small amount of special-purpose memory, its function can be realized by programming the program memory 142.

The address generation unit 15 has an address generation function, and the generated address is used for the memory cell array unit 16.
To be transmitted to.

The memory cell array section 16 is not particularly limited, but a memory cell array formed by arranging a plurality of dynamic memory cells in an array, and a word line selection of the memory cell array based on a row address from the address generating section. A row decoder for generating a signal, and an operation control signal for a column switch for selectively coupling a bit line coupled to a memory cell array to a common line based on a column signal from the address generation unit 15 are generated. A column decoder for doing so and a sense amplifier for amplifying weak memory cell data are included.

The buffer memory 17 is coupled to the memory cell array unit 16 and temporarily stores read data from the memory cell array unit 16 and a write buffer unit for temporarily holding write data to the memory cell array unit 16. And a read buffer section for holding the same.

Next, a detailed configuration of each part will be described.

FIG. 3 shows a configuration example of the I / O block 11.

The I / O block 11 is not particularly limited, but the input buffers IB1 to IBn and the output buffers OB1 to OBn arranged corresponding to the external pins P1 to Pn.
including. The input terminals of the input buffers IB1 to IBn and the output terminals of the output buffers OB1 to OBn are commonly connected to the corresponding external pins P1 to Pn. The output terminals of the input buffers IB1 to IBn and the input terminals of the output buffers OB1 to OBn are coupled to the synchronization circuit 12. The input buffers IB1 to IBn and the output buffers OB1 to OBn include level conversion circuits for matching the external signal level and the internal signal level of the DRAM 21 of this embodiment. This level conversion circuit enables selection of various interface formats and interface levels under the control of the control circuit 14 shown in FIG. That is, an appropriate interface format and interface level for exchanging signals with an external device are selectively set by the stored contents of the program memory 142.

FIG. 4 shows a configuration example of the synchronizing circuit 12.

A plurality of the synchronizing circuits 12 are formed corresponding to the input buffers IB1 to IBn shown in FIG. 3, but all have the same structure, and therefore one circuit structure is representatively shown in FIG. Indicated.

The latch enable signal LEB and the synchronous enable signal SEB are transmitted from the control circuit 14 shown in FIG. Clock pulse CP is transmitted from clock pulse generator 10 shown in FIG. The AND logic of the clock pulse CP and the synchronization enable signal SEB is obtained by the gate G2, and the clock pulse CP
And the inversion signal of the synchronization enable signal SEB are obtained at the gate G3.
A gate G4 for obtaining those OR logics is arranged at the subsequent stage of the gates G2 and G3, and the logic output of this gate G4 is used as a clock CLKB. Further, the clock CP is buffered by the gate G5 to obtain the clock CLKA. When the synchronous enable signal SEB is at high level, the clock CLKA and the clock CLKB are in phase, and when the synchronous enable signal SEB is at low level, the clock CLKA and clock CLKB are in opposite phase.

Gate G10 and clocked inverter G8
And are coupled in a loop shape, and the clocked inverter G9 is arranged in the preceding stage thereof, so that the input terminal Inpu
A first latch circuit 121 capable of latching the input data from t in synchronization with the clock CLKA is formed. A second latch circuit 122 capable of latching the output signal of the first latch circuit 121 in synchronization with the clock CLKB is arranged at the subsequent stage of the first latch circuit 121. Clocked inverter G
A gate G7 for inverting the clock CLKA is provided for the purpose of operating 8 and G9 complementarily. Similarly, a gate G6 for inverting the clock CLKB is provided for the purpose of operating the clocked inverters G11 and G12 complementarily.

Further, the selection circuit 123 for selecting the output signal of the first latch circuit 121 and the output signal of the second latch circuit 122, and the selection output thereof are inverted and output from the output terminal Output. Gate G1
5 are provided. The selection circuit 123 is based on the clocked inverter G15 for taking in the output signal of the second latch circuit 122, the clocked inverter G16 for taking in the output signal of the first latch circuit 121, and the select signal SELA. A gate G14 for inverting the select signal SELA is provided for the purpose of complementarily operating the clocked inverters G15 and G16. Select signal SELA is obtained by buffering latch enable signal LEB transmitted from control circuit 14 shown in FIG. 1 with gate G18.

In the above configuration, depending on the states of the sync enable signal SEB and the select signal SELA,
Different functions are performed as follows.

When the select signal SELA is at low level, it functions as a simple latch circuit for latching the input signal in synchronization with the clock CLKA. The operation timing in this case is shown in FIG. As shown in FIG. 5, when the select signal SELA is at low level,
When the clocked inverter G16 is activated, the first
The output signal of the latch circuit 121 selectively outputs the output terminal Out.
By enabling output from put, the latch operation by the first latch circuit 121 is enabled. in this case,
Since the second latch circuit 122 is not selected, the clock C
The logic of LKB is undefined.

When the select signal SELA is at high level, the clocked inverter G15 is activated and the output signal of the second latch circuit 122 can be selectively output from the output terminal Output. First
The operations of the latch circuit 121 and the second latch circuit 122 are enabled. At this time, the synchronization enable signal S
When EB is set to the high level and the clocks CLKA and CLKB are in the same phase as shown in FIG. 6, the first
By simultaneously operating the latch circuit 121 and the second latch circuit 122, double synchronization of the input signal is realized. That is, the first latch circuit 121 performs the first synchronization by the clock CLKA, and the second latch circuit 1
The second synchronization is performed at 22 with the clock CLKB, whereby the dual synchronization of the input signal is performed. On the other hand, when the select signal SELA is set to low level, the clocks CLKA and CLKB are changed as shown in FIG.
When the signals are in the opposite phase, the first latch circuit 121 and the second latch circuit 122 are operated at different timings, so that the function as the master-slave D-type flip-flop is realized.

In this way, the synchronization enable signal SEB and the latch enable signal L output from the control circuit 14 are output.
Depending on the state of EB, in the synchronizing circuit 12,
It is possible to select a function as a simple latch circuit, a function as a dual synchronizing circuit for an input signal, and a function as a master-slave D-type flip-flop.

FIG. 8 shows a configuration example of the switch 13.

As shown in FIG. 8, the switch 13 includes a plurality of switch circuits SW1 to SWn arranged corresponding to the external pins P1 to Pn. Switch circuit SW1
All of SWn have the same configuration. Switch circuit SW1
As shown in the representative configuration of each switch circuit SW
1 to SWn are n channel type MOS transistors Q11 to Q1m corresponding to the address bus A-BUS, n channel type MOS transistors Q21 to Q2m corresponding to the data bus D-BUS, and n channel type corresponding to the control bus C-BUS. MOS transistors Q31 to Q
Including 3m. The MOS transistors Q11 to Q1m,
The drain electrodes (or source electrodes) of Q21 to Q2m and Q31 to Q3m are coupled to the synchronization circuit 12, and the source electrodes (or drain electrodes) are the address bus A-BU.
S, data bus D-BUS, or control bus C-
Bound to BUS. MOS transistors Q11 to Q1
Switch control signals from the control circuit 14 shown in FIG. 1 are input to the gate electrodes of m, Q21 to Q2m, and Q31 to Q3m. By turning on the MOS transistor by the switch control signal from the control circuit 14, the output terminal of the synchronization circuit 12 can be coupled to the address bus A-BUS, the data bus D-BUS, or the control bus C-BUS. It is said that The control circuit 1 determines which MOS transistor is turned on.
4 determined by the contents of the program memory 142. In other words, the program memory 1 in the control circuit 14
The contents of 42 determine the definitions of the external pins P1 to Pn. Assuming that the switch circuit SW1 corresponds to the external pin P1, for example, MOS transistors Q11 to Q
When any one of 1m is turned on, its external pin P
1 functions as an input pin for an address signal transmitted to the address bus A-BUS. Similarly, when any of the MOS transistors Q21 to Q2m is turned on, the external pin P1 functions as an input / output pin for data exchanged via the data bus D-BUS.
When any of the MOS transistors Q31 to Q3m is turned on, the external pin P1 is connected to the control bus C-
It functions as an input pin for a control signal transmitted via BUS. Each of the address bus A-BUS, the data bus D-BUS, and the control bus C-BUS is composed of a plurality of signal lines, and which one of the MOS transistors Q11 to Q1 is assigned an external pin.
It is determined by which of m, Q21 to Q2m, and Q31 to Q3m is turned on. For example, when the MOS transistor Q11 is turned on, the external pin P1 corresponds to the lowest address, and the MOS transistor Q1
When m is turned on, the external pin P1 corresponds to the highest address.

In this way, the external pin P1 is controlled by the operation control of the MOS transistors in the switch circuits SW1 to SWn by the switch control signal from the control circuit 14.
It is possible to set the definition of ~ Pn and change it. If the definition of the external pins P1 to Pn is fixed, basically only the setting at the time of initialization of the CPU 141 is sufficient, but by the control of the switch 13, each of the address, data, and control signal is controlled. It is possible to change the coupling relationship between the path and each external pin over time, and such switch control allows the capture of address, data, and control signals over time through the same external pin. In particular, protocol type control in data communication can be facilitated. In that case, the protocol analysis is C
It can be performed by the PU 141.

FIG. 9 shows a configuration example of the address generator 15.

As shown in FIG. 9, the address generator 15 has a row address latch 9 for latching a row address fetched via the address bus A-BUS.
1, a refresh counter 92 for generating an address in a refresh operation for holding data in a dynamic memory cell, a column address latch 93 for latching a column address fetched via an address bus A-BUS, A column address counter 94 capable of continuously generating a scan column address in the burst mode, an arithmetic unit 95 capable of address arithmetic for realizing an interleave mode (also called an Intel scramble mode), and a column address selection Multiplexer (MPX) 96 for. The row address output from the row address latch 91 and the column address selectively output from the multiplexer 96 are transmitted to the memory cell array unit 16 shown in FIG. A control signal SELM1 from the control circuit 14 shown in FIG. 1 is input to the multiplexer 96, and the control signal SELM1 is input.
Based on the above, the multiplexer 96 selects the output address of the column address latch 93, the output address of the column address counter 94, and the output address of the arithmetic unit 95. In the case of normal random access of the memory cell array section 16, the output address of the column address latch 93 is selectively transmitted to the memory cell array section 16 by the multiplexer 96. In the burst mode, the column address input from the outside is used as the initial address, and the column address is sequentially generated by the increment operation of the column address counter 94, which is selectively transmitted to the memory cell array unit 16 by the multiplexer 96. It Further, in the interleave mode, the arithmetic operation of the output address of the column address latch 93 and the output address of the column address counter 94 is performed by the arithmetic unit 95, and the arithmetic result is selectively stored in the memory cell array unit 16 by the multiplexer 96. Transmitted.

As described above, in the DRAM 21 of the present embodiment, the output address of the column address latch 93, the output address of the column address counter 94, and the arithmetic unit 95 according to the control signal SELM1 from the control circuit 14.
The output address of is selectively transmitted to the memory cell array section 16. The selection operation of the multiplexer 96 is determined by the stored contents of the program memory 142 in the control circuit 14.

FIG. 10 shows a structural example of the main part of the memory cell array section 16.

The memory cell array portion 16 includes, but is not particularly limited to, a plurality of memory mats including a plurality of dynamic memory cells MC. The plurality of memory mats, as one of which is representatively shown, includes a plurality of word lines W0 to WN and a pair of bit lines BL, BL * (* indicates low active or signal , Which indicates inversion), and the dynamic memory cell MC is coupled to the intersection of the word line and the bit line pair. The dynamic memory cell MC has a charge storage capacity C
1 and an n-channel type MOS transistor Q58 coupled thereto. The gate electrode and the drain electrode of the MOS transistor forming one memory cell MC are respectively coupled to the corresponding bit line and word line. By driving one word line to the selection level based on the row address, the MOS transistors Q58 of all the memory cells MC coupled thereto are turned on, and the charge storage capacitance C1 and the bit line corresponding thereto are turned on. By electrically connecting and, data writing to the memory cell MC or data reading from the memory cell MC becomes possible. Since the memory cell data is very weak, the memory cell data is amplified by the sense amplifier coupled to the bit line pair BL, BL *. In FIG. 10, although not particularly limited, a main sense amplifier 101 and a sub sense amplifier 102 are coupled to the bit line pair BL, BL *. Further, a shared sense system is adopted in order to share the bit line and the sense amplifier among a plurality of memory mats. That is, the shared MOS transistors Q56, Q57 and Q40, Q are provided in the middle of the bit line pair.
41 is provided to turn on the shared MOS transistor on the side corresponding to the selected memory mat. The shared MOS transistors Q40 and Q41 are controlled in operation by the shared control signal SHR0, and the shared MOS transistors Q56 and Q57 are controlled in operation by the shared control signal SHR1.

The main sense amplifier 101 is constructed as follows.

P-channel type MOS transistor Q54
And a n-channel MOS transistor Q55 connected in series, and a p-channel MOS transistor.
A transistor Q52 and a second inverter formed by serially connecting an n-channel MOS transistor Q53 are coupled in a ring shape. MOS transistor Q52,
Q53 series connection point and MOS transistor Q5
4 and Q55 are connected in series as input / output nodes of the main sense amplifier 101, and bit lines BL,
Bound to BL *. MOS transistor Q52,
The source electrode sides of Q54, Q53, Q55 are coupled to the main common source MCS, and a voltage of a predetermined level for the sense amplifier operation is applied via the main common source MCS.

The input / output node of the main sense amplifier 101 is an n-channel MOS transistor Q5 whose operation is controlled by a main column switch control signal MYSW generated by decoding a column address.
0 and Q51 are provided. The MOS transistors Q50 and Q51 are main column switches corresponding to the main sense amplifier 101. When the main column switch is turned on, the bit line BL,
BL * is adapted to be selectively coupled to the main common line MI / O. Further, the n-channel type MOS transistors Q63, Q64, Q65 are coupled to form a main precharge circuit. In this main precharge circuit, when the main precharge signal MPC is at a high level, the main precharge level MVMP is supplied to the bit lines BL, BL *, so that the bit lines BL, BL,
BL * is precharged.

The sub sense amplifier 102 corresponding to the main sense amplifier 101 is constructed as follows.

P-channel type MOS transistor Q47
And a n-channel MOS transistor Q48 connected in series, and a p-channel MOS transistor.
A transistor Q45 and a second inverter formed by serially connecting an n-channel MOS transistor Q46 are coupled in a ring shape. MOS transistor Q45,
Q46 in series, and MOS transistors Q47, Q
The serial connection portion of 48 is an input / output node of the sub-sense amplifier 102, and bit lines BL, BL are respectively connected via n-channel type MOS transistors Q44, Q49.
Bound to * This MOS transistor Q49,
The point of having Q44 is largely different from the configuration of the main sense amplifier described above. MOS transistors Q44, Q49
Is turned on when the sub-sense amplifier enable signal SSAE is set to a high level, and the serial connection points of the MOS transistors Q45 and Q46 and the serial connection points of the MOS transistors Q47 and Q48 are respectively connected to the bit lines BL and BL *. To conduct. The source electrodes of the MOS transistors Q45, Q47, Q46, Q48 are coupled to the sub-common source SCS, and a voltage of a predetermined level for the sense amplifier operation is applied via the sub-common source SCS.

At the input / output node of the sub sense amplifier 102, n channel type MOS transistors Q42, 4 whose operation is controlled by a sub column switch control signal SYSW generated by decoding a column address.
3 is provided. This MOS transistor Q42,
Reference numeral 43 is a sub column switch corresponding to the sub sense amplifier 102. When the sub column switch is turned on, the sub bit lines SBL, SBL *
, Are selectively coupled to the sub-common line SI / O. The n-channel MOS transistors Q60 and Q6 are connected to the sub bit lines SBL and SBL *.
A sub-precharge circuit is formed by coupling 1, Q62. In this sub precharge circuit, when the sub precharge signal SPC is at the high level, the sub precharge level SVMP is supplied to the sub bit lines SBL and SBL * to precharge the sub bit lines SBL and SBL *. Although not particularly limited, the main precharge level MVMP and the sub precharge level SVMP are set to be equal to each other.

In the memory cell array section 16 having the above structure, various control signals except for the row address and the column address are basically supplied from the control circuit 14 shown in FIG. Therefore, in reading the memory cell data, whether only the main sense amplifier 101 or the sub sense amplifier 102 is activated, or both the main sense amplifier 101 and the sub sense amplifier 102 are activated at a predetermined timing. Can be programmed. A normal memory operation is realized by setting only the main sense amplifier 101 or the sub sense amplifier 102 to be activated. Moreover, the following operations can be realized by using the main sense amplifier 101 and the sub sense amplifier 102.

FIG. 11 shows an example of operation timing in the configuration shown in FIG.

For example, when the word line W0 is driven to the selection level based on the decoded output of the row address, if the shared control signal SHR1 is set to the high level and the shared control signal SHR0 is set to the low level, the shared MOS. The transistors Q40 and Q41 are turned off, and the storage data of all the memory cells MC coupled to the word line W0 are stored in the corresponding bit lines BL and BL.
It is transmitted to *. At this time, the main common source MCS
When a voltage of a predetermined level for the sense amplifier operation is supplied to the main sense amplifier 101 via, the weak memory cell data transmitted to the bit line is amplified by the main sense amplifier 101. Then, the main column switch control signal MYSW is set to the high level and MO
When the S transistors Q50 and Q51 are turned on, the memory cell data amplified by the main sense amplifier 101 is transmitted to the main common line MI / O via the MOS transistors Q50 and Q51. Main common line M
The memory cell data transmitted to the I / O is transferred to the data bus D- shown in FIG. 1 via a main amplifier (not shown).
It is sent to BUS. Then, the sub-sense amplifier enable signal SSAE is asserted to the high level and the MOS
When the transistors Q44 and Q49 are turned on and a voltage of a predetermined level for the sense amplifier operation is applied via the sub-common source SCS, the sub-sense amplifier 10
2 is operated and the memory cell data amplified by the main sense amplifier 101 is transferred to the sub sense amplifier 1
02, so that the sub column switch control signal S
The memory cell data is output via the sub-common line SI / O at the timing when YSW is asserted to the high level. Moreover, after the sub-sense amplifier enable signal SSAE is negated to the low level, the sub-bit lines SBL and SBL * are electrically connected to the bit lines BL and BL.
Since the data is released from *, the memory cell data is held in the sub sense amplifier 102. This sub sense amplifier 1
The data held in 02 is the sub column switch control signal S
It can be read any number of times by asserting YSW high.

As described above, the main sense amplifier 101
The memory cell data amplified by the sub sense amplifier 10
Data bus D-BUS because it can be held at 2
It is possible to prepare to read the memory cell data by selecting the next word line without waiting for the completion of the output of the memory cell data to. That is, after the memory cell data is held in the sub-sense amplifier 102, bit line precharge and equalization can be performed, so that the time from the selection of a word line to the selection of the next word line can be apparently shortened. .

FIG. 12 shows a configuration example of the buffer memory 17.

As shown in FIG. 12, the buffer memory 17 is not particularly limited, but the read buffer unit RB for buffering the data output from the main amplifier 36 in the memory cell array unit 16 and the memory cell array. A write buffer unit WB for buffering write data to the unit 16 is included.

The output terminal of the read buffer section RB is coupled to the data bus D-BUS, and the read data transmitted from the main amplifier 36 is output to the data bus D-BUS via the read buffer section RB. It has become so. The read buffer unit RB is not particularly limited, but includes a D-type flip-flop for temporarily holding the data transmitted from the main amplifier 36.

The input terminals of the write buffer section WB are the data bus D-BUS and the control bus C-.
It is coupled to BUS, and it is possible to capture write data and a write flag.

The write buffer section WB includes a plurality of write buffer units WBUF1 to WBUFn. The write buffer units WBUF1 to WBUFn have the same configuration. As shown in the representative internal structure of one of them, the write buffer unit WBU
F1 to WBUFn are not particularly limited, but a plurality of D flip-flops (DF /
F) 351 to 35n and a D-type flip-flop 37 for storing the write flag of the data held therein. The number n of D-type flip-flops for holding write data is set equal to the number of bits constituting the data bus D-BUS.

The input terminals of the D-type flip-flops 351 to 35n are connected to the data bus D-BUS, and the output terminals are connected to the multiplexer 31. The multiplexer 31 has a function of selectively transmitting the output signals of the D-type flip-flops 351 to 35n and the data of the data bus D-BUS to the write amplifier 33 in the subsequent stage. Also,
A multiplexer 32 is provided so that the output signal of the D-type flip-flop 37 and the write control signal transmitted by the C-BUS can be selectively transmitted to the write amplifier controller 34 in the subsequent stage. Multiplexer 3
The operation control of 1 and 32 is controlled by the control signal SELM2 from the control circuit 14 shown in FIG.

In the above structure, the write data to the memory cell array section 16 are written in the write buffer units WBUF1 to WBUF in the order of being fetched from the data bus D-BUS.
It is sequentially taken in by the D-type flip-flop in the BUF1n. This write buffer unit WBUF1 to WBUF
Of the data taken in 1n, the write flag corresponding to the data actually written in the memory cell array unit 16 is set to "1", but if the data that does not need to be written in the memory cell array unit 16 is If there is, the write flag corresponding to that data is set to "0".

The write data and the write flag from the write buffer section WB are read out in synchronization with each other, and the write amplifier 33 and the write amplifier controller 3 respectively.
4 is transmitted. In the memory cell array section 16, the write flag “
The write data corresponding to 0 "is prohibited from being written into the memory cell array section 16. That is, only the data corresponding to the write flag" 1 "is written into the memory cell array section 16.

As described above, the D-type flip-flop 35
By temporarily holding the write data using 1 to 35n, the memory cell array operation can be matched with the external memory rate. However, when it is necessary to match the external operation and the internal operation for data writing in timing, the multiplexers 31 and 3
2, the data bus D-BUS and the control bus C-BUS are selected to form a path route, and the data bus D-BUS and the control bus C-B are formed.
The write data of US and the write flag are transmitted to the write amplifier 33 and the write amplifier controller 34. In this case, the write buffer unit WB does not function.
The operations of the multiplexers 31 and 32 are determined by the stored contents of the program memory 142.

According to the above embodiment, the following operational effects can be obtained.

(1) As described above, when the function is selected by the bonding master method or the master slice method, the built-in logic is fixed. Therefore, the function cannot be recombined unless redesigned. Even if the user wants to rearrange the functions, he / she cannot respond, but
According to the above embodiment, the function of each functional block is selectively realized by the CPU 141 in accordance with the contents of the program memory 142. Therefore, rewriting of the program memory 142 makes it possible to change and set the function. Therefore, redesign of hardware such as redesign of embedded logic is unnecessary.

(2) As the program memory 142, a page access type programmable ROM, such as an EEPROM, in which the program can be changed in a state where it is installed in the system is applied, so that the program stored in the program memory 142 can be changed. Since the operation control of each functional block is performed, it is possible to change the function of each functional block by changing the stored content of the program memory 142, that is, by changing the program. In addition, as described above, the program memory 142
When the EEPROM is applied to, the on-board rewriting of the EEPROM is possible, so that the user can change the function of the shipped DRAM.
Further, even in the case of an extremely small amount of special-purpose memory, its function can be realized by programming the program memory 142.

(3) By providing the switch 13 for switching the signal transmission path to the plurality of external pins P1 to Pn, the definition of the external pins P1 to Pn can be easily changed.

(4) By providing the synchronizing circuit 12 for synchronizing the input signal with the clock, the signal acquisition can be stabilized, and such an input signal synchronizing mode is required. It can be selectively set accordingly.

(5) The write buffer unit WB capable of storing the write data to the memory cell array unit 16 and the CPU 1
By providing a read buffer RD capable of storing the read data from the memory cell array 16 under the control of 41, the speed of data read / write can be increased, and such a write buffer section WB, The function selection of the read buffer RD is enabled by programming the control circuit 14.

FIG. 13 shows another configuration example of the address generator 15.

The address generator 15 shown in FIG.
What is different from that shown in FIG. 9 is that the number of address outputs is made plural assuming a multi-bank configuration. That is,
A plurality of row latches 131 to 13n for latching the output address are provided at the subsequent stage of the row address latch circuit 91.
Are arranged, and a plurality of column address counters 941 to 94n for generating column addresses, arithmetic units 951 to 95n for address arithmetic, and multiplexers 961 to 961 for address selection are arranged in the subsequent stage of the column address latch 93. By arranging 96n, a plurality of row addresses and column addresses can be output. The number of output row addresses and column addresses is made equal to the number of banks in the multi-bank configuration.

The row latches 131 to 13n, the column address counters 941 to 94n, and the arithmetic units 951 to 95n.
The operation of the multiplexers 961 to 96n is performed by the control circuit 14. That is, the program memory 14
2 by rewriting the program stored in the row latches 131 to 13n, the column address counter 9
It is possible to change the operation states of 41 to 94n, arithmetic units 951 to 95n, and multiplexers 961 to 96n.

A plurality of column address counters 941
Although ~ 94n is provided, it can be replaced with a single column address counter.

FIG. 14 shows another configuration example of the memory cell array section 16.

The memory cell array section 16 shown in FIG.
However, the configuration greatly different from that shown in FIG. 10 is the configuration of the sense amplifier, and the other configurations are the same.

In FIG. 14, two sense amplifiers 1
03, 104 are provided. First sense amplifier 103
The configuration is basically the same as that of the sub-sense amplifier 102 shown in FIG. However, the function is slightly different from that of the sub-sense amplifier 102, and the signals handled there are changed accordingly.

P-channel type MOS transistor Q47
And a n-channel MOS transistor Q48 connected in series, and a p-channel MOS transistor.
The transistor Q45 and a second inverter formed by connecting an n-channel type MOS transistor Q46 in series are coupled in a ring shape, and the MOS transistors Q45 and Q46.
Of the first sense amplifier 103 is connected to the bit lines BL and BL * via n-channel type MOS transistors Q44 and Q49, respectively. ing. The MOS transistors Q44 and Q49 are
The first sense amplifier enable signal SAESA is turned on by being set to a high level to turn on the MOS transistors Q45 and Q46 in series and the MOS transistors Q47 and Q48 in series to bit lines BL and BL *, respectively. Make it conductive. MOS transistor Q
The source electrode sides of 45, Q47, Q46, and Q48 are coupled to the first common source CSSA, and a voltage of a predetermined level for the sense amplifier operation is applied via the first common source CSSA.

The input / output node of the first sense amplifier 103 has an n-channel MOS transistor Q6.
A precharge circuit composed of 0, Q61 and Q62 is provided. The operation of this precharge circuit is controlled by the precharge control signal PCSA. The first column switch control signal YS generated by decoding the column address is input to the input / output node of the first sense amplifier 103.
N-channel type MOS transistors Q42 and 43 whose operations are controlled by WSA are provided. This MOS
The transistors Q42 and 43 are sub-column switches corresponding to the first sense amplifier 103. When the sub column switch is turned on, the bit line B
L and BL * are selectively coupled to the first common line I / OSA.

The second sense amplifier 104 has the same structure as that of the first sense amplifier 103, and in particular, FIG.
The configuration of the main sense amplifier 101 shown in FIG. 3 differs greatly in that n-channel type MOS transistors Q60 and Q61 are added. Further, it is composed of n-channel type MOS transistors Q63, Q64, Q65,
A precharge circuit whose operation is controlled by the precharge control signal PCSB is provided. Since the sense amplifiers are cut off from the bit lines BL, BL * by the MOS transistors Q44, Q49, Q60, Q61, the n-channel type MOS transistors Q71, Q71 are connected to the bit lines BL, BL *. A precharge circuit formed by connecting Q72 and Q73 is provided. The operation of this precharge circuit is controlled by a precharge control signal PC. In FIG. 14, the precharge levels VMPSA, VMPSB, VMP are set to be equal to each other, although not particularly limited.

FIG. 15 shows the operation timing of the configuration shown in FIG.

When the word line W0 is driven to the selection level based on the decoded output of the row address, the shared control signal SHR0 is asserted to the low level, the shared MOS transistors Q40 and Q41 are turned off, and then the word The storage data of all the memory cells MC coupled to the line W0 are stored in the corresponding bit lines BL and B.
It is transmitted to L *. At this time, the second common source CSS
A voltage of a predetermined level for the operation of the sense amplifier is supplied to the second sense amplifier 104 via B, and when the second sense amplifier enable signal SAESB is asserted to the high level, the weak signal transmitted to the bit line is transmitted. Different memory cell data is amplified by the second sense amplifier 104. This memory cell data is output to the second common line I / OSB when the second column switch control signal YSWSB goes high. The second sense amplifier enable signal SAESB is negated to the low level, and the first sense amplifier enable signal SAESA is asserted to the high level after the bit lines BL and BL * are precharged by the precharge circuit. This time, the first sense amplifier 103 can amplify the memory cell data obtained by driving the word line WN to the selected level.

As described above, the first sense amplifier 103,
And the second sense amplifier 104 both have the first
Since the operation control is enabled by the sense amplifier enable signal SAESA and the second sense amplifier enable signal SAESB, the first sense amplifier 103 and the second sense amplifier 104 are alternately switched every time a different word line is driven to the selection level. The high speed read is enabled by using this. When the word line W1 is selected after the word line W0 is selected and then the word line W0 is selected again, for example, when the word line W0 is selected, the data when the word line W0 is selected is the second sense. If the data amplified by the amplifier 104 and the word line W1 is selected is assumed to be amplified by the first sense amplifier 103, the data on the word line W0 to be selected again next is already the second sense amplifier. Since it is held in 104, if it is used, it is not necessary to select the word line W0 again, and high-speed reading of data is possible.

Further, as shown in FIG. 16, sense amplifiers SA1 and SA2 and bit lines BL11 and BL11 are used.
*, BL12, BL12 *, BL13, BL13 * may be arranged alternately. Bit line BL11,
BL11 *, BL12, BL12 *, BL13, BL1
A plurality of word lines W0 are provided so as to intersect with 3 *.
1, W02, W11, W12, W21 and W22 are provided, and the dynamic memory cells MC are coupled to the intersections thereof. In this case, the sense amplifier SA
1 and SA2, the first sense amplifier 1 shown in FIG.
03, or the configuration of the second sense amplifier 104 is applied.

An example of the operation in the above configuration will be described.

When the sense amplifier SA1 is selectively activated, the shared control signal YSW2 is set to the high level and the shared control signals YSW1, YSW3, YSW are set.
4 is low level. Thereby, the bit line BL1
By transmitting the data of 2, BL12 * to the sense amplifier SA1 via the shared MOS transistors Q18, Q19, the data can be amplified by the sense amplifier SA1. The shared control signal YSW4 may be at a high level if it is precharged. When the sense amplifier SA2 is selectively activated, the shared control signal YSW3 is set to the high level and the shared control signals YSW1 and YSW are set.
2, YSW4 is at low level. This causes the data on the bit lines BL12, BL12 * to be shared MO.
Sense amplifier S via S-transistors Q20 and Q20
The data can be amplified by the sense amplifier SA2 by being transmitted to A2. The shared control signal YSW1 may be at a high level as long as it is precharged.

In the configuration shown in FIG. 16, the operation control signal of the sense amplifier, the shared control signal, etc. are generated by the control circuit 14 as in the above embodiment.

Further, although the case where the sense amplifier is duplicated has been described in the above-mentioned embodiment, for example, in FIG. 10, the sub sense amplifier 102 and the elements and signal lines corresponding thereto may be omitted. The configuration in that case is one in which a single sense amplifier is shared in a shared configuration, but by configuring the memory cell array section 16 as shown in FIG. 17, it is possible to realize multiple functions. Various functions can be selectively realized by the control means 14.

That is, in the memory cell array section 16 shown in FIG. 17, in addition to the plurality of memory cell arrays, the direct peripheral circuits 171, 172, 17n corresponding thereto, the common I / O selection circuit 71, and the main amplifier 72, 73. The direct peripheral circuits 171, 172, 17n are commonly connected to the main amplifiers 72, 73. That is, any output data of the direct peripheral circuits 171, 172, 17n can be amplified by the main amplifiers 72, 73. The direct peripheral circuits 171, 172, 17n, as one of which is representatively shown, include a plurality of sense amplifiers SA11, SA12, SA1n commonly connected to the common data line 74 via a column switch (not shown),
The common data line 74 is selectively connected to the main amplifier 7
And n-channel type MOS transistors Q71, Q72, Q73, Q74 for coupling to 2, 73. M
OS transistors Q71, Q72 and Q73, Q74
Are complementarily turned on / off by the common I / O selection circuit 71. That is, the MOS transistor Q
When the common data line 74 is coupled to the main amplifier 72 by turning on 71 and Q72, the MO
S transistors Q73 and Q74 are turned off. On the contrary, when the common data line 74 is coupled to the main amplifier 73 by turning on the MOS transistors Q73 and Q74, the MOS transistors Q71 and Q72 are turned off.

According to the above configuration, the main amplifiers 72, 7
Since 3 is duplicated, it is possible to access two memory cell arrays at the same time. For example, the direct peripheral circuit 171 is selectively coupled to the main amplifier 72,
While the data is being read from the memory cell array corresponding to the direct peripheral circuit 171, one of the other direct peripheral circuits 172 to 17n is connected to the main amplifier 7.
Data can be read from the memory cell array corresponding to the direct peripheral circuit by being selectively coupled to the memory cell 3. Here, the direct peripheral circuits 171 to 17n
And the connection relationship between the main amplifiers 72 and 73,
It can be pre-programmed in the control circuit 14.

FIG. 18 shows another configuration example of the I / O block 11.

The I / O block 11 shown in FIG.
Corresponding to the input buffers IB1 to IBn, synchronization circuits 12A to 12n are arranged at the subsequent stage thereof. The output terminals of the synchronizing circuits 12A-12n are coupled to the switch circuit 13 shown in FIG. The synchronization circuit 12A-
As 12n, the same configurations as those shown in FIG. 4 can be applied.

FIG. 19 shows another configuration example of the write amplifier WA in the buffer memory 17.

In the configuration shown in FIG. 12, multiplexers 31 and 32 are provided, and the write amplifier 3 is provided in the subsequent stage.
3 and the write amplifier controller 34 are arranged, but in the configuration shown in FIG. 19, the write amplifier 331 corresponding to the D-type flip-flops 351 to 35n.
-33n and the write amplifier controller 341 corresponding to the D-type flip-flop 37, the buffer memory 17
I try to place it inside. Write amplifier 331 to 3
3n and the function of the write amplifier controller 341 are
It is basically the same as that shown in FIG. In this case, since the write amplifiers 331 to 33n and the write amplifier controller 341 are arranged in the buffer memory 17, the write amplifier and its control amplifier can be omitted in the memory cell array unit 16.

FIG. 20 shows another example of the structure of the read buffer section RB in the buffer memory 17.

The read buffer unit RB includes a plurality of output buffer units RBUF1 to RBUFn and bus drivers 231 to 23n arranged at the subsequent stage thereof. The bus drivers 231 to 23n are output buffer units RB.
Data bus D based on the output signals of UF1 to RBUFn
-Provided to drive the BUS. The output buffer units RBUF1 to RBUFn have the same configuration as each other, and as one of the configurations is representatively shown, the main amplifier 3 included in the memory cell array unit 16 is shown.
D-type flip-flop 22 capable of holding data from 6
1. D-type flip-flop 222 capable of holding output data of D-type flip-flop 221, and output data of main amplifier 36, D-type flip-flop 221
Output data of the D-type flip-flop 222 and a multiplexer 223 for selectively transmitting the output data of the D-type flip-flop 222 to the bus driver 231 in the subsequent stage.

The data from the main amplifier 36 is delayed by one clock in the D-type flip-flop 221 and further delayed by one clock in the D-type flip-flop 222 at the subsequent stage. In this way, the D-type flip-flops 221 and 222
Are connected in series to delay the memory cell data, it is possible to cope with the pipeline processing of the memory cell data. The operation control information of the multiplexer 223 is programmed in the control circuit 14.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, even when semiconductor chips are developed in various types for refresh in DRAM,
According to the contents of the program memory 142 instead of the bonding master method or the master slice method, the CPU
It can be configured to be selectively settable by 141.

Further, the functions realized in the respective functional blocks in the above embodiment are examples, and various function selections are performed by the CPU 14 according to the contents of the program memory 142.
It can be selectively set by 1.

Although the MOS transistor is used in the above embodiment, a bipolar transistor may be used.

Although the program memory 142 is constituted by the EEPROM in the above embodiment, a PROM, a flash memory, a mask ROM or the like can be applied instead of the EEPROM.

In the above description, the case where the invention made by the present inventor is mainly applied to the DRAM included in the communication control system which is the background field of application has been described. The present invention can be widely applied to various semiconductor memory devices used in various electronic devices such as a type RAM or a read-only memory (ROM).

The present invention can be applied on condition that it includes at least a functional block.

[0113]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, by including the central processing unit, the operation of the functional block is controlled according to the storage information of the storage means, so that different functions can be realized by changing the storage contents of the storage means. Thereby,
It is possible to change the functions of the semiconductor memory device. Further, by improving the versatility of the semiconductor integrated circuit, it is possible to finely cover the special application requested by the user.

[Brief description of drawings]

FIG. 1 is a block diagram of an overall configuration example of a DRAM applied to a communication control system that is an embodiment of the present invention.

FIG. 2 is a block diagram of a configuration example of a main part of the communication control system.

FIG. 3 is a block diagram showing a configuration example of an I / O block included in the DRAM.

FIG. 4 is a circuit diagram of a configuration example of a synchronization circuit included in the DRAM.

FIG. 5 is an operation timing chart of the synchronization circuit.

FIG. 6 is an operation timing chart of the synchronization circuit.

FIG. 7 is an operation timing chart of the synchronization circuit.

FIG. 8 is a circuit diagram of a configuration example of a switch included in the DRAM.

FIG. 9 is a block diagram of a configuration example of an address generation unit included in the DRAM.

FIG. 10 is a circuit diagram showing a configuration example of a main part in a memory cell array part included in the DRAM.

11 is an operation timing chart of a main part of the circuit shown in FIG.

FIG. 12 is a block diagram of a configuration example of a buffer memory in the memory cell array unit.

FIG. 13 is a block diagram of another configuration example of the address generation unit.

FIG. 14 is a circuit diagram showing another configuration example of a main part of the memory cell array part.

FIG. 15 is an operation timing chart of the circuit shown in FIG.

FIG. 16 is a block diagram of another configuration example of a main part in the memory cell array part.

FIG. 17 is a block diagram of another configuration example of a main part in the memory cell array part.

FIG. 18 is a block diagram of another configuration example of the I / O block.

FIG. 19 is a block diagram of another configuration example of a write amplifier in the buffer memory.

FIG. 20 is a block diagram of another configuration example of a read amplifier in the buffer memory.

[Explanation of symbols]

 11 I / O block 12 synchronization circuit 13 switch 14 control circuit 141 CPU 142 program memory 15 address generation unit 16 memory cell array unit 17 buffer memory 21 DRAM 22 host processor 23 system bus P1 to Pn external pins

Claims (4)

[Claims] 1. A semiconductor memory device having a functional block having a plurality of functions that can be selectively realized, and a storage unit that stores the function selection information for each functional block and its operation control information, and the storage unit. A semiconductor memory device, comprising: a central processing unit that controls the operation of the functional blocks according to stored information of the means. 2. A semiconductor memory device according to claim 1, further comprising a plurality of external pins and a switch for switching a signal transmission path to the plurality of external pins under the control of the central processing unit. 3. The semiconductor memory device according to claim 1, further comprising a synchronization circuit that synchronizes an input signal with a clock under the control of the central processing unit. 4. A memory cell array unit having a plurality of memory cells arranged in an array, a first buffer capable of storing write data to the memory cell array under the control of the central processing unit, and the central processing unit. 4. A second buffer capable of storing read data from the memory cell array under the control of claim 1.
The semiconductor memory device according to the item.