JPH0821953B2 - Data transceiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION “Industrial field of application” The present invention is applicable to, for example, communication between a synchronous terminal control device and a synchronous multiplex conversion device or communication between a control device using a CPU (central processing unit) and a terminal device. The present invention relates to a transmitter / receiver for applied data transmission.

"Prior Art" FIG. 3 shows a conventional data transceiver. Send buffer
11 receives the transmission data signal 13a from the data processing unit 13 by the transmission buffer control signal 12a from the transmission control circuit 12,
After that, the transmission data signal 13a is sent to the parallel signal / serial signal conversion circuit 14. The parallel signal / serial signal conversion circuit 14 converts the parallel signal into a serial signal and sends it to the error detection signal insertion circuit 15. Error detection signal insertion circuit
The reference numeral 15 inserts an error detection signal at the end of the frame while transmitting the received signal as a transmission frame signal 15a.

On the other hand, the signal error detection circuit 16 receives the reception frame signal 17a, sends it to the serial signal / parallel signal conversion circuit 18, and if the error detection signal at the end of the frame is normal, issues the reception frame normal signal 16a and outputs the data processing unit 13a. Send to. The serial signal / parallel signal conversion circuit 18 converts the serial signal into a parallel signal and sends the parallel signal to the reception buffer 19. The reception buffer 19 sends the reception data signal 19a to the data processing unit 13 after receiving the signal according to the reception buffer control signal 21a.

The control signal identification circuit 22 is a control signal from the data processing unit 13.
It determines whether 13b is a signal for transmission control or a signal for reception control, and sends a transmission control signal 22a and a reception control signal 22b. The transmission control circuit 12 transmits a control signal for receiving the transmission data signal 13a to the transmission buffer 11 by the transmission control signal 22a and a control signal for transmitting to the parallel signal / serial signal conversion circuit 14 after completion of the transmission data signal 13a. It is sent as the control signal 12a. The reception control circuit 21 sends to the reception buffer 19 a control signal for receiving the data from the serial signal / parallel signal conversion circuit 18 and a control signal for sending it out as a reception data signal 19a as a reception buffer control signal 21a.

FIG. 4 shows the states of the transmission frame signal 15a and the reception frame signal 17a when communication is performed using the configuration example of FIG. The horizontal axis indicates the time passage, and the block above the horizontal axis indicates the signal frame. The numbers are for distinguishing the correspondence between signal frames. Thus, in the past, only half-duplex communication was possible.

In this conventional transmitter / receiver, the completion of both transmission and reception is notified by a reception frame normal signal 16a which notifies that reception is normally performed. Therefore, the next transmission data signal 13a is performed after receiving the reception data signal 19a.
Further, the transmission buffer 11 and the reception buffer 19 cannot simultaneously perform the operation of receiving data and the operation of transmitting data, respectively. With such a configuration, the data processing unit 13 itself can simultaneously perform a data transmission operation and a data reception operation, but cannot perform continuous transmission / reception, which improves the transmission / reception processing capacity and improves the communication capacity as a whole. It is not suitable for a system that attempts to increase the efficiency efficiently.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transmitter / receiver that solves the drawback that the conventional technique cannot perform continuous transmission and continuous reception and thus cannot improve the transmission efficiency.

[Means for Solving the Problems] According to the present invention, the two surfaces of the first and second transmission buffers are provided, and the first and second transmission buffers are controlled by the transmission control circuit. To receive the transmission data signal at the second transmission buffer and the parallel signal from the second transmission buffer.
Simultaneously sending a transmission data signal to the serial signal exchange circuit, and then transmitting the data of the first transmission buffer to the second transmission buffer.
High-speed transfer to the transmission buffer is performed, and after the transfer, the transmission buffer notifies the data processing unit that the transmission buffer can receive the transmission data signal. Also the first,
Two surfaces of the second reception buffer are provided, the first and second reception buffers are controlled by the reception control circuit, and the first reception buffer always receives the signal from the serial signal / parallel signal conversion circuit, and the second reception buffer. Simultaneously sending the received data signal from the reception buffer to the data processing unit, and thereafter, receiving the reception frame normal signal from the signal error detection circuit to transfer the data of the first reception buffer to the second reception buffer at high speed. After the transfer is completed, the reception interrupt signal notifies that the reception data signal can be sent from the second reception buffer to the data processing unit.

In this way, data can be continuously transmitted and received.

"Embodiment" FIG. 1 shows an embodiment of the present invention. First transmission buffer
31 is the first transmission buffer control signal 33 from the transmission control circuit 33.
The second transmission buffer 32 receives the transmission data signal 13a by a.
Send to The second transmission buffer 32 receives the data from the first transmission buffer 31 by the second transmission buffer control signal 33b,
It is sent to the parallel signal / serial signal conversion circuit 14. The parallel signal / serial signal conversion circuit 14 has a second transmission buffer 32.
The data signal from is converted into a serial signal and sent to the error detection signal insertion circuit 15. The error detection signal insertion circuit 15 inserts the error detection signal at the end of the frame while sending the signal as the transmission frame signal 15a.

The transmission control circuit 33 is provided with the transmission control signal 34a from the control signal identification circuit 34, and transmits the transmission data signal 1 to the first transmission buffer 31.
The first transmission buffer control signal 33a for receiving 3a is transmitted, and the second transmission buffer control signal 33b for transmitting data to the parallel signal / serial signal conversion circuit 14 is transmitted to the second transmission buffer 32. After the end of the respective control signals 33a, 33b, the first transmission buffer control signal 33a and the second transmission buffer control signal 33a for transferring the data from the first transmission buffer 31 to the second transmission buffer 32 are transmitted.
It issues a transmission buffer control signal 33b. In addition, the transmission control circuit 3
After the end of the data transfer between the transmission buffers 31 and 32, 3 issues a transmission interruption signal 33c to the data processing unit 13 to notify the first transmission buffer 31 that the next transmission data signal 13a can be received.

The signal error detection circuit 16 receives the reception frame signal 17a,
While being sent to the serial signal / parallel signal conversion circuit 18, if the error detection signal at the end of the frame is normal, the reception frame normal signal 16a is issued. The serial signal / parallel signal conversion circuit 18 converts the serial signal into a parallel signal and sends the parallel signal to the first reception buffer 41. The first reception buffer 41 receives data according to the first reception buffer control signal 43a from the reception control circuit 43 and sends the data to the second reception buffer 42. The second reception buffer 42 receives the second reception buffer control signal 43.
The data is received from the first reception buffer 41 by b, and the reception data signal 19a is sent to the data processing unit 13.

The reception control circuit 43 sends the first reception buffer control signal 43a for receiving the data from the serial signal / parallel signal conversion circuit 18 to the first reception buffer 41, and the second reception buffer control signal 34b from the control signal identification circuit 34 The second reception buffer control signal 43b is sent from the reception buffer 42 to send the reception data signal 19a to the data processing unit 13. After the second reception buffer 42 finishes sending the reception data signal 19a, the reception frame normal signal 16a from the signal error detection circuit 16 transfers the data from the first reception buffer 41 to the second reception buffer 42. The reception buffer control signal 43b and the first reception buffer control signal 43a are sent. Also, after the data transfer between the reception buffers 41 and 42 is completed, the reception interrupt signal 43c for notifying that the reception data signal 19a can be sent from the second reception buffer 42c.
Emit.

The control signal identification circuit 34 is a control signal from the data processing unit 13.
It discriminates whether 13b is a control signal for transmission or a control signal for reception, and sends a transmission control signal 34a to the transmission control circuit 33 and a reception control signal 34b to the reception control circuit 43.

FIG. 2 shows the states of the transmission frame signal 15a and the reception frame signal 17a when communication is performed using the configuration example of FIG. The horizontal axis indicates the time passage, and the block above the horizontal axis indicates the signal frame. The numbers are for indicating the correspondence between signal frames. As shown in this figure, continuous transmission and continuous reception are possible. With such a configuration, continuous transmission / reception can be performed, and the overall transmission efficiency can be improved.

"Effects of the Invention" As described above, the transmitting and receiving buffers are each provided on two sides, and those buffers are controlled individually at the same time.
Also, since transmission and reception can be performed continuously by issuing the transmission interruption signal and the reception interruption signal, the transmission efficiency can be maximized. Further, since each of the data transmitters / receivers can be composed of two buffers and a simple control circuit, there is an advantage that the circuit scale can be reduced.

Therefore, the data transmitter / receiver of the present invention needs to transfer a large amount of data to a plurality of devices at high speed by using a simple data transmitter / receiver, for example, a synchronous terminal station control device for line setting data of a synchronous multiplex converter. Can be applied to rewrite from.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a data transceiver according to the present invention, FIG. 2 is a diagram showing the states of a transmission frame signal and a reception frame signal in the configuration example of FIG. 1, and FIG. 3 is a conventional data transceiver. FIG. 4 is a block diagram showing the configuration of FIG. 4, and FIG. 4 is a diagram showing states of a transmission frame signal and a reception frame signal in the conventional data transceiver of FIG. 13: data processing unit, 14: parallel signal / serial signal conversion circuit, 15: error detection signal insertion circuit, 16: signal error detection circuit, 18: serial signal / parallel signal conversion circuit, 31: first
Transmission buffer, 32: Second transmission buffer, 33: Transmission control circuit, 34: Control signal identification circuit, 41: First reception buffer, 42:
Second reception buffer 43: reception control circuit.

Claims (1)

[Claims] 1. A transmission data signal from a data processing unit is received by a transmission buffer, a data signal of the transmission buffer is converted into a serial signal by a parallel signal / serial signal conversion circuit, and the serial signal is inserted into an error detection signal insertion circuit. , The error detection signal is inserted, the received frame signal is received by the signal error detection circuit, the received frame signal is converted to a parallel signal by the serial signal / parallel signal conversion circuit, and the parallel signal is converted. A data transmitter / receiver which receives a parallel signal of the reception buffer and sends the parallel signal of the reception buffer to the data processing unit as reception data is provided with a first transmission buffer and a second transmission buffer as the transmission buffer, and the transmission from the data processing unit. At the same time as receiving the data in the first transmission buffer, The transmission data signal from the second transmission buffer feed to the parallel signal / serial signal converting circuit, after which the transmission data signal of the first transmission buffer is transferred to the second transmission buffer, after the transfer completion,
A transmission control circuit for notifying the data processing unit of a transmission interrupt signal indicating that the first transmission buffer can receive the transmission data signal, wherein the first reception buffer and the second reception buffer are provided as the reception buffer; At the same time that the parallel signal from the serial signal / parallel signal is received by the first reception buffer, the reception data signal is sent from the second reception buffer to the data processing unit, and then the reception frame normal signal from the signal error detection circuit is sent. Data is transferred from the first receiving buffer to the second receiving buffer after inputting, and after the transfer is completed, a receiving interrupt signal indicating that the receiving data signal can be sent from the second receiving buffer is sent to the data processing unit. A data transceiver comprising a reception control circuit for notifying.