JPH0821917B2 - AGC circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention mainly relates to an AGC for adjusting the gain of a received intermediate frequency signal in a receiving portion of a wireless communication device.
(Auto Gain Control) circuit, especially TDMA (Time Division Multiple Acces)
s) Concerning the optimum AGC circuit for the system.

[Prior Art] A conventional AGC circuit detects the amplitude level of a received signal and suppresses the fluctuation of the signal level by adjusting the gain of the variable gain amplifier according to the detection result. It is intended to provide a constant signal. This can greatly improve the dynamic range of the receiver.

The principle of detecting the amplitude level of the received signal and adjusting the gain of the variable gain amplifier to suppress the fluctuation of the signal level to make it substantially constant will be described with reference to FIG.

In FIG. 4, the received intermediate frequency signal is input terminal 1
And is supplied to the detection circuit 3 and the variable gain amplifier 5. Detection is performed in the detection circuit 3, and the detection output of the detection circuit 3 is smoothed by the filter 4. The output of the filter 4 is supplied to the variable gain amplifier 5 as a gain control voltage.

The variable gain amplifier 5 controls the gain of the intermediate frequency signal supplied from the input terminal 1 in accordance with the gain control voltage supplied from the filter 4 so that the amplitude level of the intermediate frequency signal becomes constant and is detected from the output terminal 2. Output to a circuit (not shown). Due to this action, the detection circuit in the subsequent stage can always obtain an appropriate input signal, so that stable reception is possible.

[Problems to be Solved by the Invention] However, the conventional AGC circuit is premised on that a received signal is continuously received for a long time and that the received frequency is constant. Therefore, in a TDMA (Time Division Multiple Access) system in which signals are transmitted in bursts and frequency hopping is performed for each burst signal at a constant cycle, there is a problem that the functions cannot be fulfilled at all. The reason will be described with reference to FIG.

FIG. 3 shows burst signal length d, burst signal interval T,
An example of the burst reception signal in the case of the frequency hopping period τ (= 5T) is shown. As shown in FIGS. 3 (b) and 3 (c), the reception frequency changes in the order of f0, f2, f4, f1, f3 during the frequency hopping period τ (= 5T) (see FIG. See FIG. 3 (c). During this time, the received signal is discontinuously received as a burst signal having a burst signal length d and a burst signal interval T (Fig. 3 (a)).

As shown in FIG. 3 (c), each burst signal has a frequency different from those of the burst signals before and after it, so that the reception level is discontinuous due to the influence of frequency selective fading or the like (FIG. 3 ( See a)). If a conventional AGC circuit is used in such a system, the reception level changes discontinuously for each burst signal, so that a completely incorrect gain setting is made at the rising portion of the burst signal, etc., and it functions as an AGC circuit. I can't.

[Means for Solving the Problems] The present invention has been made in view of the above problems, and enables accurate gain control even for a received signal whose amplitude level changes discontinuously for each burst signal. In order to achieve this object, a variable gain amplifier that amplifies an input signal, a level detection circuit that detects the amplitude level of the input signal, and a delay circuit that delays the output of the level detection circuit are provided. The output of the delay circuit is configured to control the gain of the variable gain amplifier.

Further, preferably, a sample hold circuit for supplying the output of the level detection circuit as a sample hold to the delay circuit is provided.

More preferably, the delay amount of the delay circuit is set to the frequency hopping cycle of the transmission system that performs the frequency hopping at a constant cycle.

[Operation] In the AGC circuit with the above configuration, even if the amplitude level of the received signal changes discontinuously for each burst signal, the amplitude level of the burst signal one cycle before is changed by the delay circuit. By controlling the gain by supplying it to the amplifier, the gain control can be performed accurately.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an AGC circuit according to the present invention.

In FIG. 1, the received intermediate frequency signal is input terminal 1
And is supplied to the detection circuit 3 and the variable gain amplifier 5. Detection is performed in the detection circuit 3, and the detection output of the detection circuit 3 is smoothed by the filter 4. The output of the filter 4 is delayed by the delay circuit 6 and then supplied to the variable gain amplifier 5 as a gain control voltage.

The delay circuit 6 delays the output signal of the filter 4 by the frequency hopping period τ (see FIG. 3) and supplies it to the variable gain amplifier 5. That is, the current burst signal gain is 1
It will be determined by the amplitude level of the burst signal of the same frequency in the past by the frequency hopping period τ. Since the frequency hopping period τ is sufficiently short, the amplitude level of the immediately preceding burst signal of the same frequency is almost the same as the amplitude level of the burst signal of the present frequency. Therefore, the gain of the current burst signal is controlled using this burst signal level. The configuration of the delay circuit 6 will be described later with reference to FIGS. 5 and 6.

The variable gain amplifier 5 performs gain control of the intermediate frequency signal supplied from the input terminal 1 in accordance with the gain control voltage supplied from the delay circuit 6 so that the amplitude level of the intermediate frequency signal becomes constant and is detected from the output terminal 2. Output to a circuit (not shown). As a result, signals are transmitted in bursts and frequency hopping is performed for each burst signal at a fixed cycle.
The system can also implement the AGC function.

FIG. 2 is a block diagram showing another embodiment of the AGC circuit according to the present invention.

In FIG. 2, the received intermediate frequency signal is input terminal 1
And is supplied to the detection circuit 3 and the variable gain amplifier 5. Detection is performed in the detection circuit 3, and the detection output of the detection circuit 3 is smoothed by the filter 4. The output of the filter 4 is sampled and held by the sample hold circuit 7, and the held signal is supplied to the delay circuit 6. The delay circuit 6 performs a delay, and after this delay, the gain control voltage is supplied to the variable gain amplifier 5.

Delay circuit 6 is configured similarly to delay circuit 6 shown in FIG. That is, the output signal of the filter 4 is delayed by the frequency hopping period τ (see the third) to delay the variable gain amplifier 5
Supply to. The sample hold circuit 7 includes a filter 4
Is a sample and hold circuit that samples and holds the output level of the signal at every burst signal interval T.

The variable gain amplifier 5 controls the gain of the intermediate frequency signal supplied from the input terminal 1 in accordance with the gain control voltage supplied from the sample hold circuit 7 so that the amplitude level of the intermediate frequency signal becomes constant and is output from the output terminal 2. Output from a detection circuit (not shown). As a result, in addition to the effect of the embodiment of FIG. 1, the effect of keeping the gain of the variable gain amplifier 5 constant during one burst signal can be obtained.

Next, the configuration of the delay circuit 6 described above will be described with reference to FIGS. 5 and 6.

FIG. 5 is a block diagram showing an example of the configuration of the delay circuit 6. In FIG. 5, the input signal is converted into a digital signal by the A / D converter 8 in synchronization with the burst signal and supplied to the shift register array 9. The shift register array 9 delays by sequentially shifting the A / D converted burst signal, and outputs the result to the D / A converter 10. D
The / A converter 10 outputs the output signal of the shift register array 9 to D /
It is converted to A and converted back to an analog signal for output. During this period, A / D conversion in the A / D converter 8, shift in the shift register array 9, and D / A conversion in the D / A converter 10
It is performed synchronously based on the same clock signal.

FIG. 6 is a block diagram showing another example of the configuration of the delay circuit 6. In FIG. 6, the input signal is the condenser
Buffer 15, condenser 16, condenser 17, etc.
1, the buffer 12, the buffer 13, the buffer 14, etc., and the analog switch 18, the analog switch 19, the analog switch 20, etc. are sequentially transferred. In this transfer,
Two-phase clock signals φA and φB synchronized with the burst signal are used. That is, the analog switch 18, the analog switch 20, etc. are on / off controlled by the clock signal φA, and the analog switch 19 etc. are controlled by the clock signal φB.
ON / OFF control is performed by both, and both analog switch groups alternately repeat ON / OFF. By repeating this transfer, a signal delayed by a predetermined delay amount can be obtained.

According to the configuration of the delay circuit 6 shown in FIGS. 5 and 6 described above, since the circuit has a sample hold function, the sample hold circuit 7 shown in FIG. The circuit shown in the figure can be realized.

[Effects of the Invention] As described above, the present invention includes a variable gain amplifier that amplifies an input signal, a level detection circuit that detects the amplitude level of the input signal, and a delay circuit that delays the output of the level detection circuit. Since the gain of the variable gain amplifier is controlled by the output of the delay circuit, the gain control is performed by supplying the amplitude level of the burst signal one cycle before to the variable gain amplifier through the delay circuit. This makes it possible to perform accurate gain control even for a received signal whose amplitude level changes discontinuously for each burst signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an AGC circuit according to the present invention, FIG. 2 is a block diagram showing another embodiment of an AGC circuit according to the present invention, and FIG. 3 is a waveform explaining frequency hopping. FIG. 4 is a block diagram showing a conventional AGC circuit, FIG. 5 is a block diagram showing an example of the configuration of a delay circuit, and FIG. 6 is a block diagram showing another example of the configuration of a delay circuit. is there. 3 …… Detection circuit 4 …… Filter 5 …… Variable gain amplifier 6 …… Delay circuit 7 …… Sample hold circuit 8 …… A / D converter 9 …… Shift register array 10 …… D / A converter 11 ～ 14 …… Buffer 15 ～ 17 …… Condenser 18 ～ 19 …… Analog switch 20 …… Analog switch 21 ～ 22 …… Inverter

Claims (3)

[Claims] 1. A variable gain amplifier for amplifying an input signal; a level detection circuit for detecting an amplitude level of the input signal;
A delay circuit for delaying the output of the level detection circuit,
An AGC circuit, wherein the output of the delay circuit controls the gain of the variable gain amplifier. 2. The AGC circuit according to claim 1, further comprising a sample hold circuit which samples and holds the output of the level detection circuit and supplies it to the delay circuit. 3. The AGC circuit according to claim 1, wherein the delay amount of the delay circuit is a frequency hopping cycle of a transmission system which performs frequency hopping at a constant cycle.