JPH08214323A - Digital convergence device - Google Patents

Abstract

PURPOSE: To obtain an image without generating color slurring by automatically adjusting a correction current supplied to a convergence coil corresponding to the reference system or non-reference system of an input video signal. CONSTITUTION: The digital convergence correction data of m×n adjusting points are stored in a data preservation part 103, and the correction data are transferred to frame memory 104 via a data transfer control part 102. The correction data in the frame memory 104 are also used for vertical direction interpolation in a vertical interpolation circuit 112, and suplied to the convergence coils 143-148 via flip-flops 113-124, D/A conversion circuits 125-130, LPFs 131-136 and amplifier circuits 137-142. An interpolation timing is obtained in the vertical interpolation circuit 112. and also, an interpolation coefficient is generated, however, the interpolation timing and interpolation coefficient are adjusted corresponding to a video signal of reference system or non-reference system by a delay circuit 1 and a delay quantity setting circuit 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital convergence device applied to a color television receiver, an RGB three-tube projection receiver and the like.

[0002]

2. Description of the Related Art In recent years, color television receivers have become larger and wider (wider), and projection receivers have been in the limelight. This is a conventional CRT
In the case of a (cathode ray tube) type image receiver, the maximum diagonal length is about 40 inches, and if a larger size is desired,
This is because it becomes a projection receiver.

A general projection receiver is small and
R with built-in high brightness CRT (diagonal length 10 inches or less)
Video signals of corresponding three primary colors (RGB) are supplied to the GB projection tubes, and RGB video lights emitted from the respective projection tubes are superimposed on the screen to display a video. However, since the RGB projection tubes are normally installed side by side in the horizontal direction, the incident angles of the RGB image lights with respect to the screen are different, and the RGB image lights do not completely match on the screen, causing a color shift. Therefore, by supplying appropriate correction currents to the horizontal and vertical correction coils provided in the respective projection tubes, the RGB image lights are matched on the screen, and a good image without color shift is displayed. A device that generates this appropriate correction current is generally called a convergence device.

The convergence device includes an analog system and a digital system. Since the present invention is an invention relating to the digital system, the digital system will be described below.
The operation principle will be described with reference to the configuration example of the digital convergence device in FIG.

First, when the power of the projection receiver is turned on, the control microcomputer 101 starts its operation, and the correction data stored in the data storage unit 103 is transferred to the frame memory 104 to the data transfer control unit 102. Give instructions to do so. This correction data represents the convergence correction data of the convergence adjustment points arbitrarily set on the video screen. The data transfer control unit 102 writes the correction data while controlling the address of the frame memory 104 at the same time as reading the correction data from the data storage unit 103 according to the above instruction. In the selection circuit 105, the address 108 output from the data transfer control unit 102 and the address 109 output from the read address generation unit 106.
Is selected, and the data transfer unit 1 is used during the above data transfer.
02 Output address is selected. The selection control signal 107 of the selection circuit 105 is output by the data transfer control unit 102.

Through the above operation, the frame memory 104
The correction data is stored in. When the data transfer is complete,
The data transfer control unit 102 controls the selection circuit 105 to select the output address 109 of the read address generation unit 106, and the normal operation of the convergence correction signal generation is started. Read address generator 10
A horizontal synchronizing signal 110, a vertical synchronizing signal 111, and a clock (FCK) 150 are supplied to 6, and a read address is output from the read address generating unit 106 with reference to each input signal. The read address is supplied to the frame memory 104 via the selection circuit 105. The correction data is sequentially output from the frame memory 104 and supplied to the vertical interpolation circuit 112.

Since the frame memory 104 has only the correction data of arbitrary adjustment points, the correction data as it is becomes discontinuous data. Therefore, the correction data between the adjustment points in the horizontal direction is obtained by the low-pass filters 131 to 136 in the subsequent stage.
Are smoothed and made continuous, and vertical interpolation processing is performed between the adjustment points in the vertical direction. Vertical interpolation circuit 1
From 12, the correction data corresponding to each line is output, the phases are matched by the flip-flops 113 to 124, the digital data is converted to an analog signal by the D / A conversion circuits 125 to 130, and the low pass filters 131 to 136 are further supplied. Removes harmonic components. Then, the signals are supplied to the corresponding convergence coils 143-148 via the amplifier circuits 137-142.

Next, the interpolation principle will be described. FIG.
It is assumed that the adjustment points are arranged at positions on the screen as shown in FIG. 3, and the intervals between the adjustment points are a lines in the vertical direction and 1/8 horizontal scanning period in the horizontal direction.

The horizontal and vertical convergence correction data of each RGB at the m-th adjustment point [m, n] in the vertical direction and the n-th adjustment point in the horizontal direction within the field are RH.
[M, n], RV [m, n], GH [m, n], GV
Let [m, n], BH [m, n], and BV [m, n].
Further, the convergence correction data at the (m + 1) th vertical direction and the nth horizontal adjustment point [m + 1, n] is set to RH [m + 1, n], RV [m + 1, n], GH.
[M + 1, n], GV [m + 1, n], BH [m + 1,
n] and BV [m + 1, n]. On the interpolation line between the adjustment points, interpolation is performed based on the convergence correction data of the upper and lower adjustment points to obtain the convergence correction data. Interpolation point [m, x, n] on the x-th line from the adjustment point [m, n]
The convergence correction data of rh [m, x,
n], rv [m, x, n], gh [m, x, n], gv
[M, x, n], bh [m, x, n], bv [m, x,
n], rh [m, x, n] = RH [m, n] × k + RH [m +
1, n] × (1-k) rv [m, x, n] = RV [m, n] × k + RV [m +
1, n] × (1-k) gh [m, x, n] = GH [m, n] × k + GH [m +
1, n] × (1-k) gv [m, x, n] = GV [m, n] × k + GV [m +
1, n] × (1-k) bh [m, x, n] = BH [m, n] × k + BH [m +
1, n] × (1-k) bv [m, x, n] = BV [m, n] × k + BV [m +
1, n] × (1−k). However, k is a weighting constant predetermined according to the distance from both adjustment points.

The vertical interpolation circuit 112 includes a coefficient multiplier 1123,
Flip-flop 1122, coefficient unit 1124, adder 1
The coefficient generating circuit 1121 supplies the coefficients to the coefficient multipliers 1123 and 1124. The coefficient output timing from the coefficient generation circuit 1121 is obtained based on the horizontal and vertical synchronization signals.

FIG. 25 shows a coefficient generating circuit 1 for producing the above k.
The structural example of 121 is shown. The n value of the n-ary down counter 2301 and the coefficient unit 2302 is the number of scanning lines between adjustment points in the vertical direction. The n-ary down counter 2301 counts down from n to 0 by using the horizontal synchronizing signal as a clock. Therefore, k becomes 1 at the adjustment point position, and decreases by 1 / n every horizontal scanning period until it becomes 0.

Next, the timing operation of data reading from the frame memory 104 and vertical interpolation will be described. To calculate the convergence correction signal of one interpolation point, RH [m, n], RH [(m + 1), n], RV
[M, n], RV [((m + 1), GH [m, n], G
H [m + 1, n], GV [m, n], GV [m + 1,
n], BH [m, n], BH [m + 1, n], BV
It suffices if there are 12 pieces of data of [m, n] and BV [m + 1, n]. For example, the data read cycle is 1/128.
Assuming that the horizontal scanning period is ⅛ horizontal scanning period between the adjustment points in the horizontal direction, it is possible to read a maximum of 16 data, and it is possible to read 12 data necessary for calculating the interpolation point ((of FIG. 27). See a)).

FIG. 26 shows a read address generation circuit 106.
1 shows a circuit configuration. Here, the FCK 150 serves as a reference clock for reading, and is, for example, a clock that is 256 times the horizontal scanning frequency (256 fH in the figure). Counter 1405
Is an n-ary counter, and the n value is set to a value substantially equal to the number of scanning lines between adjustment points in the vertical direction. This n-ary counter represents the current vertical adjustment point position. The counter 1406 represents the adjustment point position in the horizontal direction, and if the interval between the adjustment points is 1/8 horizontal scanning cycle, it counts 8 fH as a clock. The counter 1407 counts with 128 fH as a clock. This serves as a reference for reading out the 12 correction amount data necessary for calculating the convergence correction signal of one interpolation point. An address calculation circuit 1408 calculates an address based on these three counter values. The data read by this address is supplied to the coefficient unit 1123 and the flip-flop 1122 of the vertical interpolation circuit 112.

Flip-flop 1 shown in FIG. 27 (b)
The output of 122 is supplied to the coefficient multiplier 1124 and multiplied by k.
The coefficient unit 1123 multiplies the input data by (1-k) and outputs it. Both outputs of the coefficient unit 1123 and the coefficient unit 1124 are supplied to the adder 1126 and become the output data shown in (c) of FIG. As the output of the adder 1126, valid data and dummy data (marked with * in the figure) are alternately output. Adder 112
The output of 6 is supplied to the flip-flops 113 to 118,
By latching at a predetermined timing, the multiplexed state of data can be solved. Flip-flops 113-118
27 are shown in (d) to (i) of FIG. Since the output phases of the respective flip-flops are different as shown in the figure, the respective flip-flop outputs are set to the flip-flops 119 to 124.
And all of the signal phases can be aligned by supplying the signal to the input terminal and latching again at the same timing. FIG. 27 (j)
Indicates the output timing of the flip-flops 119 to 124.

The outputs of the flip-flops 119 to 124 are supplied to the D / A conversion circuits 125 to 130 and converted from digital signals to analog signals. The outputs of the D / A conversion circuits 125-130 are low-pass filters 131-13.
6 and the higher harmonic components are removed. The convergence correction signals output from the low-pass filters 131 to 136 pass through the amplifier circuits 137 to 142 and are supplied to the corresponding convergence coils installed on the necks of the RGB projection tubes to perform convergence correction.

Consider a case where a non-standard video signal is input to a projection receiver having such a digital convergence device. Here, the non-standard video signal is a signal in which the number of horizontal scanning lines in one frame is other than the standard number, such as NTS.
In the case of C broadcasting, the standard is 525 lines, but it is assumed that this is a video signal of 540 lines or 500 lines. Such a non-standard video signal, for example, fast-forwards (rewinds) the VTR.
It occurs when it is played back.

For example, a sawtooth current and a standard sawtooth current input to a vertical deflection coil when a non-standard video signal having 540 horizontal scanning lines in one frame is input to a projection receiver for NTSC broadcasting are shown in FIG. Show.
FIG. 29 shows the two sawtooth wave currents and the correction current output from the digital convergence device in the same drawing.

As is well known, a sawtooth wave current is passed through a deflection coil to generate a magnetic field for scanning, but since the size of the screen to be scanned is fixed, the amplitude A of the sawtooth wave current is fixed.
Is also fixed, the slope of the sawtooth wave current changes in proportion to the change in time during one frame period.

On the other hand, the digital convergence device reads out correction data with reference to the vertical synchronizing signal and the horizontal synchronizing signal and performs interpolation calculation to create a correction current. Therefore, as shown in the lower part of FIG. 28, even if the number of scanning lines in one field changes, the correction current outputs exactly the same data. As can be seen from FIG. 29, the current flowing through the deflection coil is D1 in the standard time and D2 in the non-standard time at the position of the sth scan line, for example. Since the number of scanning lines is the same sth, it is the same position on the screen. The digital convergence device
Since the correction current is generated based on the correction data of the adjustment points set on the screen, the value of S1 is always output during the sth scanning line. This correction current S1 is a value that is adjusted and set so that there is no color misregistration on the screen at the time of a standard signal, so there is no problem when the current value flowing through the deflection coil is D1, but the current value is D2.
If so, color shift will naturally occur. The larger the difference between the currents in the standard time and the non-standard time, the larger the color shift. Therefore, in FIG. 29, the color shift increases as the number of scanning lines increases.

[0020]

As described in the prior art, in the case of a projection receiver using digital convergence, a color shift occurs when a non-standard video signal is displayed during fast forward (rewind) playback of a VTR. There is.

Therefore, according to the present invention, the correction current supplied to the convergence coil can be automatically adjusted according to whether the input video signal is the standard system or the non-standard system, and it is possible to contribute to obtain an image without color shift. It is an object to provide a convergence device.

[0022]

According to a first aspect of the present invention, there is provided a digital convergence apparatus comprising a storage means for storing digital convergence correction data of m × n adjustment points arbitrarily set on a screen, and the storage means. Reading control means for controlling reading from the means, computing means for computing digital convergence correction data between the adjustment points arranged in the vertical direction from a plurality of digital convergence correction data read from the storage means, and output of the computing means Digital-to-analog conversion means for analogizing data, low-pass filter for smoothing output data of the digital-to-analog conversion means, counter for counting horizontal synchronizing signals in one field period, and difference between output data of the counter and reference data The difference means and the output data of the difference means And 1/2 means that / 2, the 1 /
And a delay means for delaying the vertical synchronizing signal according to the output data of the two means.

According to a third aspect of the present invention, there is provided a digital convergence device, which stores a digital convergence correction data of m × n adjustment points arbitrarily set on a screen, and controls reading from the storage means. Read control means, computing means for computing digital convergence correction data between the adjustment points arranged in the vertical direction from a plurality of digital convergence correction data read from the storage means, and analog for analogizing output data of the computing means. Conversion means, a low-pass filter for smoothing the output data of the analog conversion means,
A counter that counts the horizontal sync signal in one field period,
A delay storage unit that stores a delay amount, a delay amount read control unit that controls reading from the delay amount storage unit according to output data of the counter, and a vertical synchronization signal according to output data of the delay amount storage unit. And a delay means for delaying.

According to a fifth aspect of the present invention, there is provided a digital convergence device comprising a storage means for storing digital convergence correction data of m × n adjustment points arbitrarily set on the screen, and a counter 1 for counting horizontal synchronizing signals. The reading control means for controlling reading from the storage means, the counter 2 for counting the horizontal synchronizing signal, and the coefficient generation means for outputting data according to the distance to the adjustment point, and the reading means from the storage means Computation means for computing the digital convergence correction data between the adjustment points arranged in the vertical direction from a plurality of digital convergence correction data based on the coefficient output from the coefficient generation means, and analog conversion for analogizing the output data of the calculation means. Means and a low-pass filter for smoothing the output data of the analog conversion means. A counter 3, a counter 3 for counting horizontal synchronization signals in one field period, setting data storage means for outputting setting data stored according to the data of the counter 3, and count control according to the data of the setting data storage means. It is provided with a count control signal generating means for generating the signal 1 and the count control signal 2.

A digital convergence apparatus according to claim 8 of the present invention comprises a storage means for storing digital convergence correction data of m × n adjustment points arbitrarily set on the screen, and a counter 1 for counting horizontal synchronizing signals. The reading control means for controlling reading from the storage means, the counter 2 for counting the horizontal synchronizing signal, and the coefficient generation means for outputting data according to the distance to the adjustment point, and the reading means from the storage means Computation means for computing the digital convergence correction data between the adjustment points arranged in the vertical direction from a plurality of digital convergence correction data based on the coefficient output from the coefficient generation means, and analog conversion for analogizing the output data of the calculation means. Means and a low-pass filter for smoothing the output data of the analog conversion means. And filter, a counter 3 for counting the horizontal synchronizing signal of one field period is for and a count control signal generating means for generating a count control signal in accordance with data of the counter 3.

According to a tenth aspect of the present invention, there is provided a digital convergence apparatus in which a storage means for storing digital convergence correction data of m × n adjustment points arbitrarily set on a screen and a reading operation from the storage means are controlled. Read control means, a counter for counting horizontal synchronization signals in one field period, a coefficient storage means for storing coefficients, and a coefficient read control means for controlling the reading of the coefficient storage means corresponding to the data of the counter. Between the digital convergence correction data read from the storage means, i-multiplying means for multiplying the output data of the coefficient storage means, and between the plurality of adjustment points arranged in the vertical direction from the plurality of digital convergence-correction data output from the i-folding means. Calculating means for calculating digital convergence correction data; Analog converting means for analog of the output data of stage, the output data of said analog converting means is obtained by including a low pass filter for smoothing.

[0027]

According to the first and third aspects of the present invention, the convergence correction current is equal to a value corresponding to 1/2 of the difference between the number of scanning lines in the standard video signal and the number of scanning lines in the non-standard video signal. By shifting the phase of, the color shift at the center of the screen can be eliminated and a video display in which the color shift is inconspicuous can be obtained.

In claims 5 and 10 of the present invention, mx
The correction current is non-standard by controlling the read control means for controlling the reading from the storage means for storing the digital convergence correction data of the n adjustment points and the coefficient generating means for outputting the data according to the distance from the adjustment point. By expanding or contracting in response to an increase or decrease in the number of scanning lines at the time of a video signal, color misregistration can be eliminated and an image display without color misregistration can be obtained.

In the eighth aspect of the present invention, the correction data output from the storage means for storing the digital convergence correction data of the m × n adjustment points corresponds to the increase / decrease in the number of scanning lines in the non-standard video signal. By multiplying by n, it is possible to obtain a video display without color shift.

[0030]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the present invention. The difference between this embodiment and the conventional example is that a delay circuit 1 for delaying the synchronizing signal by the delay amount set by the delay amount setting circuit 2 is added to the line of the vertical synchronizing signal 111. The delay circuit 1 is, for example, a counter with a load enable, and uses the input vertical synchronizing signal 111 as a load signal to load the value of the delay amount setting circuit 2 as an initial value and counts from the initial value in synchronization with the horizontal synchronizing signal 110. It is a circuit that performs an up operation and outputs a signal at a set value (for example, 2 ¹⁰ (1024) in the case of a 10-bit binary counter). In this case, the length from the initial value to the set value is the delay amount.

FIG. 2 shows a concrete configuration example of the delay amount setting circuit 2. A counter 71 in FIG. 2 is a counter that counts the number of horizontal scanning lines in one field, and is cleared by the vertical synchronizing signal to count the horizontal synchronizing signal. A difference between the count value and the standard scanning line held in the standard scanning line number holding unit 72 is taken by the -1 multiplication circuit 73 and the addition circuit 74. This difference tells whether the current video signal is standard. For example, the value of the counter 71 is 25
0 and the value of the standard scanning line holding unit is 262, the adding circuit 7
The output of 4 is -12. Next, this value is 1/2 circuit 7
The value becomes -6 in 5, and the value held in the reference value holding unit 76 is added by the adding circuit 77 and input to the delay circuit 1.

There is a case where the output of the adder circuit 74 has a negative value as in the above-mentioned example, but the fact that the delay amount has a negative value means that it is advanced in time, which is physically impossible.
Therefore, for example, if a value delayed by one field is set in the reference value holding unit 76, the apparent time can be advanced.

When the vertical synchronizing signal is delayed by half the difference from the number of standard scanning lines in this way, the start position of the read address generating circuit 106 operating based on the vertical synchronizing signal is also delayed in synchronization. To do. As a result, the correction current is
become that way.

In FIG. 3, T1 and T2 represent the time axis centers of the sawtooth current in standard time and non-standard time, respectively. For example, when the number of scanning lines increases by nH in the non-standard time, the deflection coil current in the first scanning line T1 is D3 in the standard time, D4 in the non-standard time, and the correction current is S2. As described in the conventional example, since the same correction current is applied to different sawtooth wave current values, color misregistration occurs in the scanning line portion of T1.

However, the correction current according to this embodiment is n
Since the phase is delayed by / 2, the correction current is S2 with respect to the sawtooth wave current value D3 in the scanning line T2. Since this value is the same as the value when there is no color shift in standard time, the correction current according to this embodiment does not cause color shift in the scanning line T2.

In the conventional example, since the color shift increases as the number of scanning lines increases, the color shift in the upper part of the screen is the smallest and the color shift in the lower part becomes larger. However, in the present invention, as described above, the scanning line T at the substantially center of the screen is displayed.
There is no color shift at the position of 2, and the color shift increases as the distance from T2 increases. Generally, when a person views an image, he / she tends to see the center of the screen as the main point of view, and therefore, in the case of an image having no color shift in the vicinity of the center as in this embodiment, the impression of the image quality is quite good. Regarding the degree of color misregistration, conventionally, the color misregistration gradually increases from the point where there is no color misregistration to the position where the number of scanning lines is advanced by one field length. Since the number of scanning lines changes only by the amount, the amount of color misregistration can be reduced.

FIG. 4 shows a second embodiment of the present invention. The overall configuration is almost the same as that of the first embodiment,
The delay amount setting circuit 3 is different. FIG. 5 shows a configuration example of the delay amount setting circuit 3. 5, the same parts as those in FIG. 2 have the same numbers. In the second embodiment, an address calculated based on the scanning line numerical value for one field period is input to the delay amount storage circuit 91, and the corresponding value is output to the delay circuit 1. For example, in the NTSC broadcast, the delay amount storage circuit 91
Is a ROM, for example, when the count value of the counter 71 is 262 of the standard time, the address conversion circuit 92 outputs the address A1 and selects the stored delay amount t1. When the count value is 270, the address A2 is set to the address A2. The stored delay amount t2 is output. If the relationship between the stored delay amount and the count value is set to be the same as the count value and the output value of the delay amount setting circuit 2 in the first embodiment, the same effect as in the first embodiment can be obtained. It will be. Further, the same delay amount t3 is set for counter values of 260 to 263, and the delay amount t4 is set for 264 to 267. The number is m in the nth field,
In the (n + 1) th field, it is possible to reduce a problem when a signal having a different number of scanning lines is input for each field like (m + α) lines. This is because when a signal having a different number of scanning lines for each field is input in the first embodiment, the delay amount changes for each field, that is, the delay amount of the correction current changes, and the scanning line position without color misregistration (FIG. 3). T2) changes. If the color shift position slightly changes in the center of the screen,
There is a possibility that it can be recognized by the human eye, and this may lead to deterioration of image quality.

Therefore, as described above, the same delay amount is used for each counter value 4 to reduce the change in the delay amount. The counter 71 is a binary counter, and the address conversion circuit 92 shifts the counter value to the right by 2 bits (4 times).
The number of stored values of the delay amount storage circuit 91 is 1
There is also an effect that can be reduced to / 4.

As described above, the deterioration of the image quality when a signal having a different number of scanning lines is input for each field is reduced as in the second embodiment, and as shown in FIGS. 6 and 7. The continuous comparison circuit 1001 may be provided. The delay amount setting circuit of FIG. 6 is equivalent to the counter 7 shown in FIG.
1 is an example in which the continuous comparison circuit 1001 is provided between the adder circuit 74 and the adder circuit 74. The delay amount setting circuit of FIG.
This is an example in which 001 is provided.

FIG. 8 shows a specific structure of the continuous comparison circuit 1001. In the figure, reference numerals 1201 to 1204 denote latch circuits. In this circuit, the counter value input from the counter 71 is sequentially latched by the vertical synchronizing signal, and the comparison circuit 1205 compares the counter values for four vertical scanning periods, for example. If the comparison circuit 1205 outputs only when the counter values of the four vertical scanning periods are the same, the output of the latch circuit 1204 changes only when the counter values of the four vertical scanning periods are the same. By providing such a continuous comparison circuit 1205, the delay amount can be stabilized and the deterioration of image quality can be further reduced.

FIG. 9 shows a third embodiment. Also, FIG.
The read address generating circuit 106 has a configuration example shown in FIG.
1 shows a configuration example of the coefficient generation circuit 1121, and FIG. 12 shows a configuration example of the count control circuit 6. The n-ary counter 7 of the read address generation circuit 106 and the n-ary down counter 8 of the coefficient generation circuit 5 perform a counting operation when the count enable signal is at a high level, and hold a current count value when the count enable signal is at a low level. To do. In the count control circuit 6 that generates this count enable signal, the counter 9 counts the number of scanning lines in one field, and the storage circuit 10 outputs the corresponding value. If the value output from the storage circuit 10 is, for example, a positive value, the m-ary counter 11 operates, and if the value is a negative value, the m-ary counter 14 operates.
For example, when a non-standard signal of 270 scanning lines in one field is input in NTSC broadcasting, the value of the counter 9 becomes 270,
The storage circuit 10 outputs the value stored corresponding to 270. This value is, for example, a value obtained by dividing the number of standard scanning lines 262 by the difference 8 between the standard number of scanning lines 262 and the counted number of scanning lines, and rounding down the decimal point, that is, 262 / (270-262) ≈32. . This value becomes the m value of the m-ary counter 11, and sets the count enable signal to the low level once every 32 times of the horizontal synchronizing signal (see a in FIG. 13). In this way, when the number of scanning lines in one field exceeds the number of standard scanning lines, the count enable signal is controlled so that the outputs of the read address generating circuit 106 and the coefficient generating circuit 1121 are 2 or more.
Since the scanning lines have the same value, the correction current output from the digital convergence device also has the same value. If the positions where the two scanning lines have the same value are increased by the increased number of scanning lines, the correction current has a characteristic in which the time axis is extended. This state is shown in FIG.

As is apparent from FIG. 14, since the correction current of this embodiment also expands in proportion to the sawtooth current at the time of the non-standard signal, the relation between the sawtooth wave current and the correction current is the same when there is no color shift. It remains a relationship. Therefore, even when the non-standard video signal is displayed, the color shift does not occur.

For example, one field 250 in NTSC broadcasting
When the non-standard signal of the scanning line is input, the value of the counter 9 becomes 250, and the storage circuit 10 outputs the value stored corresponding to 250. This value is, for example, 2 standard scan lines.
The value obtained by dividing the standard scanning line number 262 by the difference between the number of scanning lines and the counted number of scanning lines -12 by 12 is rounded down to the decimal point, that is, 262 / (250-262) ≈21. The absolute value of this value becomes the m value of the m-ary counter 14, and sets the count clock signal to the high level once every 21 times of the horizontal synchronization signal (see b in FIG. 13). This high level period is set so that it immediately follows the horizontal synchronizing signal and becomes a horizontal blanking period. When the number of scanning lines in one field is smaller than the standard number of scanning lines in this way, the outputs of the read address generating circuit 106 and the coefficient generating circuit 1121 are binary advanced by one scanning line by controlling the count clock signal. The same applies to the correction current output from the digital convergence device. The correction current has a characteristic in which the time axis is contracted by increasing the binary-advanced position by the amount corresponding to the decrease in the number of scanning lines. Similarly to the case where the number of scanning lines is increased, the correction current of this embodiment also contracts in proportion to the sawtooth current at the time of the non-standard signal.
It remains as it was when there was no color shift. Therefore, even when the non-standard video signal is displayed, the color shift does not occur. However, as shown in FIG. 15, the correction current is not continuous when the number of scanning lines increases or decreases, but
Since it is made continuous by a low-pass filter, there is usually no problem. However, this may be a problem in the case of high-definition video such as high-definition broadcasting. In such a case, it is possible to reduce the deterioration of the image by changing the position for each field without fixing the position that is not continuous.

Further, in the third embodiment, the continuous comparison circuit described in the second embodiment (see FIG. 7) is provided between the counter 9 and the storage circuit 10.
By disposing (see), it is possible to reduce image deterioration when the number of scanning lines differs between fields.

FIG. 16 shows a fourth embodiment. In this embodiment, a data conversion circuit 15 is provided as compared with the conventional configuration, and the output of the frame memory 104 is converted into data and supplied to the vertical interpolation circuit 112. The other parts have the same structure as the conventional device.

A configuration example of the data conversion circuit 15 in the figure is shown in FIG.
7 shows. In FIG. 17, the counter 16 is a counter that counts the number of scanning lines in one field. The address generation circuit 17 also generates an address for reading the value stored in the storage circuit 18 (for example, ROM). This address includes information on the number of scanning lines in one field period and the vertical position currently being scanned. For example, if five vertical adjustment points are installed, NTSC
During broadcasting, the number of scanning lines at the adjustment point in one field period is 262.5 / 5≈52. On the basis of the number of scanning lines between the adjustment points, a 52-ary counter (not shown) is installed in the address generation circuit 17, which provides information on which adjustment point the current scanning position is. appear. Therefore, for example, if the address is 12 bits, the 52-ary counter value is set to the lower 3 bits, and the counter 16 value is set to the upper 9 bits to obtain an address including the number of scanning lines in one field period and the current scanning position. Become. Based on such an address,
The storage circuit 18 outputs the magnification kt for the coefficient unit 19, and the correction data is multiplied by kt.

The magnification data stored in the storage circuit 18 will be described. For example, consider a case where five adjustment points in the vertical direction (P1, P2, P3, P4, P5 from the top) are installed. At present, the number of scanning lines in one field period is 270, and magnifications kt = kp1 and P at scanning line positions above P1.
At the scanning line position between 1 and P2, the magnification kt = kp12, and similarly, the magnifications kt are kp23, kp34, and kp4.
5 and kp5, the relations of the respective magnifications are kp1 <kp12 <kp23 <kp34 <kp45 <kp5, and the correction current is set so as not to have a color shift with the sawtooth current in the standard time. This setting is
It can be actually obtained from experiments.

FIG. 1 shows the correction current when the above setting is made.
8 shows. Although there is a correction current only up to the number of scanning lines for one field at the time of a standard signal, no more scanning lines are displayed on the screen, so there is no problem. In this way, the frame memory 1
By multiplying the correction data read from 04 by kt according to the increase / decrease in the number of scanning lines, it is possible to obtain an image without color shift.

Further, by installing the continuous comparison circuit (see FIG. 7) described in the second embodiment between the counter 16 and the address generation circuit 17 in FIG. 17, when the number of scanning lines differs between fields. Image deterioration can be reduced.

FIG. 19 shows a fifth embodiment. In this embodiment, an n-value control circuit 20 is provided as compared with the conventional device, and the output of the n-value control circuit 20 controls the read address generation circuit 106 and the coefficient generation circuit 1121.

FIG. 20 shows an example of the configuration of the read address generating circuit 106 in FIG. 2, and FIG. 2 shows an example of the configuration of the coefficient generating circuit 1121.
FIG. 22 shows an example of the configuration of the n-value control circuit 20. The n value of the n-ary counter 23 of the read address generation circuit 106 and the n-ary down counter 24 of the coefficient generation circuit 1121 is usually the number of scanning lines between adjustment points in the vertical direction as described in the conventional example, and is 1 field. The same value is obtained even if the number of scanning lines changes. In this embodiment, this n value is changed according to the number of scanning lines. Specifically, the counter 26 in the n-value control circuit 20 counts the number of scanning lines in one field, and the storage circuit 27 outputs a value according to the count value. For example, assuming that the number of adjustment points in the vertical direction is 5, when the standard number of scanning lines is 262 in NTSC broadcasting, the n value is set to 52. Therefore, the read address generation circuit 10
The n-ary counter 23 of No. 6 and the n-ary down counter 24 of the coefficient generating circuit 1121 each become a 52-ary counter and operate. When the number of scanning lines becomes 272, the n value is set to 5
4, when the number of scanning lines is 252, the n value is changed to 50. Since the n-ary counter 23 of the read address generating circuit 106 is a counter indicating the position of the adjustment point in the vertical direction, for example, the horizontal synchronization signal is counted 52 times from the time when one adjustment point is read at the time of the standard number of scanning lines to the next adjustment point. To do. Similarly, the coefficient generation circuit 1121 includes the n-ary down counter 24 and the coefficient unit 2.
Depending on 5, the value from 1 to 0 is output 52 times. This means that when the number of scanning lines is 272, the n value is 54, and 54 times is 1 cycle. That is, the number of scanning lines between the adjustment points is 2
This means that the number of books has increased. At this time, the correction current is the same as that in FIG. 14 shown in the third embodiment. However, in the third embodiment, the low-pass filter is used for the continuous operation, but in the present embodiment, the output of the coefficient generation circuit 1121 is continuously changed corresponding to the increased scanning lines, so that the vertical interpolation circuit 112 is continuously operated. The value is output and the correction current also becomes a continuous value. Also n
Since the value is an integer value, it is the same 52 when the number of scanning lines is 262 and 260, for example. If it is left as it is, a slight color shift occurs. Therefore, the above problem can be solved by operating the control circuit 28 in the n-value control circuit 20 to increase or decrease the n value by 1 only between certain adjustment points. For example, considering the case of the number of scanning lines 262 in the standard time as a reference, in the case of the scanning line 260, among the five adjustment points, two may be 51 scanning lines and three may be 52 scanning lines. By doing so, it is possible to reduce color shift when a non-standard video signal is input.

Further, in the fifth embodiment, the continuous comparison circuit (see FIG. 8) described in the second embodiment is installed between the counter 26 and the storage circuit 27 in FIG. 22, so that the number of scanning lines between fields is increased. When the values are different, the deterioration of the image can be reduced.

[0053]

As described above, according to the first and second embodiments of the present invention, the non-standard video signal in which the number of scanning lines in one field period is increased or decreased from the standard video signal is input in the digital convergence apparatus. The color misregistration that occurs in some cases can be significantly reduced at the center of the screen. In general, people tend to look at the center of the screen as a center. Therefore, if there is no color shift in the center of the screen, the overall image quality of the video screen will be good.

Further, according to the third, fourth and fifth embodiments of the present invention, it occurs when a non-standard video signal in which the number of scanning lines in one field period is increased or decreased from the standard video signal is input in the digital convergence apparatus. Color shift can be significantly reduced on the entire screen.

[Brief description of drawings]

FIG. 1 is a diagram showing a digital convergence device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a delay amount setting circuit of FIG.

3 is a correction current characteristic diagram shown for explaining the operation of the apparatus of FIG.

FIG. 4 is a diagram showing a second embodiment of the present invention.

5 is a diagram showing an example of a delay amount setting circuit in FIG.

FIG. 6 is a diagram showing still another example of the delay amount setting circuit.

FIG. 7 is a diagram showing still another example of the delay amount setting circuit.

8 is a diagram showing the continuous comparison circuit of FIG. 7. FIG.

FIG. 9 is a diagram showing a third embodiment of the present invention.

10 is a diagram showing an example of a read address generation circuit in FIG.

11 is a diagram showing an example of the coefficient generation circuit of FIG.

12 is a diagram showing an example of a count control circuit in FIG.

13 is a timing diagram shown for explaining the operation of the apparatus of FIG.

14 is a correction current characteristic diagram shown for explaining an operation example of the apparatus of FIG.

FIG. 15 is a correction current characteristic diagram shown to explain another operation example of the apparatus of FIG.

FIG. 16 is a diagram showing a fourth embodiment of the present invention.

17 is a diagram showing an example of the data conversion circuit of FIG.

FIG. 18 is a correction current characteristic diagram shown for explaining an operation example of the apparatus of FIG. 16.

FIG. 19 is a diagram showing a fifth embodiment of the present invention.

20 is a diagram showing an example of a read address generation circuit of FIG.

21 is a diagram showing an example of the coefficient generation circuit of FIG.

22 is a diagram showing an example of an n-value control circuit in FIG.

FIG. 23 is a diagram showing a conventional digital convergence device.

FIG. 24 is a diagram showing an example of adjusting position setting on the screen.

FIG. 25 is a diagram showing an example of the coefficient generation circuit of FIG. 23.

FIG. 26 is a diagram showing an example of a read address generation circuit of FIG. 23.

FIG. 27 is a diagram showing an example of a read timing of correction data.

FIG. 28 is a characteristic diagram of a sawtooth current and a convergence current of a conventional example.

FIG. 29 is a characteristic diagram of a sawtooth wave current and a convergence correction current in a conventional example.

[Explanation of symbols]

1 ... Delay circuit, 2, 3 ... Delay amount setting circuit, 6 ... Count control circuit, 15 ... Data conversion circuit, 20 ... N-value control circuit, 101 ... Control microcomputer, 102 ... Data transfer control section, 103 ... Data storage Part, 104 ... Frame memory,
105 ... Selection circuit, 106 ... Read address generation circuit, 112 ... Vertical interpolation circuit, 113-118, 119-
124 ... Flip-flop, 125-130 ... D / A conversion circuit, 131-136 ... Low-pass filter, 137-
142 ... Amplification circuit, 143-148 ... Convergence coil.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masanori Fujiwara, Masanori Fujiwara, 1-9-2, Harara-cho, Fukaya-shi, Saitama, Fukaya Plant, Toshiba Corp. (72) Hisayuki Mihara, 3-3-9, Shimbashi, Minato-ku, Tokyo Toshiba Abu E. Ltd. (72) Inventor Toshio Obayashi 1-9-2 Hararacho, Fukaya City, Saitama Prefecture Fukaya Factory, Toshiba Corporation

Claims (11)

[Claims] 1. A storage unit for storing digital convergence correction data of m × n adjustment points arbitrarily set on a screen, and a read timing signal is created based on a horizontal synchronizing signal, a vertical synchronizing signal, and a clock. A read control unit that controls reading of the digital convergence correction data from the storage unit, and a digital convergence interpolation between the adjustment points arranged in the vertical direction by performing arithmetic processing on a plurality of digital convergence correction data read from the storage unit. An arithmetic means for obtaining correction data, a digital-analog conversion means for converting the output correction data from the arithmetic means into an analog signal, a low-pass filter for smoothing the output signal of the digital-analog conversion means, and a horizontal synchronization signal for one field period. A counter that counts Difference means for calculating the difference between the output data of the input data and the reference data, ½ means for halving the output data of the difference means, and input to the read control means according to the output data of the ½ means. And a delay means for delaying the vertical synchronization signal. 2. A continuous comparison means for outputting data to the difference means when the count data of the counter is the same number of k field periods is further provided.
The described digital convergence device. 3. A storage means for storing digital convergence correction data of m × n adjustment points arbitrarily set on the screen, and a read timing signal is created based on a horizontal synchronizing signal, a vertical synchronizing signal and a clock. A read control unit that controls reading of the digital convergence correction data from the storage unit, and a digital convergence interpolation between the adjustment points arranged in the vertical direction by performing arithmetic processing on a plurality of digital convergence correction data read from the storage unit. An arithmetic means for obtaining correction data; a digital-analog conversion means for converting the output data of the arithmetic means into an analog signal; a low-pass filter for smoothing the output signal of the digital-analog conversion means; and the horizontal synchronization signal for one field period. Count counter and store delay amount The delay amount storage means, the delay amount read control means for controlling the reading from the delay amount storage means according to the output data of the counter, and the input to the read control means according to the output data of the delay amount storage means. A digital convergence device comprising: a delay unit that delays the vertical synchronization signal. 4. The digital convergence device according to claim 3, further comprising a continuous comparison means for outputting the delay amount read control means data when the count data of the counter is the same number in the k field period. 5. A storage means for storing digital convergence correction data of m × n adjustment points arbitrarily set on the screen, and a first means for clearing the vertical synchronization signal and counting the horizontal synchronization signal.
Read counter means for outputting an address for reading the digital convergence correction data from the storage means, and a second counter for counting the horizontal synchronization signal, and the count value is processed to process the count value. Adjustment points,
Coefficient generating means for outputting data according to the distance to the current line, and arithmetic processing of the plurality of digital convergence correction data read from the storage means to obtain digital convergence interpolation correction data between the adjustment points arranged in the vertical direction. In the case of obtaining, the calculating means obtained by calculating based on the coefficient output from the coefficient generating means, the digital-analog converting means for converting the output correction data of the calculating means into analog, and the output signal of the digital-analog converting means are smoothed. A low-pass filter, a third counter that counts the horizontal synchronizing signal in one field period, a setting data storage unit that outputs setting data stored in advance according to count data of the third counter, According to the setting data output from the setting data storage means, the first counting system Signal, and count control signal generation means for generating a second count control signal, wherein the second counter of the coefficient generation means and the first counter of the read control means include the first count control signal. The digital convergence device, wherein the count operation is controlled to continue counting or hold a count value by the second count control signal. 6. The count data of the third counter is k
6. The digital convergence apparatus according to claim 5, further comprising a continuous comparison unit that outputs data to the setting data storage unit when the number of field periods is the same. 7. The digital convergence device according to claim 5, further comprising a count control signal generating means for changing the generation timing of each of the first count control signal and the second count control signal for each field. 8. A storage means for storing digital convergence correction data of m × n adjustment points arbitrarily set on the screen, and a first means for counting horizontal synchronization signals which is cleared by a vertical synchronization signal.
Read counter means for outputting an address for reading the digital convergence correction data from the storage means, and a second counter for counting the horizontal synchronization signal, and the count value is processed to process the count value. Adjustment points,
Coefficient generating means for outputting data according to the distance to the current line, and arithmetic processing of the plurality of digital convergence correction data read from the storage means to obtain digital convergence interpolation correction data between the adjustment points arranged in the vertical direction. In the case of obtaining, the calculating means obtained by calculating based on the coefficient output from the coefficient generating means, the digital-analog converting means for converting the output correction data of the calculating means into analog, and the output signal of the digital-analog converting means are smoothed. A low-pass filter, a third counter that counts the horizontal synchronizing signal in one field period, a setting data storage unit that outputs setting data stored in advance according to count data of the third counter, Count number control according to the setting data output from the setting data storage means A count number control signal generating means for generating a number, and the count number of the second counter of the coefficient generating means and the first counter of the read control means is controlled by the count number control signal. A digital convergence device. 9. The count data of the third counter is k.
9. The digital convergence device according to claim 8, further comprising continuous comparison means for giving output data to the setting data storage means when the number of field periods is the same. 10. A correction data storage unit for storing digital convergence correction data of m × n adjustment points arbitrarily set on a screen, and a read control unit for reading the digital convergence correction data from the storage unit. A counter for counting horizontal synchronization signals in one field period, a coefficient storage means for storing coefficients, a coefficient read control means for reading out the coefficient of the coefficient storage means corresponding to the data of the counter, and the correction data storage I multiplication means for multiplying the digital convergence correction data read from the means by a coefficient according to the coefficient output from the coefficient storage means, and a plurality of digital convergence correction data output from the i multiplication means. , Digital convergence compensation between the adjustment points aligned vertically Digital comprising: arithmetic means for arithmetically operating the correction data; digital-analog conversion means for analog-converting the output data of the arithmetic means; and a low-pass filter for smoothing the output signal of the digital-analog conversion means. Convergence device. 11. The digital convergence device according to claim 10, further comprising a continuous comparison means for outputting the data to the coefficient read control means when the count data of the counter has the same number of k field periods.