JPH08213541A - Semiconductor device - Google Patents

Abstract

PURPOSE: To enhance semiconductor chips provided on a module board in mounting density by a method wherein bump electrodes of different functions are provided so as not to confront each other, and the semiconductor chips connected to different leads are formed into groups. CONSTITUTION: Eight semiconductor chips 4A and 4B and eight semiconductor chips 4C and 4D are mounted on the front and rear of a module board 1 respectively. The semiconductor chips 4A to 4D are made to form an SRAM, and the surfaces of the semiconductor chips where semiconductor elements or wirings are provided are molded with silicone rubber or resin 7. Bump electrodes 6 of solder, Au or the like are provided on the semiconductor chips 4A to 4D respectively, and leads 5A to 5D are connected to the bump electrodes 6 through a TAB method. The semiconductor chip 4A is stacked on the semiconductor chip 4B, the leads 5A and 5B of them of the same function are connected together with solder. On the rear side of the module board 1, the semiconductor chips 4C and 4D and leads 5C and 5D are disposed the same as above. A semiconductor chip of different function from the other semiconductor chips is a decoder 3, and one selected out of eight semiconductor chips is made to serve as a decoder on both the front and rear of a module board.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, it relates to a semiconductor device formed by modularizing a plurality of semiconductor chips and mounting them on a module substrate.

[0002]

2. Description of the Related Art A semiconductor device having a high packaging density, which is formed by mounting a plurality of packages in which semiconductor chips are encapsulated on a mounting substrate (module substrate), is published by Nikkei McGraw-Hill Co., Nikkei Electronics Supplement, no. 2 “Microdevices” p150.

[0003]

The present inventor has found the following problems as a result of examining the semiconductor device.

Since it is difficult to reduce the size of the package itself, it is difficult to increase the packaging density of semiconductor chips on the module substrate.

An object of the present invention is to increase the mounting density of a semiconductor device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

That is, the bump electrode of the semiconductor chip is connected to the lead, and a plurality of semiconductor chips having the lead are connected to the wiring of the module substrate to form a semiconductor device.

According to the above-mentioned means, since the semiconductor chip is not sealed with the package, the mounting density of the semiconductor chip on the module substrate can be increased.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) Hereinafter, Embodiment 1 of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a side view showing a schematic configuration of the semiconductor device, and FIG. 3 is a diagram showing the semiconductor device. It is the front view which showed schematic structure.

In FIG. 1 to FIG. 3, reference numeral 1 denotes a module substrate formed by laminating a plurality of ceramic layers and wiring layers made of laminated ceramics, and eight semiconductor chips 4A, 4B, respectively on the front surface and the back surface. It is equipped with 4C and 4D. The semiconductor chips 4A, 4B, 4C and 4D are
For example, a static RAM is configured, and it is not sealed by a package made of ceramic, resin, or the like, and has a structure in which the surface on which the semiconductor element or wiring is provided is molded with the resin 7. There is.

Each of the semiconductor chips 4A, 4B, 4C and 4D is provided with a bump electrode 6 made of solder, gold or the like, and the bump electrode 6 is provided with TAB (Tape Automated).
The leads 5A, 5B, 5C, and 5D are connected by bonding. The semiconductor chip 4A is stacked on the semiconductor chip 4B by connecting the respective leads 5A to the leads 5B of the semiconductor chip 4B by, for example, soldering. That is, for example, the lead 5A for inputting an address signal to the semiconductor chip 4A is connected to the lead 5B for inputting an address signal to the semiconductor chip 4B.

Similarly, the lead 5A for inputting / outputting data of the semiconductor chip 4A is connected to the lead 5B for inputting / outputting data of the semiconductor chip 4B. That is, in each lead 5A and lead 5B,
Those having the same function are connected by, for example, solder. Each of the leads 5B is connected to the decoder 3 and the leads 2 through wiring (not shown) in the module substrate 1.
Connected to

However, the lead 5A ₁ for inputting the chip select signal to the semiconductor chip 4A is the lead 5B for inputting the chip select signal to the semiconductor chip 4B.
_It is connected to the lead 3A of the decoder 3 without being connected to ₁ . The lead 5B ₁ is connected to a lead 3A different from the lead 3A to which the lead 5A ₁ is connected. Eight semiconductor chips 4A, 4B by the decoder 3
One semiconductor chip 4A or 4B is selected from among the above.

Each lead 5D of the semiconductor chip 4D
The semiconductor chip 4D is mounted on the semiconductor chip 4C by connecting to the lead 5C of the semiconductor chip 4C by, for example, soldering. Each lead 5C is connected to the decoder 3 or the lead 2 through the wiring in the module substrate 1.

However, the lead 5D ₁ for inputting the chip select signal of the semiconductor chip 4D is the lead 5C for inputting the chip select signal of the semiconductor chip 4C.
Instead of connecting to ₁ , it is directly connected to the lead 3A of the decoder 3. The lead 5C ₁ is connected to the leads 3A different from the leads 3A of the lead 5D ₁ decoder 3 is connected. The decoder 3 selects one semiconductor chip 4C or 4D from the eight semiconductor chips 4C and 4D. The main surface of each of the semiconductor chips 4A, 4B, 4C, and 4D, that is, the surface on which the semiconductor element and wiring are provided, is molded with silicone rubber 7 or resin 7.

As described above, the semiconductor chips 4A, 4B, 4C, and 4D to which the leads 5A, 5B, 5C, and 5D are connected by the TAB are mounted on the module substrate 1 without being sealed with the package, and the semiconductors are mounted. By configuring the device, one semiconductor chip 4A, 4B, 4C, 4
Since the area occupied by D on the module substrate 1 can be reduced, many semiconductor chips 4A, 4 can be mounted on the module substrate 1.
B, 4C, 4D can be mounted. That is, the packaging density of the semiconductor device can be increased.

Also, the semiconductor chip 4A is laminated on the semiconductor chip 4B, and the semiconductor chip 4D is laminated on the semiconductor chip 4C.
Without increasing the number of semiconductor chips 4A, 4
B, 4C, 4D can be mounted.

Next, a modification of the first embodiment will be described.

FIG. 4 is a perspective view of a part of the module substrate 1 for explaining a modification of the first embodiment.

As shown in FIG. 4, a semiconductor chip 4E may be further mounted on the semiconductor chip 4A. 5E is a lead of the semiconductor chip 4E.
Connected to A.

However, the lead 5E ₁ for inputting the chip select signal to the semiconductor chip 4E is the lead 5A ₁ ,
5B ₁ leads 5A ₁ and 5B ₁ of the decoder 3 without being connected to 5B _1.
Is connected to a lead 3A different from the lead 3A connected to. Although the back surface of the module substrate 1 is not shown, similarly, on the back surface, a semiconductor chip is further mounted on the semiconductor chip 4D and three semiconductor chips are stacked.

(Second Embodiment) FIG. 5 is a front view of a semiconductor device according to a second embodiment of the present invention.

In FIG. 5, 1A on the front surface of the module substrate 1 is a connection terminal, and 1B is a connection terminal on the back surface.
In this embodiment, one set of three semiconductor chips 4B, 4A, and 4E is arranged on the surface of the module substrate 1, and four sets are arranged. Similarly, on the back side, the semiconductor chips 4C, 4
Three sets of D and 4F are set as one set, and four sets are arranged.

In the second embodiment, the semiconductor chips 4B, 4
By directing the main surfaces of A, 4E, 4C, 4D, and 4F, that is, the surfaces on which the semiconductor elements and wiring are provided and covered with the resin 7 to the module substrate 1, the leads 5
The lengths of A, 5B, 5E, 5C, 5D and 5F are shortened.

(Third Embodiment) FIG. 6 is a side view of a semiconductor device according to a third embodiment of the present invention, and FIG. 7 is a front view of the semiconductor device.

In the third embodiment of the present invention, the semiconductor chip 4A mounted on the front surface of the module substrate 1 faces the module substrate 1 with the back surface thereof facing the module substrate 1, and the semiconductor chip 4C mounted on the back surface of the module substrate 1. Has its main surface facing the module substrate 1. By doing so, when the semiconductor device is viewed from the semiconductor chip 4B, the leads 5B of the semiconductor chip 4B and the leads 5C of the semiconductor chip 4C have the same function. Reed 5B with the same function
And 5C are connected by a through wiring (through hole wiring) 8 of the module substrate 1.

That is, by connecting each lead 5B to the lead 5C having the same function as the lead 5B by the through wiring 8, for example, the lead 5B for inputting an address signal to the semiconductor chip 4B is Through the wiring 8, it is connected to the lead 5C for inputting the address signal to the semiconductor chip 4C. Similarly, each lead 5B which is an input / output terminal of data of the semiconductor chip 4B is connected to the lead 5C which is an input / output terminal of data of the semiconductor chip 4C through the through wiring 8.

However, the lead 5B ₁ for inputting the chip select signal of the semiconductor chip 4B and the lead 5C for inputting the chip select signal of the semiconductor chip 4C.
₁ is not connected by the through wiring 8, the lead 5B ₁ is connected to the decoder 3 provided on the front surface of the module substrate 1, and the lead 5C ₁ is connected to the decoder 3 on the back surface of the module substrate 1.

Here, the module substrate 1 according to the present embodiment has a single-layer structure made of resin such as glass epoxy, and no wiring other than the through wiring 8 is provided inside. However, on the front surface and the back surface of the module substrate 1, between the wiring for connecting the semiconductor chips 4B, 4C and the leads 2 or the decoder 3 (not shown in FIGS. 6 and 7) and the semiconductor chips 4B, 4C. Wiring and the like for connecting the. The through wiring 8 is formed by forming a through hole in the module substrate 1 by, for example, a drill, and then plating a copper layer by, for example, vapor deposition or electroless plating.

As described above, the leads 5B and 5 having the same function
By connecting C with the through wiring 8, a wiring other than the through wiring 8 is not provided in the module substrate 1 to form a single layer structure, so that the reliability of the module substrate 1 can be improved.

Moreover, since the leads 5B and 5C having the same function are connected by the through wiring 8, the number of wirings provided on the front surface and the back surface of the module substrate 1 can be reduced.

The module substrate 1 and the through wiring 8
May be formed of laminated ceramics. In this case, the wiring that connects the semiconductor chips 4B and 4C to the lead 2, the wiring that connects the semiconductor chips 4B and 4C to the decoder 3, and the like are embedded in the module substrate 1. However, the number of these wirings is
For example, since only the wiring that connects the semiconductor chip 4B on the surface of the module substrate 1 to the leads 2 and the decoder 3 needs to be provided, the number of embedded wirings can be significantly reduced, and therefore the reliability of the module substrate 1 can be improved. Can be higher.

(Fourth Embodiment) FIG. 8 is a plan view of two semiconductor chips according to a fourth embodiment of the present invention, and FIG.
8 is a side view of the two semiconductor chips shown in FIG. 8 that are faced to each other and connected to the same lead, and is viewed from the direction I. FIG. 10 shows the two semiconductor chips connected to the same lead. It is a side view when it sees from the direction of II.

The fourth embodiment of the present invention is a semiconductor chip 4
In A, the bump electrodes 6A are sequentially arranged from the upper left corner, and the bump electrodes 6B having the same function as the bump electrodes 6A are connected to the semiconductor chip 4
In B, they are arranged from the upper right corner. That is, the bump electrodes 6A ₂ ... 6A _N-1 of the semiconductor chip _{4A, 6A N, 6A N +} 1 ...
6A _{N + M} and 6B _{2 of the} semiconductor chip 4B ... 6B _N-1 , 6B _N
In 6B _{N + 1} and 6B _{N + M} , those having the same subscript are bump electrodes having the same function.

When the semiconductor chip 4B and the main surface of the semiconductor chip 4A are overlapped so as to face the main surface of the semiconductor chip 4A, the bump electrodes 6B ₂ ... 6B _N-1 , 6B _N ...
6B _{N +1} and 6B _{N + M} are bump electrodes 6 of the semiconductor chip 4A.
_{A 2 ... 6A N-1,} 6A N, so as to overlap the _{6A N + 1 ... 6A N +} M, their bump electrodes 6A, are arranged 6B the symmetrically. These symmetrically arranged bump electrodes 6A, 6
B is connected to the same lead 5. However, the bump electrode 6A ₁ for inputting the chip select signal of the semiconductor chip 4A and the bump electrode 6B ₁ for inputting the chip select signal of the semiconductor chip 4B are staggered so as not to overlap each other, and the bump electrodes 6A ₁ and Connected.

An insulating material 9 insulates the lead 5 connected to the bump electrode 6A ₁ from the semiconductor chip 4B, and insulates the lead 5 connected to the bump electrode 6B ₁ from the semiconductor chip 4A. . The lead 5 is formed into an appropriate shape after the semiconductor chips 4A and 4B are faced to each other and connected to the lead 5. A plurality of semiconductor chips 4A and 4B are arranged on the front surface and the back surface of the module substrate 1, respectively.

As described above, by arranging the bump electrodes 6A and 6B symmetrically and connecting them to the same lead 5, the semiconductor chips 4A, 4 on the module substrate 1 are connected.
The mounting density of B can be doubled.

As shown in FIGS. 11 and 12, the bump electrodes 6A ₁ of the semiconductor chip 4A and the semiconductor chip 4 are
The B bump electrodes 6B ₁ may be arranged at symmetrical positions, that is, when the semiconductor chip 4B is overlaid on the semiconductor chip 4A, the bump electrodes 6A ₁ and 6B ₁ may overlap. However, the lead 5 to which the bump electrode 6A ₁ is connected and the lead 5 to which the bump electrode 6B ₁ is connected are overlapped,
The insulating material 9 insulates between them.

FIG. 11 is a plan view of the two semiconductor chips 4A and 4B which are superposed, and FIG. 12 shows the semiconductor chips 4A and 4B facing each other and connected to the same lead 5, which is I of the semiconductor chip 4A. It is a side view when it sees from the direction.

The present invention has been specifically described above based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

[0043]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

Since a semiconductor device is constructed by mounting a plurality of semiconductor chips to which leads are connected by TAB on a module substrate without encapsulating with a package, the area occupied by one semiconductor chip on the module substrate can be reduced. Therefore, many semiconductor chips can be mounted on the module substrate. That is, the packaging density of the semiconductor device can be increased.

[Brief description of drawings]

FIG. 1 is a plan view showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a side view showing a schematic configuration of the semiconductor device.

FIG. 3 is a front view showing a schematic configuration of the semiconductor device.

FIG. 4 is a perspective view of a part of the module substrate 1 for explaining a modified example of the first embodiment.

FIG. 5 is a front view of the semiconductor device according to the second embodiment of the present invention.

FIG. 6 is a side view of a semiconductor device according to a third embodiment of the present invention.

FIG. 7 is a front view of the semiconductor device.

FIG. 8 is a plan view of two semiconductor chips according to a fourth embodiment of the present invention.

9 is a side view when the two semiconductor chips shown in FIG. 8 are faced to each other and connected to the same lead, and viewed from the direction I. FIG.

FIG. 10 is a side view when two semiconductor chips connected to the same lead are viewed from a direction II.

FIG. 11 is a plan view of two semiconductor chips 4A and 4B which are superposed on each other.

FIG. 12 is a side view when the semiconductor chips 4A and 4B are faced to each other and connected to the same lead 5, and viewed from the direction I of the semiconductor chip 4A.

[Explanation of symbols]

1 ... Module substrate, 2, 3A, 5A, 5B, 5C, 5
D, 5E, 5F ... Read, 3 ... Decoder, 4A, 4B,
4C, 4D ... Semiconductor chips, 6A, 6B ... Bump electrodes,
7 ... Silicone rubber or resin, 8 ... Penetration wiring, 9 ... Insulating material.

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] December 11, 1995

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction content]

[Document name] Statement

Title: Semiconductor device

[Claims] 1. By symmetrically arranging the bump electrodes having the same function of the first semiconductor chip and the second semiconductor chip, the same function is provided in a state where the first semiconductor chip and the second semiconductor chip face each other. And the bump electrodes having different functions are connected to the same lead by facing each other. The arrangement of the bump electrodes having different functions between the first semiconductor chip and the second semiconductor chip is asymmetrical. While facing the semiconductor chip,
A semiconductor device comprising a set of semiconductor chips in which the bump electrodes having different functions are connected to different leads without facing each other. 2. By symmetrically arranging the bump electrodes having the same function of the first semiconductor chip and the second semiconductor chip, the same function is provided in a state where the first semiconductor chip and the second semiconductor chip face each other. And the bump electrodes having different functions are connected to the same lead by facing each other. The arrangement of the bump electrodes having different functions between the first semiconductor chip and the second semiconductor chip is asymmetrical. While facing the semiconductor chip,
A plurality of sets of semiconductor chips connected to different leads without facing the bump electrodes having different functions are mounted on a mounting substrate, and one end of a flexible lead is connected to a bump electrode of the semiconductor chip, A semiconductor device characterized in that the other end of the lead is electrically connected to a wiring formed on the mounting substrate. 3. The set of semiconductor chips is mounted on both sides of one side and the other side of a mounting substrate, and among the leads, leads having the same function are conducted to a common wiring, and leads having different functions are made independent. 3. The semiconductor device according to claim 2 , wherein the semiconductor device is configured to be electrically connected to each corresponding wiring. 4. Bump electrodes and insulators having different functions from the first semiconductor chip and the second semiconductor chip are arranged symmetrically,
2. The method according to claim 1, wherein the first semiconductor chip and the second semiconductor chip are opposed to each other, and the bump electrodes having different functions and the insulating material are opposed to each other .
The semiconductor device according to any one of items 1 to 3 .

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a plurality of semiconductor chips on a mounting substrate.
The present invention relates to a semiconductor device mounted and modularized .

[0002]

2. Description of the Related Art A semiconductor chip sealed in a package is
A semiconductor device having a high mounting density constituted by mounting a plurality of devices on a mounting substrate (module substrate) is published by Nikkei McGraw-Hill, Nikkei Electronics Supplement, no. 2 “Microdevices” p150.

[0003]

The present inventor has found the following problems as a result of examining the semiconductor device.

[0004] Since there is a limit in reducing the size of the package itself, it is difficult to increase the mounting density of semiconductor chips on a module substrate.

An object of the present invention is to increase the mounting density of a semiconductor device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

That is, the bump electrode of the semiconductor chip is connected to the lead, and a plurality of semiconductor chips having the lead are connected to the wiring of the module substrate to form a semiconductor device.

According to the above-mentioned means, since the semiconductor chip is not sealed with the package, the mounting density of the semiconductor chip on the module substrate can be increased.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
explain.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION First of all, the technology which is the premise of the present invention
There is a technology for mounting the semiconductor device on a module substrate.
And explain.

(Mounting Technology 1) FIG. 1 is a schematic diagram of a semiconductor device.
FIG. 2 is a plan view showing a mounted state of the tool board.
FIG. 3 is a front view of the semiconductor device, and FIG. 3 shows the semiconductor device shown in FIG.
It is a side view which expands and shows .

In FIG. 1 to FIG. 3, reference numeral 1 denotes a module substrate formed by laminating a plurality of ceramic layers and wiring layers by a laminated ceramic, and eight semiconductor chips 4A, 4B and 8 semiconductors
Chips 4C and 4D are mounted. Semiconductor chip 4A,
4B, 4C, 4D, for example, which Sutatiku RAM is configured, not sealed by the package comprising a ceramic, resin, or the like, the semiconductor element and wiring shape
The formed surface is molded with silicone rubber 7 or resin 7.

[0014] semiconductor chip 4A, 4B, 4C, each of 4D are bump electrodes 6 formed of solder or gold or the like is provided, rie de 5A to the bump electrodes 6, 5B, 5
C and 5D are TAB (Tape Automated Bondin)
g) connected by

With respect to the surface, the semiconductor chip 4A is
Each lead 5A is laminated on the conductor chip 4B.
And lead 5B that have the same function
Are connected by, for example, solder. For example, a lead 5A for inputting an address signal to the semiconductor chip 4A is connected to a lead 5B for inputting an address signal to the semiconductor chip 4B, and similarly, a lead for inputting and outputting data of the semiconductor chip 4A. 5A is connected to a lead 5B for inputting and outputting data of the semiconductor chip 4B. The semiconductor chip 4B adjacent to the module substrate 1
Each lead 5B is connected to a wiring (see FIG.
(Not shown), the decoder 3 and the module substrate 1
Connected to the card 2.

On the other hand, those having different functions, for example,
The lead 5A ₁ for inputting the chip select signal to the semiconductor chip 4A is not connected to the lead 5B ₁ for inputting the chip select signal to the semiconductor chip 4B, but is connected to the lead 3A of the decoder 3. Also, lead 5
B ₁ is connected to a lead 3A different from the lead 3A to which the lead 5A ₁ is connected. 8 by decoder 3
Pieces of the semiconductor chip 4A, has a configuration for selecting one of the semiconductor chips 4A or 4B from the 4B.

The same applies to the back surface, and the semiconductor chip
4D is stacked on the semiconductor chip 4C,
The leads 5D and 5C have the same function.
Are connected to each other with solder or the like. For example, semiconductor chips
Lead 5D for inputting an address signal to the top 4D
Is for inputting an address signal to the semiconductor chip 4C.
The lead 5C is connected to the semiconductor chip 4D.
The lead 5D for inputting and outputting data is a semiconductor chip
Connected to lead 5C for input / output of 4C data
Has been. Semiconductor chip 4 adjacent to module substrate 1
C, each lead 5C is arranged in the module substrate 1.
Decoder 3 and module board by wires (not shown)
1 lead 2.

On the other hand, those having different functions, for example ,
Lead 5D ₁ for inputting a chip select signal to the semiconductor chip. 4D, the connection Sarezu the lead 5C ₁ for inputting a chip select signal to the semiconductor chip 4C,
It is connected to the lead 3A of the decoder 3. The lead 5C _1, the lead 5D ₁ is connected to the leads 3A different leads 3A connected, selects one of the semiconductor chips 4D or 4C among eight semiconductor chips 4D, 4C by the decoder 3 It has a configuration .

[0019] As mentioned above, it has not been sealed in the package
The semiconductor chips 4A, 4B, 4C, 4D are
B to lead 5A, 5B, 5C, 5D
By mounting on the module substrate 1 , the mounting area is reduced, and many semiconductor chips 4A, 4B, 4
C and 4D can be mounted. That is, the packaging density of the semiconductor device can be increased.

The semiconductor chips 4A, 4B and the semiconductor
By stacking the chips 4C and 4D, respectively,
Module substrate 1 with more semiconductor chips 4
A, 4B, 4C, 4D can be mounted.

Next, a modified example of the above-described mounting state will be described.

FIG. 4 shows a partially mounted state of this modification.
It is a perspective view shown .

In this modification, in addition to the above structure, a semiconductor
A semiconductor chip 4E is further mounted on the body chip 4A.
There is . 5E is a lead of the semiconductor chip 4E, which is the same machine
It is connected to the functional lead 5A.

On the other hand, those having different functions, for example,
Lead 5E ₁ for inputting a chip select signal to the semiconductor chip. 4E, instead of being connected to the lead 5A _1, 5B _1, and to different leads 3A leads 3A of the decoder 3 to read 5A _1, 5B ₁ is connected It is connected. Similarly, on the back surface of the module substrate 1, the semiconductor chip 4
Equipped with a further semiconductor chip on the D, and a three were laminated structure.

(Mounting Technology 2) FIG. 5 shows another mounting state.
It is a side view.

In FIG. 5, 1A is the module board 1
A connection terminal of the surface, 1B is rear surface of the connection terminal.
In this mounting state, the semiconductor chip is placed on the surface of the module substrate 1.
The tops 4B, 4A, and 4E are stacked to form one set, and four sets are arranged. Similarly on the back side, the semiconductor chip 4
C, 4D, and 4F are laminated to form one set, and four sets are arranged.

In this mounting state, the semiconductor chips 4B, 4B
Main surface of each of A, 4E, 4C, 4D, and 4F, that is,
Leads 5A, 5B, 5E, 5C, 5D, and 5F are connected.
By making the surface facing the module substrate 1
Length of leads 5A, 5B, 5E, 5C, 5D, 5F
Can be shortened .

(Mounting Technology 3) FIG. 6 shows another mounting state.
7 is a side view of the mounted state shown in FIG.
FIG.

In this mounting state, the semiconductor chip 4A mounted on the front surface of the module substrate 1 has its back surface facing the module substrate 1, and the semiconductor chip 4C mounted on the back surface of the module substrate 1 has its main surface mounted. The surface faces the module substrate 1 .

Thus, both sides of the module substrate 1
When the semiconductor chips 4A and 4B are mounted,
4B lead 5B and semiconductor chip 4C lead 5C
Those with the same function face each other.
Function lead 5B and lead 5C
Connect only by through wiring (through hole wiring) 8.
be able to.

For example, a lead 5B for inputting an address signal to the semiconductor chip 4B is connected to a lead 5C for inputting an address signal to the semiconductor chip 4C by a through wiring 8. Similarly, the semiconductor chip 4B
The lead 5B which is an input / output terminal of the data of
By being connected to the lead 5C is an input-output terminal of the data of the semiconductor chip 4C.

On the other hand, those having different functions, for example ,
The lead 5B ₁ for inputting the chip select signal of the semiconductor chip 4B and the lead 5C ₁ for inputting the chip select signal of the semiconductor chip 4C are not connected to each other by the through wiring 8 and are different in different wirings.
Connected to the third order. That is, the lead 5B ₁ is connected to the decoder 3 provided on the surface of the module substrate 1, lead 5C ₁ is connected to the back surface of the decoder 3 of the module substrate 1
Has been done.

Here, the module substrate 1 in this mounting state has a single-layer structure made of resin such as glass epoxy, and no wiring other than the through wiring 8 is provided inside. Between the semiconductor chips 4B and 4C and the lead 2
Wiring or a decoder 3 (see FIGS. 6 and 7)
(Not shown) and the semiconductor chips 4B and 4C.
Continued wiring and the like are provided on the front surface and the back surface of the module substrate 1 . Penetrating wiring 8 is the through hole formed by the module substrate 1, for example a drill or the like, in which form the shape of the deposition or electroless plating or the like, for example, a copper layer.

As described above, the leads 5B and 5 having the same function
By connecting the C in penetrating wiring 8, a single layer structure has Na provided wiring other than the through wiring 8 on the module substrate 1
And the reliability of the module substrate 1 can be improved.

Further, since the leads 5B and 5C having the same function are connected by the through wiring 8, the number of wirings provided on the front surface and the back surface of the module substrate 1 can be reduced.

The module substrate 1 and the through wiring 8
May be formed of laminated ceramics. In this case, the wiring connecting the semiconductor chips 4B and 4C and the lead 2, the wiring connecting the semiconductor chips 4B and 4C and the decoder 3, and the like are embedded in the module substrate 1. However, the number of these wires must be connected by through wires 8 .
That have different functions, such as module
The semiconductor chip 4B on the surface of the plate 1 is connected to the lead 2 and the decoder 3
Connections since it is only providing the wires or the like, can be number of wires to be embedded is greatly reduced, increasing the reliability of the module substrate 1.

(Embodiment) Techniques on which the present invention is based
With regard to the embodiment of the present invention considered based on the operation,
I will explain below.

FIG . 8 is used in the embodiment of the present invention.
FIG. 9 is a plan view showing two semiconductor chips, and FIG.
The state where the two semiconductor chips connected to the leads is
FIG. 10 is a longitudinal sectional view showing the apparatus from the direction II, and FIG.
It is a longitudinal sectional view.

In the semiconductor chip 4A used in the embodiment of the present invention, the arrangement of the bump electrodes 6A is arranged in order from the upper left corner.
Next, bump electrodes 6A ₂ ... 6A _N-1 , 6A _N , 6A _{N + 1} ... 6A
_{It is} arranged like _{N + M} , and bump electrodes 6 are provided on the semiconductor chip 4B.
The B electrodes are arranged in order from the upper right corner to the bump electrodes 6B ₂ ... 6B.
_N- 1、6B _N ... 6B _{N +} 1、6B _{N + M}
The poles 6A and 6B are arranged symmetrically . Where the subscript is
The same thing that has become a bump electrode of the same function.

With this arrangement, the main part of the semiconductor chip 4B is
When the surface and the main surface of the semiconductor chip 4A face each other,
Bump electrodes 6B ₂ ... 6B _N-1 , 6B _N ... Of conductor chip 4B
6B _{N +1} and 6B _{N + M} are semiconductors having the same function
Bump electrodes 6A _{2 of} chip 4A ... 6A _N-1 , 6A _N , 6A
_{N + 1} ... 6A It will face _{N + M.} These symmetrically
The arranged bump electrodes 6A and 6B have the same
Mode 5 is connected. On the other hand, those with different functions
For example, the bump electrodes 6A ₁ for inputting a chip select signal of the semiconductor chip 4A, the bump electrodes 6B ₁ for inputting a chip select signal of the semiconductor chip 4B is
By shifting the arrangement, they are connected to separate leads 5.

An insulating material 9 insulates the lead 5 connected to the bump electrode 6A ₁ from the semiconductor chip 4B, and insulates the lead 5 connected to the bump electrode 6B ₁ from the semiconductor chip 4A. . The lead 5 is formed into an appropriate shape after the semiconductor chips 4A and 4B are faced to each other and connected to the lead 5. A plurality of semiconductor chips 4A and 4B are arranged on the front surface and the back surface of the module substrate 1, respectively.

As described above, by arranging the bump electrodes 6A and 6B symmetrically and connecting them to the same lead 5, the semiconductor chips 4A, 4B
The mounting density of B can be doubled.

Hereinafter , all of the bump electrodes 6A and 6B are
The structure arrange | positioned facing each other is shown.

FIG . 11 shows a circuit used in this embodiment.
FIG. 12 is a plan view showing one semiconductor chip, and FIG.
The state where the two semiconductor chips thus connected to the leads is
It is a longitudinal cross-sectional view shown from a direction.

In this case, the semiconductor chips 4A, 4B
The bump electrode 6A ₁ and the bump electrode 6B ₁ having different functions are paired.
At the main surface of the semiconductor chip 4B and the semiconductor chip.
When the main surface of the bump 4A faces, the bump electrode 6
A ₁ and 6B ₁ will face each other. In this case, the van
Lead 5 to which bump electrode 6A ₁ is connected, and bump electrode 6
An insulating material 9 is provided between the lead 5 to which B ₁ is connected and
To isolate and insulate each.

Also, in the present embodiment,
As in the art, multiple sets were mounted in the longitudinal direction of the mounting board 1.
Therefore, a method of using wiring that penetrates the mounting board 1 is suitable.
May be used.

Although the present invention has been described in detail with reference to the embodiments, the present invention is not limited to the above-described embodiments, and may be variously modified without departing from the gist thereof. Needless to say.

[0048]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

By connecting the semiconductor chips not sealed by the package to the leads by TAB and mounting the semiconductor chips on the module substrate, the mounting area is reduced, and many semiconductor chips can be mounted on the module substrate.

Further, by laminating the semiconductor chips, more semiconductor chips can be mounted on the same size module substrate.

Therefore, the mounting density of the semiconductor device can be increased.

[Brief description of drawings]

FIG. 1 is a plan view showing a mounted state of a semiconductor device on a module substrate .

FIG. 2 is a front view of the semiconductor device shown in FIG . 1 ;

FIG. 3 is an enlarged side view showing the semiconductor device shown in FIG.

FIG. 4 is a perspective view partially showing a mounting state of a modified example .

FIG. 5 is a side view showing another mounting state .

FIG. 6 is a front view partially showing another mounting state .

FIG. 7 is a side view of the mounting state shown in FIG . 6 ;

FIG. 8 shows two semiconductors used in the embodiment of the present invention.
It is a top view showing a chip .

FIG. 9 shows the connection of the two semiconductor chips shown in FIG .
It is a longitudinal cross-sectional view showing a continuous state from the I direction .

FIG. 10 is a plan view showing the two semiconductor chips shown in FIG . 8 as leads.
FIG. 2 is a longitudinal sectional view showing a connected state from a direction II .

FIG. 11 shows two semiconductor chips used in this embodiment .
It is a top view which shows a top.

FIG. 12 is a view for reading two semiconductor chips shown in FIG . 11;
FIG. 3 is a longitudinal sectional view showing a state of connection from a direction I.

[Explanation of reference numerals] 1 ... Module substrate, 2, 3A, 5A, 5B, 5C, 5
D, 5E, 5F ... Read, 3 ... Decoder, 4A, 4B,
4C, 4D ... Semiconductor chips, 6A, 6B ... Bump electrodes,
7 ... Silicone rubber or resin, 8 ... Penetration wiring, 9 ... Insulating material.

Front page continuation (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication location H01L 25/00 A 25/065 25/07 25/18 H01L 25/08 Z (72) Inventor Masayuki Watanabe Chiba Prefecture 3681 Hayano, Mobara-shi Hitachi Device Engineering Co., Ltd. (72) Inventor Toshio Kanno 1450, Kamisuihonmachi, Kodaira-shi, Tokyo Inside Musashi Plant, Hitachi, Ltd. (72) Seiichiro Tsukui, Asahidai, Moroyama-cho, Iruma-gun, Saitama Prefecture Address Nitto Eastern Semiconductor Co., Ltd. (72) Inventor Takashi Ono 64 Naganuma, Tenno-cho, Minami-Akita-gun, Akita Prefecture Akita Denshi Co., Ltd. Musashi factory

Claims (4)

[Claims] 1. A state in which a first semiconductor chip and a second semiconductor chip are opposed to each other by symmetrically arranging bump electrodes having the same function in the first semiconductor chip and the second semiconductor chip. Then, the bump electrodes having the same function are opposed to each other and connected to the same lead, and the arrangement of the bump electrodes having different functions in the first semiconductor chip and the second semiconductor chip is asymmetrical, With the chip and the second semiconductor chip facing each other,
A semiconductor device comprising a set of semiconductor chips in which the bump electrodes having different functions are connected to different leads without facing each other. 2. A state in which the first semiconductor chip and the second semiconductor chip are opposed to each other by symmetrically arranging bump electrodes having the same function in the first semiconductor chip and the second semiconductor chip. Then, the bump electrodes having the same function are opposed to each other and connected to the same lead, and the arrangement of the bump electrodes having different functions in the first semiconductor chip and the second semiconductor chip is asymmetrical, With the chip and the second semiconductor chip facing each other,
A plurality of sets of semiconductor chips connected to different leads without facing the bump electrodes having different functions are mounted on a mounting substrate, and one end of a flexible lead is connected to a bump electrode of the semiconductor chip, A semiconductor device characterized in that the other end of the lead is electrically connected to a wiring formed on the mounting substrate. 3. The sets of semiconductor chips are mounted on both sides of one surface and the other surface of a mounting substrate, respectively, and among the leads, leads having the same function are electrically connected to a common wiring to have different functions. 3. The semiconductor device according to claim 2, wherein the lead is made independent and is electrically connected to each corresponding wiring. 4. The first semiconductor chip and the second semiconductor chip are arranged symmetrically with bump electrodes and insulators having different functions, and the first semiconductor chip and the second semiconductor chip are opposed to each other. 2. In this state, the bump electrodes having different functions and the insulating material are opposed to each other, respectively.
The semiconductor device according to claim 3.