JPH08204663A - Identification signal detector - Google Patents

Abstract

PURPOSE: To improve the reliability for detecting an identification signal phase- multiplexed onto an intermediate frequency signal by providing an output of AND between a detection result by an identification signal detection means and a detection result of an intermediate frequency detection means. CONSTITUTION: The detector is provided with an identification signal detection means 2 applying in-phase synchronization detection to an identification signal S8 with an output S13 of a phase locked loop circuit 10 phase-locking to an identification signal S8 obtained based on a detection result signal S7 resulting from applying orthogonal synchronization detection to an intermediate frequency signal, an intermediate frequency detection means 3 applying in-phase synchronization detection to the intermediate frequency signal S1, and a logical arithmetic means 5 providing an output of an AND signal S4 between a detection result signal S2 from the identification signal detection means 2 and a detection result signal S3 of the intermediate frequency detection means 3. Then an AND between the detection result signal S2 of the identification signal detection means 2 detecting the identification signal S8 through phase locking by a phase lock loop circuit 10 and the detection result signal S3 of the intermediate frequency detection means 3 is provided as an output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an identification signal detecting device, and can be applied to, for example, an AM stereo identifying device for identifying and displaying whether or not an AM stereo broadcast is received.

[0002]

2. Description of the Related Art Conventionally, an AM stereo discriminating apparatus discriminates whether or not an AM stereo broadcast is received by detecting a pilot signal superimposed on an AM stereo broadcast signal. A method for detecting a pilot signal is a band pass filter (hereinafter referred to as BPF) having a predetermined pass band.
That detects the level of the signal that has passed through the
There is one that counts several cycles and detects how many cycles the signal passed through F continues.

[0003]

However, in the above-mentioned method, it is not possible to confirm on the frequency axis whether or not the detected signal is a pilot signal. Further, since the frequency of the pilot signal is a very low frequency such as 25 [Hz], it is difficult to increase the narrow band selectivity. Therefore, in the above-mentioned detection method, when a single signal component enters the band of the pilot signal (BPF pass band) such as the beat with the adjacent station, a signal other than the pilot signal is erroneously detected as a pilot signal. However, there is a problem in that detection speed and reliability are low.

The present invention has been made in consideration of the above points, and proposes an identification signal detecting device which can improve the reliability of detection when detecting an identification signal which is phase-multiplexed and superimposed on an intermediate frequency signal. Is what you are trying to do.

[0005]

In order to solve the above problems, the present invention provides an AM-modulated intermediate frequency signal (S
In the identification signal detecting device (1) for detecting the identification signal (S8) of a predetermined low frequency which is phase-multiplexed and superimposed on 1),
The intermediate frequency signal (S1) is subjected to quadrature synchronous detection, and the detection result (S
Identification signal detecting means (2) for in-phase synchronous detection of the identification signal (S8) by the output (S13) of the phase lock loop circuit (10) that locks in phase with the identification signal (S8) obtained based on 7). An intermediate frequency detection means (3) for synchronously detecting the intermediate frequency signal (S1), a detection result (S2) of the identification signal detection means (2), and a detection result (S3) of the intermediate frequency detection means (3). And a logical operation means (5) for outputting a logical product (S4) based on the above.

[0006]

The identification signal (S8) is sent to the phase lock loop circuit (1
Identification signal detecting means (2) for phase-locked detection in (0)
When the identification signal (S8) which is phase-multiplexed and superimposed on the intermediate frequency signal is detected by outputting the logical product of the detection result (S2) of (1) and the detection result (S3) of the intermediate frequency detection means (3). , The reliability of detection can be improved.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, reference numeral 1 denotes an AM stereo discriminating apparatus as a whole, which is superposed on an AM stereo broadcast signal.
A 25 [Hz] pilot signal is detected and displayed.

The AM stereo identification device 1 converts the broadcast signal into P
An intermediate frequency signal S1 obtained by performing stable envelope detection at LL is given to the pilot signal detecting section 2, the intermediate frequency level detecting section 3 and the switching signal generating section 4. The pilot signal detecting section 2 and the intermediate frequency level detecting section 3 send the respective detection signals S2 and S3 to the first and second of the AND circuit 5.
It is given as the condition input of. The AND circuit 5 detects the detection signal S
A logical product signal S4 corresponding to 2 and S3 is given to the driver 6 to control blinking of the light emitting diode 7.

The switching signal generating section 4 outputs a quadrature switching signal S5 and an in-phase switching signal S6 which are synchronized with the intermediate frequency signal S1, respectively, to the pilot signal detecting section 2.
And to the intermediate frequency level detector 3. The pilot signal detector 2 supplies the intermediate frequency signal S1 to the synchronous detector 8,
The sub-channel detection signal S7 that is quadrature modulated by the quadrature switching signal S5 is sent to the BPF 9 and the outside. BPF
Reference numeral 9 mainly passes the stereo pilot signal S8 included in the low range of the sub-channel detection signal S7 and supplies it to the pilot signal PLL circuit 10 and the pilot signal level detection circuit 11.

As a result, the pilot signal PLL circuit 10 and the pilot signal level detection circuit 11 cause the DC component of the subchannel detection signal S7, the voice band component, and the parasitic phase modulation (Incide) of the signal itself from the broadcasting station.
It is possible to prevent malfunction due to the ntal phase modulation).

The PLL circuit 10 for the pilot signal includes a synchronous detector 12, a low-pass filter (hereinafter referred to as LPF) 13, a voltage-controlled oscillator (hereinafter referred to as VCO) 14, and a counter 15 to which the pilot signal S8 is applied.
multiply. The pilot signal level detection circuit 11 supplies the pilot signal S8 to the synchronous detector 16 and the counter 15
The in-phase detection is performed by the switching signal S13 sent by. The synchronous detector 16 generates a DC component signal S14 according to the level of the pilot signal S8, and supplies it to the comparator 18 as a DC component signal S15 through the LPF 17.

The comparator 18 operates in a hysteresis manner, and depending on whether or not the DC component signal S15 has reached a predetermined level or higher, a detection signal of logic "1" level or logic "0" level indicating the presence or absence of a pilot signal. Outputs S2. The intermediate frequency level detector 3 detects the intermediate frequency signal S1 by the synchronous detector 19
To a main channel detection signal S16 which is in-phase multi-modulated by the in-phase switching signal S6.
It is supplied to the comparator 21 as a DC component signal S17 through 0.

The comparator 21 is a logic "1" level or a logic indicating whether or not the intermediate frequency signal S1 is obtained by synchronizing with the broadcast signal according to whether or not the DC component signal S17 has reached a predetermined level or higher. The detection signal S3 of "0" level is output. The switching signal generation unit 4 includes a synchronous detector 22, an LPF 23, a DC amplification circuit 24, a VC to which the intermediate frequency signal S1 is applied.
The PLL is applied by the O25 and the counter 26, and the quadrature switching signal S5 and the in-phase switching signal S6 are output from the counter 26. DC amplifier circuit 24
Adjusts the PLL loop gain according to the detection signal S3. The synchronous detector 22 quadrature-detects the intermediate frequency signal S1 with the quadrature switching signal S5.

In the above configuration, when the pilot signal S8 and the intermediate frequency DC component signal S17 reach a predetermined level or more in synchronization with the AM stereo broadcast signal, the pilot signal detecting section 2 and the intermediate frequency level detecting section 3 respectively, The AND circuit 5 outputs the detection signals S2 and S3 of the logic "1" level.
Give to. Thereby, the AND circuit 5 can output the logical product signal S4 of the logic "1" level to turn on the light emitting diode and display that the AM stereo signal is being received.

When a normal AM broadcast is received or the tuning with the AM stereo broadcast is incomplete, the pilot signal S8 or the DC component signal S17 disappears and the detection signal S
At least one of 2 and S3 becomes the logic "0" level. As a result, the AND circuit 5 outputs the logical product signal S4 of logic "0" level to turn off the light emitting diode.

In this way, the stereo display circuit is turned on only when the direct current component signal S17 of the intermediate frequency reaches the predetermined level or more and the logical product with the detection signal S3 is obtained by synchronizing with the AM stereo broadcast signal. I will let you. At this time, the switching signal generator 4 reduces the PLL loop gain to, for example, 1/100 of the normal gain in the phase locked state by the logic "1" level detection signal S3.

As a result, it is possible to reduce the lock sensitivity to the adjacent station and the interfering station with respect to the received AM stereo broadcast and to stably receive the AM stereo broadcast. Further, by using the switching signal generator 4 and the pilot signal PLL circuit 10 together,
It is possible to prevent erroneous stereo display due to the beat that occurs before the lock of the synchronous detection.

According to the above construction, the pilot signal S8
Detection signal S2 output from the pilot signal detecting section 2 for phase-locking and detecting
And the detection signal S3 output by the intermediate frequency level detection unit 3 are output to detect the pilot signal S8 that is phase-multiplexed and superimposed on the intermediate frequency signal S1 of the AM stereo broadcast. The reliability can be improved.

In the above embodiment, the case of detecting the pilot signal S8 of 25 [Hz] has been described.
The present invention is not limited to this, and can be widely applied to a system in which a low-frequency (low-frequency) identification signal as a marker is included in the phase information regardless of the AM stereo broadcasting system. Also in this case, the same effect as described above can be obtained. In order to cope with this, the pass band frequency f ₀ of the BPF and the oscillation frequency of the VCO of the pilot PLL may be changed.

[0021]

As described above, according to the present invention, the logical product of the detection result of the identification signal detection means for detecting the identification signal by phase-locking it in the phase-locked loop circuit and the detection result of the intermediate frequency detection means is output. By doing so, it is possible to realize an identification signal detection device that can improve the reliability of detection when detecting an identification signal that is phase-multiplexed and superimposed on an intermediate frequency signal.

[Brief description of drawings]

FIG. 1 is a connection diagram showing an AM stereo identification device according to an embodiment of an identification signal detection device of the present invention.

[Explanation of symbols]

1 ... AM stereo identification device, 2 ... Pilot signal detection unit, 3 ... Intermediate frequency level detection unit, 4 ... Switching signal generation unit, 5 ... AND circuit, 6 ... Driver, 7
...... Light emitting diodes, 8, 12, 16, 19, 22 ......
Synchronous detector, 9 ... BPF, 10 ... PLL circuit for pilot signal, 11 ... Pilot signal level detection circuit,
13, 17, 20, 23 ... LPF, 14, 25 ... V
CO, 15 ... Counter, 18, 21 ... Comparator, 24
...... DC amplification circuit, 26 …… Counter.

Claims (3)

[Claims] 1. An identification signal detecting device for detecting an identification signal of a predetermined low frequency, which is phase-multiplexed and superimposed on an AM-modulated intermediate frequency signal, wherein the intermediate frequency signal is quadrature-coherently detected and obtained based on the detection result. An identification signal detection means for in-phase synchronous detection of the identification signal by the output of a phase-locked loop circuit for phase-locking the identification signal, an intermediate frequency detection means for in-phase synchronous detection of the intermediate frequency signal, and the identification signal An identification signal detecting apparatus comprising: a logical operation means for outputting a logical product based on the detection result of the detection means and the detection result of the intermediate frequency detection means. 2. A phase lock loop circuit for quadrature-coherently detecting the intermediate frequency signal to phase-lock with the intermediate frequency signal, the phase-locked loop circuit including the quadrature synchronous detection lock signal of the identification signal detecting means. 2. The in-phase synchronous detection lock signal of the intermediate frequency detection means is output, and the loop gain of the phase lock loop circuit is controlled based on the detection result of the intermediate frequency detection means. Identification signal detection device. 3. The identification signal detecting device according to claim 1, wherein the predetermined low frequency is 25 [Hz].