JPH08204521A - Comparator circuit - Google Patents

Abstract

PURPOSE: To prevent the duty ratio of an output signal waveform corresponding to a signal change in an input signal difference from being changed by providing two PNP transistors(TRs), an NPN TR and a constant current source to the comparator circuit in addition to a differential circuit and a current mirror circuit. CONSTITUTION: When an input signal I1 is higher in its level than the level of a signal I2, a difference signal n3 between TRs QP2, QP1 is fed as the base of a TRQN 3 of an output circuit 3. Thus, the TRQN 3 is conductive and the level of an output signal O1 is decreased by receiving current from an external load via an output terminal TO1. On the other hand, since a TRQN 4 forms a current mirror circuit with a TRQN 1, the TRQN 4 is going to supply a collector current twice that of the TRQN 1. The potential of a node N4 is increased to cut off a TRQP 3. Thus, the level of the output signal O1 is decreased and the circuit transits to a stable state. The processing above is applied also to the case that the signal I1 is lower in its level than the level of the signal I2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparator circuit, and more particularly to a comparator circuit for analog signal processing.

[0002]

2. Description of the Related Art Conventionally, a comparator circuit of this type is generally composed of a differential circuit with two positive inputs and an output circuit for outputting the output signal of this differential circuit to the outside.

Referring to FIG. 3 which is a circuit diagram showing a conventional general first comparator circuit, this conventional first comparator circuit has an input signal I1, supplied to positive and complementary input terminals TI1, TI2. A differential circuit 1 that generates a differential output signal n3 at a node N3 in response to I2, a current mirror circuit 2 that constitutes an active load circuit of the differential circuit 1, and an output signal in response to the differential output signal n3. O1 is generated and output terminal TO
1 and an output circuit 3 of an open collector type for outputting to 1.

In the differential circuit 1, each emitter is commonly connected and each collector is connected to a node N1.
3, PNP type transistors QP1 and QP2 whose bases are connected to input terminals I1 and I2, respectively.
And a constant current source IS1 that supplies a constant operating current from the power supply Vcc to the node N1.

The current mirror circuit 2 has NPN type transistors QN1 and QN2 whose emitters are commonly connected to a power supply Vss and whose bases are commonly connected, and whose collectors are respectively connected to nodes N2 and N3.
Is provided.

The output circuit 3 has an NPN transistor QN3 having a base connected to a node N3, an emitter connected to a power supply Vss, and a collector connected to an output terminal O1, and a pull-up inserted between the power supply Vss and the output terminal O1. Resistance R1
With.

Next, for convenience of explanation, it is assumed that β of each transistor is sufficiently large, and the operation of the conventional comparator circuit will be described with reference to FIG. 3. Transistors QP1 and QP2 of the differential circuit 1 have common emitters. Since they are connected, the difference between the base-emitter voltages corresponds to the level difference between the input signals I1 and I2. First, the input signal I
When the signal level of 1 is higher than the signal level of the input terminal I2, the base-emitter voltage of the transistor QP2 is higher than that of the transistor QP1, and therefore almost all of the supply current of the constant current source IS1 is the transistor QP.
2 becomes the emitter / collector current, while the emitter / collector current of the transistor QP1 becomes almost zero. Further, the transistors QN1 and QN of the current mirror circuit 2 are
Since the emitter bases of 2 are commonly connected, they operate so that the same collector / emitter current flows. Therefore, the difference current between the collector currents of the transistors QP2 and QP1 is supplied as the base current of the transistor QN3 of the output circuit 3. As a result, the transistor QN3 becomes conductive, and the level of the output signal O1 decreases by taking in (short-circuiting) the current from the external load via the output terminal TO1.

The level of the output signal O1 decreases to 0.6-
When the voltage reaches 0.5 V or less, the transistor QN3 transits from the active state to the saturated state, and then the level of the output signal O1 stabilizes at about 0.2 to 0.5 V. At this time, in the transistor QN3, β is lowered to about 5 to 20, and even if the base current is somewhat large, it is in a sufficiently stable state with respect to the collector current determined by the power supply voltage, the resistance value of the resistor R1, and the emitter-collector voltage. Can be kept.

Next, when the input condition changes and the level of the input signal I1 becomes lower than the level of the input signal I2, contrary to the above, the base-emitter voltage of the transistor QP1 becomes larger than that of the transistor QP2, and QP1. Has a larger emitter / collector current. Therefore, if an attempt is made to cause a current having the same value as the collector / emitter current of the transistor QN1 to flow as the collector / emitter current of the transistor QN2, the collector current of the transistor QP2 is insufficient. To discharge. Therefore, the potential of the node N3, that is, the differential signal n3 decreases, and at the same time, the supply source of the base current of the transistor QN3 disappears, so that the transistor QN3 transits from the saturated state to the cutoff state, and the level of the output signal O1 is pulled up. Up resistance R
It rises due to the current supplied via 1. The level increase rate of the output signal O1 depends on the value of the resistor R1 and the output terminal T.
It changes depending on the product of the capacitance values parasitic on O1.

At this time, since the transistors QN1 and QN2 have the same base-emitter voltage but different current values supplied to their respective collectors, the transistor QN1 and QN2 are different.
The system enters a stable state when N2 becomes saturated and β becomes small and β error is large.

Further, when the input condition changes and the level of the input signal I1 becomes higher than the signal level of the input signal I2 again, the transistor QN3 becomes the same as in the first state.
Is supplied, the transistor QN3 makes a rapid transition from the cutoff state to the conduction state, rapidly lowering the level of the output signal O1 and setting the level of the output signal O1 to 0.
Stabilize at about 2 to 0.5V. The series of operations described above is repeated according to the change in the input level.

Next, referring to FIG. 4, which is a circuit diagram in which the same components as those of the conventional second comparator circuit shown in FIG. 3 are designated by common reference characters / numerals, the conventional second comparator circuit of FIG. The difference from the first comparator circuit is that the open collector type output circuit 3 is replaced by a PNP type transistor QP11.
And an emitter follower type output circuit 3A including a constant current source IS3.

In operation, the level of the output signal O1 operates so as to be higher than the potential of the node N3, that is, the differential output n3 by the base-emitter voltage of the QP11. Since the output polarity is different from that of the first comparator circuit, the relationship between the input signals I1 and I2 and the output signal O1 is reversed, but the level of the output signal O1 transits from the low level to the high level in the second comparator circuit. When this is done, the transistor QP11 is cut off and the load is charged by the constant current supplied by the constant current source IS3. When the output level reaches a high level, QP11 becomes conductive and the system becomes stable.

Next, when the level of the output signal O1 transits from the high level to the low level, the constant current source IS3 constantly supplies the current. The transistor QP11 is in a conductive state, drives the supply current of the constant current source IS3 and the discharge current from the load, and the output level drops sharply. Output signal O
When 1 becomes stable, the transistor QP1
1 is in a conductive state, and continues to supply the current of the sum of the supply current of the constant current source IS3 and the load current.

In a series of output level transition operations, in the second conventional comparator circuit, the current drivability for the output load varies depending on whether it rises from a low level to a high level or falls from a high level to a low level. It's very different.

[0016]

SUMMARY OF THE INVENTION In the above-described conventional comparator circuit, the state transition time, that is, the rising edge, of the output signals of both the first and second circuits from low level to high level and from high level to low level is raised. Since one of the slew rates at the time of falling depends on the load condition and the other depends on the drive capacity of the output transistor, the state transition of the output signal corresponding to the signal change of the input signal difference greatly differs in both transition states. It is extremely difficult to match the time, and there is a drawback that the output signal waveform is greatly distorted including the duty change.

[0017]

SUMMARY OF THE INVENTION A comparator circuit according to the present invention responds to a supplied first and second input signals of complementary signals, and first and second nodes having opposite polarities to each other. A differential circuit that generates a second differential signal; a current mirror circuit that forms an active load circuit of the differential circuit using the second node as an input end and the first node as an output end; A comparator circuit comprising an output circuit for generating an output signal in response to supply of a first differential signal, wherein the output circuit has an emitter as a first power source, a base as a first node, and a collector as an output terminal. A first transistor of a first conductivity type connected to each other, and a second transistor of a second conductivity type having an emitter connected to a second power supply, a base connected to a third node, and a collector connected to the output terminal. , The emitter is the first A third transistor of a first conductivity type having a source connected to the second node and a collector connected to the third node; and one end connected to the second power supply and the other end connected to the third node. And a first constant current source connected to each other.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Next, referring to FIG. 1, which is a circuit diagram in which components common to those of FIG. 3 are designated by common reference characters / numerals, the present embodiment shown in FIG. The comparator circuit of the example includes transistors QP3, QN3, Q in addition to the differential circuit 1 and the current mirror circuit 2 which are common to the conventional one.
Active load type output circuit 3 including N4 and constant current source IS2
Equipped with B.

In the transistor QN3 of the output circuit 3B, the collector is connected to the output terminal TO1, the base is connected to the node N3, and the emitter is connected to the power supply Vss. The transistor QP3 has the collector connected to the collector of the transistor QN3 and the output terminal T.
The base of O1 is connected to the node N4 and the emitter of the transistor QN4 is connected to the power supply Vcc. The collector of the transistor QN4 is connected to the node N4 and the base of the transistor QN4 is connected to the node V2 of the power supply Vss. The constant current source IS2 has an area, one end of which is connected to the power supply Vcc and the other end of which is connected to the node N4, and supplies a constant current twice as high as that of the constant current source IS1.

Next, the operation of this embodiment will be described with reference to FIG.
Is large enough. First, the operations of the differential circuit 1 and the current mirror circuit 2 are the same as in the conventional case, and when the input signal I1 is higher than the signal I2, the transistors QP2 and
The difference current between the collector currents of QP1, that is, the differential signal n3 is supplied as the base current of the transistor QN3 of the output circuit 3. As a result, the transistor QN3 becomes conductive, and the level of the output signal O1 decreases by taking in (short-circuiting) the current from the external load via the output terminal TO1. On the other hand, since the transistor QN4 forms a current mirror circuit with the transistor QN1, it tries to flow twice the collector current of the transistor QN1 corresponding to the double emitter area. At the node N4, since the supply current from the constant current source IS2 is larger than the collector current of the transistor QN4, the potential rises, and the potential difference between the emitter and the base of the transistor QP3 is reduced. As a result, the transistor QP3 is turned off. For this reason,
In this case, the load current drive capability of the output circuit 3B becomes the drive capability of the transistor QN3, which is β times the differential signal n3 supplied as the base current.

As a result, the output signal O of the output terminal TO1
A level of 1 drops rapidly. When the level of the output signal O1 reaches 0.6V to 0.5V or less, the transistor QN3
Is saturated and depends on the saturation voltage 0.5 to 0.2
A stable state is reached at a value of about V.

Next, when the input signal I1 becomes lower than the signal I2, the collector current distribution of the transistors QP1 and QP2 reverses, the potential of the difference signal n3 decreases, and the transistor QN3 in the saturated state passes the reverse recovery time. , Transition to the cutoff state. Further, the transistor QN4 supplies a current twice as large as the collector current of the increased transistor QP1, and since its magnitude is larger than the supply current of IS2, the potential of the node N4 drops due to discharge and is in the cutoff state. The transistor QP3 is supplied with the base current and transits to the conductive state. The level of the output signal O1 rises in response to the driving of the collector current of the transistor QP3.

The level of the output signal O1 rises and the power source V
When the voltage reaches a level about 0.6 to 0.5 V lower than cc, the transistor QP3 makes a transition to a saturated state, and the output signal O
The level of 1 is lower than the power supply Vcc by the saturation voltage (0.5 to 0.2V) of the transistor QP3, and is in a stable state.

When the levels of the input signals I1 and I2 further change and the level of the signal I2 falls below the level of the signal I1 again, the transistor QP3 changes from the saturation state to the cutoff state after a reverse recovery time, and the transistor QN3 changes from the cutoff state. By transiting to the saturated state after passing through the conductive state,
The level of the output signal O1 stabilizes at the saturation potential of the transistor QN3.

After that, a series of operations are repeated with a change in the input signal.

The load driving capability of the comparator circuit of this embodiment is β times that of each of the transistors QP3 and QN3 of the output circuit with respect to the differential output current value of the differential circuit, and PN
By matching the characteristics of the P and NPN transistors, it is possible to easily obtain the matching of their driving capabilities.

The load capacitance of the output terminal O1 is 20 pF and the currents of the constant current sources IS1 and IS2 are 100 μA and 200 μ, respectively.
With A and R1 set to 5 KΩ, the characteristics of the present embodiment and the conventional comparator circuit will be described with reference to FIGS. 2A and 2B, which are characteristic diagrams showing operation simulation waveforms of the present embodiment and the conventional comparator circuit, respectively. Comparing with each other, the signal transmission delay from the input signal transition to the output signal transition of each of the present embodiment and the conventional circuit is 1 at the fall time.
The values are 8.0 ns and 17.5 ns, and are 32.5 ns and 72.5 ns at the same rise, respectively. Taking the ratio of the rising and falling state transition times, 1.8 and 4.1 are obtained in each of the present embodiment and the conventional circuit.
It can be seen that the circuit of the present embodiment is more consistent in the rise and fall operation delay times. Further, as described above, the slew rate at the time of the output transition of the conventional circuit is largely different between the rising edge and the falling edge, and the output signal corresponding to the signal change of the input signal difference is integrated with the deviation of the signal delay time. Although the waveform was greatly distorted, the comparator circuit of the present embodiment has a small difference in slew rate between the rising time and the falling time, and by easily matching the delay time of the circuit, The duty of the output signal waveform corresponding to the signal change of the input signal difference hardly changes and the distortion is small.

Therefore, the comparator circuit of this embodiment is most suitable for the zero-cross comparator which extracts the crossing points of the input signal levels by matching the time delays.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made. For example, even if the polarity of the transistor of this embodiment is inverted, the same effect can be obtained by inverting the polarity of the input signal, as a matter of course, without departing from the gist of the present invention.

[0030]

As described above, in the comparator circuit of the present invention, the output circuit includes the first transistor of the first conductivity type having the base connected to the first node and the collector connected to the output terminal, and the emitter. The second power supply to the base to the third
Second conductive type second transistor in which the collector is connected to the output terminal and the third conductive type third transistor in which the base is connected to the second node and the collector is connected to the third node And a first constant current source for supplying a constant current to the third node, the difference in slew rate between rising and falling is small and it is easy to match the delay time of the circuit. By taking advantage of this, there is an effect that the duty of the output signal waveform corresponding to the signal change of the input signal difference is hardly changed and the distortion is also reduced.

Further, since the output drive capacity can be made large,
The output slew rate is large, and there is an effect that excellent output characteristics can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a comparator circuit of the present invention.

FIG. 2 is a characteristic diagram showing an example of respective simulation waveforms of operations of the present embodiment and the conventional first comparator circuit.

FIG. 3 is a circuit diagram showing a first conventional comparator circuit.

FIG. 4 is a circuit diagram showing a second conventional comparator circuit.

[Explanation of symbols]

1 differential circuit 2 current mirror circuit 3, 3A, 3B output circuit QN1 to QN4, QP1 to QP3, QP11 transistor

Claims (3)

[Claims] 1. A difference for generating first and second differential signals having mutually opposite polarities at first and second nodes in response to supplied positive and complementary first and second input signals. A dynamic circuit, a current mirror circuit that forms an active load circuit of the differential circuit using the second node as an input end and the first node as an output end, and responds to the supply of the first differential signal. An output circuit for generating an output signal according to the first conductivity type, wherein the output circuit has an emitter connected to a first power source, a base connected to the first node, and a collector connected to an output terminal. A second transistor of a second conductivity type, in which an emitter is connected to a second power source, a base is connected to a third node, and a collector is connected to the output terminal.
A first conductive type third transistor having an emitter connected to the first power source, a base connected to the second node and a collector connected to the third node, and one end of the second power source. And a first constant current source having the other end connected to the third node, respectively. 2. A second constant current source, one end of which is connected to the second power source and the other end of which is connected to a fourth node, and the differential circuit, wherein the respective emitters are commonly connected to each other and the fourth contact point is formed. Each base is connected to the first and second signals corresponding to the first and second signals, respectively.
Each of the collectors is connected to the input terminals of
Second conductive type fourth and fifth transistors respectively connected to the contacts of the current mirror circuit, the current mirror circuit commonly connecting the collector and the base, and the emitter to the second contact. A sixth transistor of a first conductivity type connected to a power source, a collector connected to the first contact, a base connected to the second contact and an emitter connected to the first power supply, and 7. The comparator circuit according to claim 1, further comprising a seventh transistor of the first conductivity type having the same characteristics and the same emitter area. 3. The fourth transistor comprises an emitter having an emitter area twice as large as the emitter area of the sixth transistor, and the first constant current source is twice as large as the second constant current source. The comparator circuit according to claim 1, wherein the comparator circuit supplies a current.