JPH08204150A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PURPOSE: To realize a cylindrical stuck condenser with a sidewall for securing a large condenser in a small area in a DRAM as well as enlarging focus margin in the case exposing the contact hole. CONSTITUTION: After leaving a photoresist film 12 only on the bottom part of a contact hole by performing the whole surface exposure using the adjusted exposure level, the second polycrystalline silicon film 11B is etched back to form the first sidewall 11B and the second sidewall 11Bb. Through these procedures, a cylindrical stuck condenser with a sidewall can be realized. Besides, due to the existence of a glare shielding film made of a silicon dioxide films in the exposure time of a contact hole, the focus margin can be enlarged compared with the time when a polycrystalline silicon film is existent of the surface.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a stack type dynamic RAM and its manufacturing method.

[0002]

2. Description of the Related Art In recent years, with the high integration of LSIs, the capacitor area for accumulating charges has become smaller and smaller.
It is difficult to obtain sufficient capacity to withstand soft errors. In order to increase a capacitor area per unit occupied area, a memory cell having a stack structure with a sidewall or a cylindrical stack structure has been proposed.

First, a stack type dynamic RAM with sidewalls will be described with reference to FIGS.
First, as shown in FIG. 4A, a field oxide film 2 having a thickness of 400 nm is formed on the surface of a P-type silicon substrate 1 by a selective oxidation method to partition an active region. Next, the gate oxide film 3 is formed on the surface of the active region to form the gate electrode 4G and the source / drain regions 5-1 and 5-2. 4W is a gate electrode wiring forming a part of the adjacent word line.
Next, after depositing a BPSG film 6 having a thickness of 800 nm,
Type impurity diffusion layer (one of source / drain regions 5-2)
Then, a contact hole 9 of about 0.5 μm square is formed. Next, a first polycrystalline silicon film 7 having a thickness of 400 nm and a silicon dioxide film 8 having a thickness of 100 nm are sequentially deposited. Next, the first polycrystalline silicon film 7 and the silicon dioxide film 8 are patterned by using the lithography technique. The silicon dioxide film 8 is an antiglare film that reduces the adverse effect of reflection from the surface of the polycrystalline silicon film during exposure with i-line having a wavelength of 365 nm. That is, the patterning accuracy is improved as compared with the case where the silicon dioxide film 8 is not provided. Here, the antiglare film is for reducing reflection at the interface when the photoresist film is directly provided on the polycrystalline silicon film, and ideally an antireflection film is preferable,
Due to various material restrictions, it is not always necessary to prevent reflection.

Next, as shown in FIG.
A 0 nm second polycrystalline silicon film 11 is deposited. Next, the second polycrystalline silicon film 11 is selectively removed by anisotropic reactive ion etching by anisotropic etching to form a side wall 11a as shown in FIG. 4C.
In this case, overetching can be avoided by detecting the etching end point of the silicon dioxide film 8 by a spectroscopic analysis method or the like. Next, as shown in FIG. 5, a dielectric film 12 is formed and an upper electrode (cell plate 13) made of a polycrystalline silicon film is formed.

Next, a cylindrical stack type dynamic RA
M will be described with reference to FIGS. 6 and 7. Figure 6 (a)
As shown in, until the BPSG film 6 is deposited,
This is similar to the case of the stack type dynamic RAM with sidewall. Next, a first polycrystalline silicon film 7A having a thickness of 300 nm is deposited. Next, the N-type impurity diffusion layer (5-
A contact hole 9 of about 0.5 μm square reaching 2) is opened.

Next, as shown in FIG. 6B, the thickness 100
A second polycrystalline silicon film 11A having a thickness of nm is deposited.

Next, as shown in FIG. 7A, patterning is performed by using the lithography technique to complete the formation of the lower electrode of the capacitor. Next, as shown in FIG. 7B, the dielectric film 12 is formed and the cell plate 13 is formed.

Incidentally, the term cylindrical shape is not correct in a strict sense. Although it should be referred to as a pipe type with one end closed, it will be referred to as a cylindrical type here according to the convention.

[0009]

In the above-described stack structure with sidewalls, the distance between the lower electrodes of the capacitors of the adjacent memory cells (d in FIG. 4C) is set so that the thickness of the side wall 11a is smaller than the limit resolution of lithography. Since it can be made twice as narrow, the capacitor area can be increased. However, since the lower electrode completely fills the contact hole, the capacitance value per occupied area of the semiconductor substrate does not become large as compared with the cylindrical stack structure.

Further, in the cylindrical stack structure, the inner wall portion of the contact hole positively contributes to the capacitance value, so that the capacitance value per occupied area can be increased. Further, since there is a polycrystalline silicon film having a high reflectance at the time of exposure for forming a contact hole, the size of the contact hole will vary due to the influence of reflected light unless focusing is performed accurately, and the focus margin becomes narrower. There are obstacles to manufacturing with good reproducibility. This problem can be prevented by forming the contact hole after covering the first polycrystalline silicon film 7A with an antiglare film such as a silicon dioxide film having a thickness of 100 nm. However, if so, the thickness of the lower electrode on the BPSG film is a silicon dioxide film (does not contribute to the capacitance value).
It cannot be used because the thickness increases, the step difference between the memory cell portion and the peripheral circuit portion increases, and it becomes difficult to form the aluminum-based wiring in the subsequent step.

By the way, it is easily conceived that the capacitance value can be increased if a cylindrical capacitor with a sidewall can be realized. Therefore, let's first consider making a cylinder with sidewalls as the starting point. First,
It is necessary to reduce the thickness of the first polycrystalline silicon film 7 so as not to fill the contact hole. Then, even if the side wall 11a can be provisionally formed, its height becomes low. Will end up. Another problem is how to form an antiglare film for avoiding the bad influence of the high reflectance of the polycrystalline silicon film.

Next, considering adding a sidewall to the cylindrical shape, for example, a first polycrystalline silicon film is formed, a contact hole is formed, and further patterned, and then a second polycrystalline silicon film. Can be formed by depositing and anisotropically etching. In that case, the problem of the reflectance of the polycrystalline silicon film is to leave holes, and it is necessary to take measures to prevent the N-type diffusion layer (5-2) from being exposed and damaged at the bottom of the contact hole.

Therefore, it is an object of the present invention to provide a semiconductor device having a capacitor having both advantages of a side wall and a cylindrical type, and a manufacturing method capable of realizing the same with good reproducibility.

[0014]

According to the present invention, there is provided a semiconductor device comprising:
On a contact hole provided from the surface of the insulating film on the second conductivity type semiconductor substrate having the first conductivity type impurity diffusion layer selectively formed on the surface to the first conductivity type impurity diffusion layer. A ring-shaped conductor formed of a first conductive film having an opening connected to the ring-shaped conductive film and covering the surface of the insulating film around the contact hole, and a second conductive film covering the outer peripheral side surface of the ring-shaped conductive body. And a first sidewall covering the bottom surface of the contact hole, and a pipe-shaped second portion covering the side surface of the contact hole and the side surface of the opening of the annular conductor. A stack type capacitor having a lower electrode composed of a second side wall made of a film is provided.

Here, each of the first, second and third conductive films can be, for example, a first conductivity type polycrystalline silicon film.

The semiconductor device manufacturing method of the present invention is
A first insulating film, a first conductive film, and a second insulating film serving as an antiglare film at the time of exposure are sequentially formed on a semiconductor substrate having a first-conductivity-type impurity diffusion layer selectively formed on the surface thereof. After being deposited on the second layer, the second layer is formed by photolithography technique.
An opening and a contact hole are formed in the first conductive film and the first insulating film, respectively, by forming a through hole from the surface of the insulating film to the impurity diffusion layer of the first conductivity type. A step of removing the second insulating film and the first conductive film in a region surrounding the outside of the through hole to form a ring-shaped conductive film; and a second step having a thickness such that a groove corresponding to the through hole remains A conductive film is deposited on the entire surface, a photoresist film is formed, and the entire surface is exposed and developed to leave a predetermined amount in the groove portion to form an etching mask, and the second conductive film is selectively etched by anisotropic etching. By removing the second insulating film and the etching mask, the first side wall covering the outer peripheral side surface of the annular conductor and the contact hole are removed. Forming a first part covering the surface and a second side wall having a pipe-shaped second part covering the side surface of the contact hole and the side surface of the opening of the annular conductor. It has a step of forming a lower portion.

Here, both the first and second conductive films can be, for example, a first conductive type polycrystalline silicon film, and the second insulating film can be a silicon oxide film.

[0018]

The lower electrode includes an annular conductor having an opening above the contact hole, a first side wall (sidewall) covering the outer peripheral side surface of the annular conductor, and a second side wall covering the inner wall of the contact hole. Therefore, the surface area can be made the same as that of the conventional cylindrical lower electrode having the first side wall on the outer circumference.

Since the surface of the first conductive film is covered with the antiglare film made of the second insulating film, the contact hole is formed and patterned, the influence of reflected light at the time of exposure can be reduced. Furthermore, after forming an etching mask in the groove portion and performing anisotropic dry etching to form the first and second side walls, the second conductive film can be left on the bottom surface of the contact hole. In addition, the second conductive film can be left by this anisotropic dry etching. Further, not only can the second insulating film be removed by this anisotropic dry etching, but also by detecting the etching end point of this second insulating film, it is possible to avoid the height of the side wall being lowered due to overetching. it can.

[0020]

The present invention will be described below with reference to the drawings.

1 (a) to 1 (c) and FIG. 2 are vertical cross-sectional views of a semiconductor chip showing the order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1A, the surface of the P-type silicon substrate 1 is formed to a thickness of 400 n by using a selective oxidation method.
A field oxide film 2 of m is formed to define an active region. Next, a gate oxide film 3 is formed on the surface of the active region, a polycrystalline silicon film, a polycide film, etc. are formed and patterned to form a gate electrode 4G and a gate electrode wiring 4W.
To form. Here, it is called a gate electrode on the active region,
The portion extending on the field oxide film is called a gate electrode wiring. These are part of the word line. The illustrated 4G and 4W belong to adjacent word lines. Next, source / drain regions 5-1 and 5-2 (N-type impurity diffusion layers) are formed by utilizing the ion implantation method. Next, after depositing a 800 nm-thick BPSG film 6, a 400-nm-thick first N-type doped polycrystalline silicon film 7B is deposited. Next, a 100 nm thick silicon dioxide film is deposited. Next, a through hole 9A of about 0.5 μm square is formed to reach the N-type diffusion layer 5-2.
Here, the portion of the through hole below the BPSG film 6 will be referred to as a through hole 9A-1, and the portion of the first polycrystalline film 7B will be referred to as an opening 9A-2. In the photolithography process using the i-line for forming the through hole 9A, the photoresist film is exposed in the state where the surface of the first polycrystalline silicon film 7B is covered with the antiglare film (8). It is possible to avoid narrowing the margin.

Next, as shown in FIG. 1B, the silicon dioxide film 8 and the first polycrystalline silicon film 7B are patterned by using a lithographic technique to form an annular conductor 7B.
a is formed. Also at this time, since the silicon dioxide film 8 acts as an antiglare film, accurate patterning can be performed.

Next, after depositing a second polycrystalline silicon film 11B doped with N type having a thickness of 100 nm, a photoresist film is formed by a coating method, the exposure amount is adjusted, and the entire surface is exposed. A photoresist film having a thickness of about 500 nm is left as the etching mask 12 only on the bottom of the groove 10 corresponding to the through hole 9A. Subsequently, the second polycrystalline silicon film 8 and the silicon dioxide film 8 are removed by anisotropic etching (reactive ion etching using a mixed gas of HBr and Cl ₂ ), as shown in FIG. So that the first side wall 11Ba and the second side wall (11Bb-1,
11Bb-2) is formed. The end point of this etching is detected by spectroscopic analysis, for example, by detecting the light emitted when Si is etched. This emission intensity is second
Of the polycrystalline silicon film 11B becomes strong when it is etched, becomes weak when the silicon dioxide film 8 starts to be etched, and becomes strong again when the first polycrystalline silicon film 7B starts to be etched. Etching may be stopped at this point. In this way overetching can be minimized. Also, the groove 10
Since the etching mask 12 is at the bottom of the contact hole, the second polycrystalline silicon film at the bottom of the contact hole remains without being etched back. Next, the photoresist film (12) is peeled off.

Next, as shown in FIG. 2, a dielectric film 12 is formed and a cell plate 13 is formed.

The semiconductor device thus formed has the N-type impurity diffusion layers 5-1 and 5 selectively formed on the surface thereof.
-9 on the contact hole 9A-1 which is provided from the surface of the BPSG film 6 on the P-type silicon substrate 1 having the -2 to the N-type impurity diffusion layer 5-2 and which is connected therewith.
BPSG film 6 around the contact hole 9A-1
An annular conductor 7Ba made of a first polycrystalline silicon film that covers the surface of the first conductive film, and a first sidewall 11Ba made of a second polycrystalline silicon film that covers the outer peripheral side surface of the annular conductor 7Ba,
Third polycrystalline silicon having a first portion 11Bb-1 covering the bottom surface of the contact hole 9A-1 and a pipe-shaped second portion 11Ba-2 covering the side surface of the contact hole 9A-1 and the annular conductor 7Ba. A stack type capacitor having a lower electrode composed of a second side wall made of a film is provided.

The increase in the capacitance value of this embodiment will be described in comparison with the conventional example. FIG. 3 is a perspective view for estimating the area (capacitor area) that contributes to the capacitance value of the lower electrode of various capacitors.

In the simple stack type (without side wall 11a in FIG. 5), the area of the bottom surface minus the surface area of the rectangular parallelepiped shown in FIG. 3 (a) is the capacitor area, which is 4.4 μm.
It becomes m ² . In the cylindrical type (FIG. 7 (b)), as shown in FIG. 3 (b), the area of the side surface of a prism having a size of 0.3 μm square and a height of 1.1 μm is added to give a total of 5.92 μm ² . With sidewalls (Fig. 5), as shown in Fig. 3 (c),
If the thickness of the side wall is 0.1 μm, it will be 5.36 μm ² . In the present embodiment, as shown in FIG. 3D, the area of the side surface of a prism having a size of 0.3 μm square and a height of 1.1 μm of 1.52 μm ² is added, resulting in 6.85 μm ² . This is 1.28 times that with a sidewall, 1.1 of a cylindrical type.
It is 6 times.

The example in which the silicon dioxide film is removed by the anisotropic etching for forming the first and second sidewalls has been described above. This anisotropic etching may be stopped when the surface of the silicon dioxide film 8 is exposed, and then the silicon dioxide film may be selectively etched. Then,
Since it is possible to form the first and second sidewalls extending upward by about 100 nm from the surface of the annular conductor 7Ba, it is advantageous to increase the capacitance value.

As the antiglare film, a titanium nitride film can be used in addition to the silicon dioxide film. As the first and second conductive films, a polycrystalline silicon film and a refractory metal film such as a tungsten or molybdenum film can be used.

As described above, since the semiconductor device according to the present invention has the cylindrical stack type capacitor with the sidewall, it is possible to increase the capacitor area and to obtain a sufficient capacitor capacity even with a small surface area. Therefore, a DRAM that is resistant to soft errors can be obtained.

Further, in the method of manufacturing a semiconductor device according to the present invention, since the surface of the first conductive film is covered with the antiglare film during exposure when forming the annular conductor of the contact hole, the focus margin is expanded. Alternatively, accurate patterning is possible, and uniform capacitors can be formed with good reproducibility. This antiglare film can be used for detecting the end point of the reactive ion etching for forming the first and second side walls.
Further, since the bottom surface of the groove corresponding to the contact hole is protected by the etching mask made of the photoresist film during this etching, it is possible to prevent the first conductive film impurity diffusion layer from being damaged. As described above, the method of manufacturing a semiconductor device of the present invention has an effect of effectively using the antiglare film to obtain a semiconductor device such as a DRAM having a cylindrical stack structure capacitor with a sidewall with good reproducibility.

[Brief description of drawings]

1A to 1C are cross-sectional views in order of steps, which are divided into (a) to (c) for describing an embodiment of the present invention.

FIG. 2 is a cross-sectional view shown subsequent to FIG.

FIG. 3 is a perspective view for estimating a capacitor area of various capacitors.

4A to 4C are cross-sectional views in order of the processes, which are divided into (a) to (c) for illustrating a DRAM having a stack structure with sidewalls.

5 is a cross-sectional view shown subsequent to FIG.

FIGS. 6A to 6C are sectional views in order of the processes, which are divided into FIGS. 6A and 6B for explaining a cylindrical stack structure DRAM; FIGS.

FIG. 7 is a sectional view in order of the processes, which is divided into (a) and (b) subsequent to FIG. 6;

[Explanation of symbols]

1 P-type silicon substrate 2 Field oxide film 3 Gate oxide film 4G Gate electrode 4W Gate electrode wiring 5-1 and 5-2 Source / drain region (N-type impurity diffusion layer) 6 BPSG film 7, 7A, 7B Crystal silicon film 8 2 Silicon oxide film 9,9A-1 Contact hole 9A Through hole 9A-2 Opening 10 Groove 11, 11A, 11B Second polycrystalline silicon film 11a Side wall (side wall) 11Ba First side wall 11Bb-1 First part of second sidewall 11Bb-2 First part of second sidewall 12 Dielectric film 13 Cell plate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/822

Claims (4)

[Claims] 1. A first conductive type impurity diffusion layer is provided from the surface of an insulating film on a second conductive type semiconductor substrate having a first conductive type impurity diffusion layer selectively formed on the surface thereof. A ring-shaped conductor made of a first conductive film having an opening connected to the contact hole and covering the surface of the insulating film around the contact hole; and a ring-shaped conductor covering the outer peripheral side surface of the ring-shaped conductor. A first side wall of the second conductive film, a first portion covering the bottom surface of the contact hole, and a pipe-shaped second portion covering the side surface of the contact hole and the side surface of the opening of the annular conductor. A semiconductor device comprising: a stack type capacitor having a lower electrode composed of a second side wall of the third conductive film. 2. The semiconductor device according to claim 1, wherein each of the first, second and third conductive films is a first conductivity type polycrystalline silicon film. 3. A first insulating film, a first conductive film, and a second anti-glare film at the time of exposure on a semiconductor substrate having a first conductivity type impurity diffusion layer selectively formed on its surface portion. Second insulating film is sequentially deposited, and then a through hole reaching from the surface of the second insulating film to the first conductivity type impurity diffusion layer is formed by photolithography.
An opening and a contact hole are formed in the conductive film and the first insulating film, respectively, and the second insulating film and the first insulating film in the region surrounding the outside of the through hole are formed by a lithography technique.
And removing the conductive film to form a ring-shaped conductive film, and depositing a second conductive film having a thickness such that a groove corresponding to the through hole remains, forming a photoresist film and exposing the whole surface. By developing, a predetermined amount is left in the groove to form an etching mask, and the second conductive film is selectively removed by anisotropic etching to remove the second insulating film. By removing the mask, the first side wall covering the outer peripheral side surface of the annular conductor, the first portion covering the bottom surface of the contact hole, the side surface of the contact hole and the side surface of the opening of the annular conductor are removed. Manufacturing a semiconductor device, characterized in that it has a step of forming a lower portion of the stack type capacitor by a step of forming a second side wall having a pipe-shaped second portion for covering. Law. 4. The first and second conductive films are both first
4. The method of manufacturing a semiconductor device according to claim 3, wherein the conductive type polycrystalline silicon film is used, and the second insulating film is a silicon oxide film.