JPH08204128A - Multifuction lsi device and function switching method as well as processing system thereof - Google Patents

Abstract

PURPOSE: To realize a multifuctional LSI device having excellent mass productivity capable of dissolving pin necks. CONSTITUTION: Pins IS0-ISn are commonly used for the input of function circuits 1-4 while the output is connected to other pins OS0-OSm through the intermediary of a multiplexer 5 controlled by the selective signals from the selective singnal pins ISEL0, ISEL1. Accordingly, both input/output pins do not cause any pin necks capable of commonly used in respective function circuits at all by selecting only one function circuit by the multiplexer 5. Simultaneously, since one arbitrary function can be selectively used, the use of the same chip cam be increased thereby increasing the mass production effect.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-function LSI device, a function switching method thereof, and an arithmetic processing system using the LSI device.

[0002]

2. Description of the Related Art FIG. 2 shows a function distribution structure in a general electronic circuit system. Since any system basically has a hierarchical functional structure, the functional distribution progresses toward the lower levels of the hierarchical structure, and the coupling between functional circuits becomes coarse. Instead, the number of function input / output signals for providing the dedicated function to the outside tends to increase. For example, taking an intelligent system having a CPU as an example, in FIG. 2, an external circuit A is a CPU / signal / bus interface circuit directly connected to the CPU, and an external circuit B is a device directly managed by the CPU, an external circuit. C is a memory system, system I / O circuit, external circuit D
Is an I / O channel or a common I / O driver or interface, and the external circuit E is a system bus or a common bus interface.
It corresponds to a face circuit or the like. In such a system, the functional circuit 302 is a memory controller or an input / output controller, the functional circuits 303 and 304 are I / O channel controllers or shared I / O bus controllers, and the functional circuit 305 is a system. The functions are shared by the bus or common bus controller. The common circuit unit 301 is a CP
This is a part that monitors the operation of U and generates a signal that is commonly used in each functional circuit, and that also generates a signal that is fed back to the operation of the CPU from each functional circuit in an integrated manner. A machine state controller (MSC) that manages and monitors bus cycles and generates basic reference signals and clocks, and a clock generator (CLKGT) that generates various system clocks and various clocks for each functional circuit. ) Etc.

Conventionally, the circuit system shown in FIG.
Functional circuits 302 to 305 and the common circuit 30
1 to 4 to 5 each (in the case of four, the common circuit unit is
It is designed as a heterogeneous LSI (embedded in SI), or the entire system of FIG. 3 is integrated as one large-scale LSI.

[0004]

In the above-mentioned conventional technique, when an electronic board or system is constructed, if the LSI is formed for each required functional circuit, the number of types of the LSI is increased and a considerable mass production is possible. There has been a problem that it is possible to realize an LSI at low cost only for applications. In some cases, a plurality of function modes may be incorporated in a one-chip LSI, and one of the functions may be selected from a plurality of modes. Such functions are fixed to one. Then, it is used by connecting to other circuit blocks on the electronic board by one predetermined connection method for each functional block,
Even if there are some variations due to differences in local connections, basically only one usage method or mounting method is allowed, and it is possible to solve the problem of cost reduction in low-volume production type applications. Not a thing.

On the other hand, when a system (on-chip) approach is adopted in which a plurality of related functions (systems) are integrated in a large-scale one-chip LSI, the yield and design cost are reduced due to the large scale. Together with the rise, the pin neck problem detailed below arises. Figure 3 shows the LSI
An example of the process improvement of the (CMOS gate array) will be shown. It is assumed that the die size (size of the circuit integrated portion of the LSI) in both cases is the same (about 2.5 mm × 2.5 mm), and the 2 μm process rule shown in FIG. It is said that the process is improved to the 1 μm process rule in (1). The process improvement ratio, which is the ratio of miniaturization of the wiring rule, is 2 in this case. As a result, the number of transistors is improved four times. That is, in each case, about 64 gates and CMs are placed in an area for one square on the die.
In the OS process, about 260 transistors are integrated, and the number of transistors is 16 in the case of 2 μm rule and 64 in the case of 1 μm rule. However, the number of signal pads for extracting the function pins for external input / output is 44 pads in the 2 μm rule of FIG.
With 1 μm rule of (b), it has 60 pads, which is about 1.
It is only about four times as large. The first reason for this is that since the transistors are arranged in a plane, the rate of increase is proportional to the square of the process improvement ratio, whereas the signal pads are arranged linearly, so the rate of increase is almost the same. This is because it is proportional to the improvement ratio. As a second reason,
The process improvement ratio is smaller than 2 because the current (instantaneous current) capacity required to drive a load (mainly a capacitive load) connected to the outside is higher than the switching characteristic due to the increase in the switching speed of the signal. This is because the rate tends to be the same or larger because the rate becomes higher, and the signal pad size cannot be reduced so much due to the limit of the current density of the pad.

However, it is empirically known that, when integrating random logic, the number of pins required increases substantially in proportion to the number of transistors, and thus the number of transistors and the number of external input / output pins are increased. An imbalance will occur. This means that unless a large number of memory circuits or the like are integrated, the number of input / output pins is significantly short in a circuit mainly composed of random logic. That is, in order to secure a large number of function pins, it is necessary to use a chip size (die size) that is considerably larger than the circuit scale to be integrated in the LSI, which also causes an increase in development cost and a decrease in yield. Invite. That is, there is a high possibility that the cost reduction will be caused in the case of using the LSI in the small-quantity production system.

To solve this, for example, four functional circuits (Functions) which require external input / output signals of about 40 to 50 pins on a scale of 1000 gates are prepared, and 4000 gates are provided.
Let us consider the case of integration in a CMOS gate array of a large scale. If you try to integrate this into one chip as usual,
In order to secure the required number of signal pads of 160 to 200 pins, C using a process of 1 μm rule
A MOS gate array with a large die size of 10,000 gates is required, which is much larger than the die size determined by the required number of gates.

An object of the present invention is to provide a multi-function LSI device in which a large number of external input / output pins of the LSI can be secured and a pin neck does not occur while the development cost of the LSI and the manufacturing cost in mass production are kept low, and the same. It is to provide a function switching method and an arithmetic processing system using this multifunction LSI device.

[0009]

According to the present invention, there are provided a plurality of pins for external connection, a plurality of functional circuits, a selection signal input circuit for inputting a selection signal for selecting the functional circuits, and the selection signal. Disclosed is a multi-function LSI device comprising: a switching circuit for connecting one or both of an input terminal and an output terminal of a selected functional circuit to a part of the pin.

Further, according to the present invention, the switching circuit connects the output terminal of the functional circuit selected by the selection signal to a part of the pin, and the other part of the pin is for common input. Multi-function LSI characterized by being connected to the input terminals of all functional circuits as pins
A device is disclosed.

Further, the present invention discloses a multi-function LSI device in which the switching circuit is a bidirectional buffer group which is connected to a part of the pins and whose signal transmission direction can be switched bidirectionally. To do.

Further, the present invention discloses an arithmetic processing system constituted by using the above-mentioned multifunction LSI device.

[0013]

By using the switching circuit, the input / output pins can be shared by a plurality of functional circuits, the pin neck can be eliminated, and the number of pins can be small, so that the package cost can be reduced. The development cost is L
It is sufficient to manufacture one SI, and the amount of circuit design is almost the same as the case of a chip with individual functions, but the initial manufacturing cost can be kept very low and any of multiple functions can be used. High mass productivity can be secured, and the cost per chip can be kept low. Therefore, if an arithmetic processing system is configured using this LSI device, the system price can be reduced.

[0014]

EXAMPLES The present invention will be described in detail below with reference to examples. FIG. 1 shows a multifunction LSI according to the present invention.
FIG. 1 is a block diagram showing an embodiment of an apparatus, in which four functional circuits (Functions 1 to 4 are C of 1 μm rule).
This is a gate array of 1000 gate scale manufactured by MOS process, totaling 4000 gate scale). The input pins IS0 to ISn are connected to the input terminals I of the respective functional circuits 1 to 4 via the signal input buffer group 7, and the respective functional circuits 1
Output terminals O of 4 to 4 are connected to output pins OS0 to OSm through a multiplexer 5 controlled by a selection input buffer group 6 and a signal output buffer group 8.

In this configuration, the multiplexer 5 has a selection signal applied to the selection pins ISEL0 and ISEL1 (hereinafter, this signal is also attached to the pins ISEL0 and ISEL).
EL1 is enclosed in () (ISEL0), (ISEL
1) etc. The output pins OS0, OS1, ---, and OSm are switched to which output of the functional circuits 1 to 4 is connected according to (the same applies to other pins). That is, the signals generated from the selection signals (ISEL0, ISEL1) input from the outside are input to the selection input terminals A and B of the multiplexer 5, and the signals from the output terminals O of the functional circuits 1 to 4 are input. It is input to the input terminals ID0 to ID3. Then, the output signal from the output terminal O of the functional circuit corresponding to the selection signal (ISEL0, ISEL1) is selected, and the output terminal OD is selected.
Output to.

On the other hand, the external input signals input from the input pins IS0 to ISn are commonly used as an input signal group having the functions defined respectively corresponding to the functional circuits 1 to 4. That is, although described and arranged like a common signal on the circuit, each of the functional circuits 1 to 4 is recognized and processed as a different function (function corresponding to each function). Therefore, when the multiplexer 5 selects the output signal to be output to the outside, it is inevitably set to the function related to those functions, that is, the function of the input signal corresponding to the selected functional circuit.

Examining the pins in this embodiment,
The conventional technique of mounting 4000 gates on one chip and connecting to input / output pins without using a multiplexer required about 160 pins or more. However, in the die size mounting 4000 gate scale, only 60 to 70 signal pads were provided. However, according to the present embodiment, it is sufficient if there are the maximum number of pins required for each of the circuits 1 to 4 to have four functions for both input and output pins. This is 1000 gates as described in the conventional example. 40 in a large-scale gate array
It has about 50 pins. Therefore, it is sufficient to have 60 to 70 signal pads which can be secured in a die size capable of mounting 4000 gates, and can be sufficiently realized even if pads for selection signals (ISEL0, ISEL1) are added.

Thus, according to the present embodiment, the pin neck is eliminated and the four functional circuits are integrated into an LSI to reduce the development cost. In addition, a large die is not necessary, and since it has multiple functions, the amount of production is increased by that amount and the mass production effect is improved. Further, the package can be of a standard level with a small number of pins, and the package cost can be kept very low.

FIG. 4 is a block diagram showing another embodiment of the multifunction LSI device according to the present invention. In the embodiment of FIG. 1, the input buffer group 7 and the output buffer group 8 are fixed, so that the number of input signal pins and the number of output signal pins are both constant, and therefore the number of external input / output signals is substantially the same. It was necessary to design such a functional circuit to be incorporated in one chip. In the present embodiment, even if the number of input / output signals is different for each functional circuit, the bidirectional input / output buffer is used for control by the selection signal, so that the physical number of input / output buffers is not so limited. The multi-function LSI device can be designed.

Multifunction LSI shown in FIG.
The device has five functional circuits (Functions) with different functions.
n) 401 to 405 and selection signals (ISEL0, ISEL1, I) input via the selection input buffer group 409.
SEL2 / IS) multiplexers 406 to 408 controlled by three inputs, and signal input / output buffer groups 411 and 413 also controlled by the above three inputs, each having m + 1 and k + 1 input / output terminals, The LSI is composed of a signal input buffer group 410 having n + 1 input terminals and a signal output buffer group 412 having j + 1 output terminals, and when viewed from the outside, it is an LSI that can be transformed into five types of LSI in one chip.

The operation of this embodiment will be described below. First, the selection signals (ISEL1, ISEL0) are (0, 0),
When (0, 1) or (1, 0), the functional circuit 401, 402, or 403 is selected in this order. At this time, the signal (ISEL2 / IS) is the functional circuit 40.
It is assigned as one of the input signals 1 to 403. Also, under this condition, the output of the AND gate 414 is always "0", so the enable input E that is input through the inverters 415 and 416 and activates the output buffer 4110 of the signal input / output buffer group 411 is "0".
Then, the output buffer 4110 is fixed in a disable state, that is, a high impedance output state, and the functional circuits 401 to 403 regard the buffer group 411 as an input buffer group and input signals from them are input to each input terminal I.
Take in.

On the other hand, "1" is applied to the enable signal E for activating the output buffer 4130 of the signal input / output buffer group 413 under the same condition to be in the active state, and the buffer group 413 is regarded as the output buffer group.

At this time, the multiplexers 406 and 4
At 07, the input terminal ID0 connected to the output of the functional circuit 401 at (0, 0) corresponds to the values of the selection signals (ISEL1, ISEL0), and at the functional circuit 4 at (0, 1).
The input terminal ID1 connected to the output of 02 is (1, 0)
Input terminal ID connected to the output of functional circuit 403 when
2 is selected respectively. And each multiplexer 40
The selected input signal group is output to the outputs OD 6 and 407, and the output of the multiplexer 406 is the input / output buffer group 41.
3 is output to the outside, and the multiplexer 407
Is output to the outside via the multiplexer 408 and further to the output buffer 412. At this time, "0" is applied to the selection input S of the multiplexer 408, and the input terminal ID0 side, that is, the output of the multiplexer 407 is always selected.

As described above, the selection signals (ISEL1, ISEL
SEL0) is (0,0), (0,1), or (1,0)
Under the condition of, when viewed from the outside, IO is used as an input signal pin.
S0 to IOSm, IS0 to ISn and ISEL2 / IS
Total of m + n + 3, OIS0-O as output signal pins
It can be handled as an LSI including ISk and a total of k + j + 2 of OS0 to OSj.

Next, referring to FIG. 4, the selection signal (ISEL
The operation when (1, ISEL0) is (1, 1) will be described. At this time, the selection signal (ISEL2 / IS) is "0".
In the case of "1" and the case of "1", the function of the signal input / output buffer group is set as follows.

When (ISEL2 / IS) = "0". At this time, the output of the AND gate 414 is “0”,
The selection signals (ISEL1, ISEL0) are almost the same as the combinations other than (1, 1), and the pins IOS0 to IO
Sm and IS0-ISn are input pins, pins OIS0-O
ISk and OS0 to OSj are output pins. Signal (I
Since SEL2 / IS) functions as a selection signal, it cannot be used as an input signal in this case. The input terminal ID3 is selected in the multiplexers 406 and 407, the functional circuit 404 is selected, and the functional signal is output to the buffers 413 and 412 defined as the output buffers. Therefore, at this time, the present LSI device has the functional circuit 4
It can be considered equivalent to implementing only 04.

When (ISEL2 / IS) = "1". At this time, the output of the AND gate 414 becomes "1", the output buffer 4130 becomes inactive (high impedance), and conversely, the output buffer 4110 of the signal input / output buffer 411 becomes active. Therefore, as input signals from the outside, pins IS0 to ISn and OIS0 to OIS
A total of n + k + 2 ISk are assigned, and pins OS0 to OSj and IOS0 to IO are output pins to the outside.
That is, a total of j + m + 2 Sm are assigned. As the function output signal, the multiplexer 408 selects the input terminal ID1, that is, the output OB of the function circuit 405 and outputs it to the pins OS0 to OSj.
The output OA of 05 is pin IO directly via the buffer 411.
It is output to S0 to IOSm. Therefore, at this time, this L
The SI device can be considered equivalent to implementing only the functional circuit 405.

In this way, if the bidirectional input / output buffer group is divided into several groups, the input / output function is set using the selection signal, and it is used in combination with the dedicated input / output buffer group. , It is possible to determine the number of input / output pins that are physically required and their physical layout with a very high degree of freedom. Although the case where the bidirectional input / output buffer group is switched to either input or output is used here, depending on the functional circuit, for example, a bidirectional input / output signal group such as a data bus is handled. In some cases. In such a case, the output enable signal E of the bidirectional input / output buffer group
The bidirectional function can be used as it is by dynamically controlling the active / inactive by a functional circuit at a necessary timing.

FIG. 5 is a block diagram showing a more specific embodiment of the multi-function LSI of the present invention, in which 2 bits of 8-bit width data input at a slow timing are input.
A multiplexer circuit 501 for converting to bit width data and outputting at high speed timing, and a slow timing by expanding 2-bit width data input at high speed timing to 8 bit width data. Two functional circuits including a demultiplexer circuit 502 having a function of outputting with a signal output buffer group, and signal input / output buffer groups 504 and 505 for switching input / output pins, a signal output buffer group 508, a signal buffer group 506, and a selection input buffer. The multi-function LSI device is composed of 507 and can realize both functions by one LSI by switching the multi / demulti function according to a selection signal (ISEL). This operation will be described below.

FIG. 6 is a time chart showing the operation of the demultiplexer circuit 502. The selection signal (ISE) shown in FIG.
This is an operation when L) is set to "1". At this time, since the selection signal (ISEL) = “1”, all the output buffers in the signal input / output buffer 504 are inactive, and all the output buffers in the signal input / output buffer group 505 are active.

In this state, when the signal IRES for resetting the internal hardware of the LSI and determining the conversion start timing becomes active level "1", the timing signal of the rising edge of the signal ICLK (high speed clock) at that time An input data string starts to be input from pins IOS0 and IOS1 and is fetched for a total of 4 clocks (4 cycles of signal ICLK). The data of 2 × 4 = 8 bits in total for 4 cycles of this signal ICLK is demultiplexer 502.
Is converted into 8-bit parallel data having a cycle four times that of the signal ICLK. The signal ISYNC outputs the data converted by the demultiplexer 502 to the output pins OIS0 to OI.
The timing to output to S7 is determined, and after the last 2 bits of input data are taken in, the signal ICL
The output timing can be shifted by moving the phase of the signal ISYNC in synchronization with the signal ICLK up to four timings of the subsequent rising edge of K.

In FIG. 6, the data a, b, c and d are fetched from the pin IOS1 from time t ₀ when the signal IRES becomes active and the signal ICLK rises. Then, the phase of the ISYNC signal is determined so that the converted data is output from the rising time t = t ₅ of the signal ICLK immediately after the end of taking in the last data d. Therefore, at time t ₅ in the figure, the data (a, b, c,
d) is the output timing in 8-bit parallel, and time t ₁ shows the output timing of the data (not shown) captured immediately before the data (a, b, c, d). The correspondence between the data (a, b, c, d) and the data value output to the output pins OIS0, OIS1, ...

## EQU1 ## a = ((IOS0 ₀ ), (IOS1 ₀ )) b = ((IOS0 ₁ ), (IOS1 ₁ )) c = ((IOS0 ₂ ), (IOS1 ₂ )) d = ((IOS0 ₃ )) , (IOS1 ₃ ))

(OIS0) = (IOS0 ₀ ) (OIS1) = (IOS1 ₀ ) (OIS2) = (IOS0 ₁ ) (OIS3) = (IOS1 ₁ ) (OIS4) = (IOS0 ₂ ) (OIS5) = (IOS1) ₂ ) (OIS6) = (IOS0 ₃ ) (OIS7) = (IOS1 ₃ ). However, (IOS0 _j ) and (IOS1 _j ) are at time t _j.
Is a bit value fetched from each of the pins IOS0 and IOS1 at the timing of (j = 0 to 3). Thus
Data input in 2-bit parallel is grouped into 8-bit units (extended conversion) and output as 8-bit parallel data.

FIG. 7 shows the multiplexer circuit 501 of FIG.
5 is a time chart showing the operation of the selection signal (IS
This is an operation when EL) is set to "0". At this time, since the selection signal (ISEL) = “0”, all the output buffers in the signal input / output buffer 504 are active and all the output buffers in the signal input / output buffer group 505 are inactive. Become a signal ISYNC is "1", which is the clock of the slow timing timing t ₁₁ of the leading edge of the signal ICLK immediately after the
From outside the 8-bit through the OIS0~OIS7 parallel de in - the data x is inputted from the timing t ₁₂ of the rising of the next signal ICLK 4 cycles (with a period of the signal ICLK) and four by successive 2-bit output data (a, b,
c, d), and continuously outputs four to pins IOS0 and IOS1. In the case of this operation, it is assumed that the signal IRES realizes only the function of resetting the internal circuit of the LSI, but like the case of the demultiplexer, the signal IRES is
It may have a function of determining the timing to start outputting the data converted into IOS0 and IOS1 according to the input timing of ES.

The input / output relationship of the multiplexer operation is as follows. First, the input signals from the input pins OIS0 to OIS7 and the signals a to d are

[Formula 3] a = ((OIS0), (OIS1)) b = ((OIS2), (OIS3)) c = ((OIS4), (OIS5)) d = ((OIS6), (OIS7)) And the output pins IOS0 and IOS1 have time t
_A is output at ₁₂ , t is output at time t ₁₃ , c is output at time t ₁₄ , and d is output at time t ₁₅ .

In the embodiment of FIG. 5, a multiplexer circuit is not used, and a bidirectional signal input / output buffer group 504,
The function of the LSI is determined by switching the input / output function of 505 with a selection input signal (ISEL). This is because the multiplexer and the demultiplexer have exactly opposite functions, and the total number of function signals can be made substantially the same by only reversing the number of input pins and the number of output pins. This is because it is suitable to be integrated together. As described above, if the functional circuits to be integrated together are carefully studied, it can be seen that a multifunction LSI can be constructed very efficiently and effectively. That is, the multiplexer circuits 5 and 4 in FIGS.
The embodiment shown in FIG. 5 is an example showing that a multifunction LSI device can be configured very efficiently without using a special circuit for function switching corresponding to 06, 407, and 408. Can be said.

As an application of the embodiment of FIG. 5, for example, the function of the common circuit (CLKGT) 503 in FIG. 5 is multiplexed / demultiplexed to form a clock generation and control LSI, and more functional circuits are provided. Can be implemented, an arithmetic processing LSI can be realized by implementing an arithmetic function circuit and the like together with a multiplexer circuit and using a multi / demulti circuit for input / output.

A system configuration example using such a multifunction LSI of the present invention will be described with reference to the embodiment of FIG. In this system, first, an analog signal input from an input terminal 801 is amplified by an amplifier, and then a sampling type ADC (analog-digital converter) 802 is used to
It is converted into digital data of 4 bits × 8 = 8 bits, and a total of 4 sets of 2 bits each of the data are input to four demultiplexers (LSI-A) 803 to 806. The demultiplexers 803 to 806 perform almost the same operations as the demultiplexers described with reference to FIGS. 5 and 6, and convert their 2-bit inputs into 8-bit parallel data. Each output of the demultiplexers 803 to 806 is divided into four sets of 2 bits, and each output of each demultiplexer has four sets of arithmetic circuits (LSI-).
B) Input to 807-810. Each arithmetic circuit 807-
The output of 810 is also composed of 2 bits × 4 sets, and this output also has four multiplexers (LSI-C) 811.
~ 814. This multiplexer is also almost the same as that described with reference to FIGS. Finally, the 2-bit width serial data output from each of the multiplexers 811 to 814 is input to a sampling type DAC (digital-analog converter) 815, converted into analog data, amplified by an amplifier, and output as analog. Terminal 8
16 is output.

Clock generation and control circuit (LSI-D)
817 is a high-speed system clock used as a reference for ICK
At the input, the system reset signal for resetting the internal circuit and generating the external reset output signal ORES I
Demultiplexers 803-806 received by RES input
Reset signal ORES to each, clock signal OCKADC to ADC 802, and demultiplexer 80
3 to 806 clock signals OCKA0 to 3 respectively,
Clock signal OC to each of the arithmetic circuits 807 to 810
KB0 to OCKB3 and multiplexers 811 to 814
Clock signals OCKC0 to OCKC3 to each,
The clock signal OCKDAC to the DAC 815 is generated.

The demultiplexers 803 to 806 and the multiplexers 811 to 814 are substantially the same as the multifunction LSI shown in FIG. 5 as described above, except that the demultiplexers 803 to 806 are input at high speed. Reference clock signals OCKA0 to OCKA3
(Equivalent to ICLK in FIG. 5) based on (4) the low-speed synchronization clock OSY and OSY
0-3 are generated and the clock OSY is calculated by the arithmetic circuits 807-8.
Input to 10 input terminals ISY, and clock OSY0-O
This means that SY3 is input to the corresponding input terminals ISY of the multiplexers 811 to 814. Also, the multiplexer does not require a reset input, and the synchronous clock ISY input from the demultiplexer and the reference clocks OCKC0 to OC having a frequency four times that of the synchronous clock ISY are input.
KC3 has a simple structure only obtained from the clock generation and control circuit 817. However, there is essentially no difference from the multiplexer / demultiplexer function of the multi-function LSI shown in FIG. That is, the multiplexers 803 to 806 and the demultiplexers 811 to 8
5, the selection signal (ISEL) is set to "1" (pull-up PU) to make the demultiplexers 803 to 806, and the selection signal (ISE
L) may be set to “0” (pull-down PD) to form multiplexers 811 to 814. The data conversion function is almost the same as that shown in FIGS. In this way, in the entire system shown in FIG. 8, the time required for the arithmetic processing is secured by converting the analog data input at high speed into the slow digital data by the demultiplexer in the preceding stage, and the data is secured. On the other hand, the central arithmetic circuit adds the necessary arithmetic processing (filtering, complicated data conversion, etc.), and the output result is converted to high-speed analog data again by the multiplexer in the latter stage and output. are doing.

In the embodiment shown in FIG. 8, demultiplexers 803 to 806 and multiplexers 811 to 81 are provided.
Although only 4 has been described as a target of the multi-function LSI, as described above, if more functional circuits can be integrated, a clock generation and control circuit 817 is added by adding a multiplexer circuit that switches a selection signal and a function. And the functions of the arithmetic circuits 807 to 810 are both 1
It is also possible to manufacture a multi-function LSI integrated on a chip. In this case, the arithmetic circuits 807 to 81
Since the number of input / output pins of 0 is larger than the number of input / output pins of the demultiplexers 803 to 806 and the multiplexers 811 to 814, if the total number of pins is adjusted to the demultiplexer or the multiplexer, the input / output data to the arithmetic circuit is
It is necessary to reduce the number of tabbits. To do this, for example,
At present, the input / output data composed of 2 bits × 4 8 bits is bit sliced into 1 bit × 4 4 bits data (the number of LSIs increases accordingly). Conversely, if the number of pins of the arithmetic circuit is matched, the demultiplexer and the data width after demultiplexing in the multiplexer and before the multiplex are increased (for example, 16 bits), and the number of arithmetic circuits is increased (for example, 8LSI). Is very effective. The clock generation and control circuit 81
7 is a character that generates a plurality of signals of the same function,
It can be said that the physical control of the number of pins at the time of design is easy, and since many outputs are provided, it can be easily integrated as a multifunction LSI with other functional circuits such as a demultiplexer and an arithmetic circuit. Further, as described above, physical control of the number of input pins and the number of output pins at the time of design can be easily performed by providing a bidirectional input / output buffer group so that the input / output states can be finely set. is there.

FIG. 9 shows a modified example of the system shown in FIG.
C903 and 904, 500 MHz to 1 GHz (500 MHz at the sampling cycle level of DAC940)
This is based on the premise that ultra high-speed analog input / output signals (expressed as + α) are handled. However, ADC903
904 and 904 are cycles for reliably sampling the ultra-high speed analog input data (which requires sampling at 500 MHz + α) input from the analog input terminal 902 by the ADCs 903 and 904 while ensuring a sufficient sample hold time. It uses a steel. That is, ADC
250MHz + β for each ADC by alternately allocating analog input data to 903 and ADC 904
It is configured so that it can be sampled at. In order to perform this cycle steal, ADC903 and ADC90
4 is a clock generation LSI (CL
KGT-A) 905. In addition, by dividing the block into two blocks and sampling each at 250 MHz + β, the sampling rate of the ADC can be reduced, so that the switching noise inside the ADC and the output buffer reduce the external load. Since switching noise at the time of driving can be reduced and stable analog-to-digital conversion can be performed, the definite time for the output digital data can be secured for a long time, so that the demultiplexer LSIs 906 to 913 in the next stage can be secured. Even in the data latch operation for the above, a margin is provided for the setup time, and thereafter, reliable digital data processing becomes possible.

In this embodiment, the demultiplexer LSI 9
06 to 913 have a 1: 8 conversion function (1: 4 in the example of FIGS. 5 and 8). That is, 2 bits x 1 data is input and converted into 2 bits x 8 data. The synchronous clock (SYNC) and the reference clock required for the demultiplexer LSIs 906 to 913 are supplied from the clock generation LSI 905. The demultiplexer LSIs 906 to 913 also generate a reference clock to the arithmetic processing LSIs 914 to 929 in the next stage. The reference lock frequency for the arithmetic LSIs 914 to 929 is the demultiplexer LSIs 903 to 913.
Therefore, the sampling frequency of 250MHz + β is 8
32MHz + because it is equivalent to being converted to one
γ.

Subsequent multiplexer LSIs 930 to 93
3 and 935 to 938 are also 8: 1, and the conversion process exactly opposite to that of the demultiplexer LSI is performed to
Operation processing LSI 9 with a sampling frequency of 2 MHz + γ
250 MH for data sent from 14 to 929
Convert to data that changes with z + β. Then, by using the 2: 1 multiplexer LSI 939 at the final stage, a total of 16 bits of 8 bits each from two blocks separated by the cycle steal are converted to 500 MHz.
Convert to 8-bit data that changes with + α and convert to DAC94
Output to 0. The DAC 940 converts the 8-bit digital input data into analog data and outputs it at the output terminal 94.
Output to 1. In addition, the reference clock and synchronization clock (SYNC) to each demultiplexer and multiplexer
Is supplied by the clock generation LSI (CLKGT-B) 9
34. Also, in this example, CLKGT-B9
Reference clock to 34 and synchronization clock (SYNC)
Is supplied by the clock generation LSI (CLKGT-A) 90
It is done by 5.

In the present embodiment having the above-mentioned configuration, since extremely high speed analog data is handled, except for the arithmetic processing blocks by the arithmetic processing LSIs 914 to 929 which can operate at relatively slow timing (32 MHz + γ), Other blocks are LSIs that are at least one rank high-speed or that use a manufacturing process that enables high-speed switching.
There is a high possibility that it will be necessary to configure with (for example, LSI using GaAs or ECL process). Therefore, these demultiplexers, multiplexers, and LSs for block generation
The I can be incorporated as a multi-function LSI, but it may not be possible to design the arithmetic processing LSIs having different operation speeds to be incorporated together as a multi-function LSI. In the case of this example, 16 arithmetic processing LSIs are used. The bit length of the input and output is the same as the example of FIG. 8, but as described above,
The calculation cycle is the sampling frequency of the original oscillator (500 MH
It is possible to reduce the speed to 1/16 of z + α). However, since the number of input / output pins of all the LSIs is almost the same, the arithmetic processing LSIs 914 to 9 may be used depending on the arithmetic processing contents.
29 is also more efficient when it can be incorporated as a multi-function LSI on the same chip as other LSIs.

[0045]

According to the present invention, an effect equivalent to the number of input / output pins multiplied by the number of functional circuits can be obtained, and the pin neck can be eliminated. The development cost can be obtained by manufacturing one chip of an LSI in which necessary functions are integrated, and the amount of circuit design is almost the same, but the initial manufacturing cost can be kept very low. Further, in mass production, an LSI having the same number of functional circuits as the number of functional circuits is produced, so that very high mass productivity can be secured. Therefore, even a system that produces only a small amount can be sufficiently integrated into an LSI. Also, the package may be of a standard level with a small number of pins, and the package cost can be kept very low.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a multifunction LSI device according to the present invention.

FIG. 2 is a block diagram showing a general configuration in a local circuit block.

FIG. 3 is an explanatory diagram of a relationship between a circuit mountable scale of an LSI (CMOS gate array) and the number of input / output pads.

FIG. 4 is a block diagram showing another embodiment of a multifunction LSI device according to the present invention.

FIG. 5 is a block diagram showing an embodiment of a multiplexer / demultiplexer LSI device according to the present invention.

FIG. 6 is a time chart of the demultiplexer operation in the embodiment of FIG.

FIG. 7 is a time chart of the multiplexer operation in the embodiment of FIG.

FIG. 8 is a block diagram showing a configuration example of a system using the multi-function LSI device according to the present invention.

9 is a block diagram showing a modified example of the system of FIG.

[Explanation of symbols]

 1 to 4 functional circuit 5 multiplexer 6 selection input buffer group 401 to 405 functional circuit 406 to 408 multiplexer 409 selection input buffer group 411, 413 signal input / output buffer group 501 multiplexer 502 demultiplexer 504, 505 signal input / output buffer group 507 selection input Buffer 803 to 806 Demultiplexer LSI 807 to 810 Operation circuit LSI 811 to 814 Multiplexer LSI

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/82

Claims (9)

[Claims] 1. A plurality of pins for external connection, a plurality of functional circuits, a selection signal input circuit for inputting a selection signal for selecting the functional circuits, and an input terminal of the functional circuit selected by the selection signal. And a switching circuit for connecting one or both of the output terminals and a part of the pins, a multi-function LSI device. 2. The switching circuit is a circuit for connecting an output end of a functional circuit selected by the selection signal to a part of the pin, and the other parts of the pin are all common input pins. 2. The multi-function LS according to claim 1, wherein the multi-function LS is connected to the input terminal of the functional circuit of FIG.
I device. 3. The multi-function LSI device according to claim 1, wherein the switching circuit is a bidirectional buffer group which is connected to a part of the pins and whose signal transmission direction can be switched bidirectionally. . 4. The multi-function LSI device according to claim 3, wherein the functional circuit is a demultiplexer circuit for converting a high-speed serial signal into a low-speed parallel signal and a multiplexer circuit for performing an inverse conversion thereof. 5. An arithmetic processing system configured by using the multifunction LSI according to claim 1. Description: 6. A multifunction L according to claim 4, for converting a high speed serial signal into a low speed parallel signal.
5. An SI device, an arithmetic processing LSI device for performing arithmetic processing using the low speed parallel signal as an input, and a low speed parallel signal output from the arithmetic processing LSI device for converting to a high speed serial signal. And a multi-function LSI device as described above. 7. A function switching method for a multi-function LSI device, comprising a plurality of functional circuits, wherein one of the functional circuits is selected and used, and one or both of an input terminal and an output terminal of the selected functional circuit is the LSI. Multi-function LS characterized in that the function is switched by switching so as to be connected to part of the external connection pins of the device.
Method of switching function of I device. 8. The input terminal of each of the functional circuits uses a part of the pin as a common input pin, and only the output terminal of the selected functional circuit is connected to another part of the pin via a multiplexer. 8. The function switching method for a multi-function LSI device according to claim 7, wherein the function switching is performed by the above. 9. A part or all of an input end and an output end of the selected functional circuit is connected to a part of the pin through a bidirectional buffer group whose signal transmission directions can be switched bidirectionally. 8. The function switching method for a multi-function LSI device according to claim 7, wherein the function switching is performed by the above.