JPH08201544A - Radio paging receiver and clock with radio paging receiver - Google Patents

Abstract

PURPOSE: To obtain a clock in which data is taken in a period in which the data is stable by a method wherein the changeover point of the signal of received radio waves is detected from the synchronous signal part of a decoded FSK signal and a strobe pulse used to take in the data is generated immediately before the changeover point. CONSTITUTION: Counters 53, 54 count the output of a reference oscillator 52 while decoded data as the output of a four-edge-detection-type phase detection circuit 51 is in the section of a logic value of 0. Its oscillation frequency is, e.g. 76.8kHz. Counters 55, 56 count 1/2 of counted values by the counters 53, 54 as initial values in a moment in which the decoded data is changed from 0 to 1, gates 57, 58 detect a moment in which the counted values become preset values, they generate a strobe signal, and the data is taken in a signal processing circuit by a strobe pulse. Thereby, a point in which the data is changed over can be estimated precisely, and the influence of a jitter or the like can be reduced when the received data is taken in.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio paging receiver, and proposes a method for generating a timing for fetching data demodulated by a direct conversion type receiving circuit. The present invention is particularly effective for a system that transmits data by 4FK modulation.

[0002]

2. Description of the Related Art Conventionally, RCR using 2FSK modulation
STD-41 NTT radio calling system, STD
The -42 POCSAG radio calling system is adopted. In these receivers, a clock for fetching data uses a bit synchronization method or a preamble synchronization method, but detects a data edge, compares it with an internal clock, and extracts it by statistical processing. .
The data rate of the conventional 2FSK radio calling method is 51
Since the shift frequency is 2 or 1200 bps and the deviation frequency is 4.0 kHz or 4.5 kHz, the phase of the baseband signal per bit of data is 7.5π (1200 bps) to 1 in the receiving circuit of the direct conversion system.
Since it was rotated by 7.5π (512 bps), the jitter at the leading edge of data corresponds to an angle of 0.5π at maximum when the 4-edge detection type phase detection circuit is used, which is 1/15 to 1 of the 1-bit section. It was / 35, which was sufficiently smaller than the stabilization time of the data. Therefore, it suffices to fetch the decoded signal by detecting the edge position of the pulse and delaying it a certain amount.

[0003]

[Problems to be Solved by the Invention] However, RCR
In STD-43, since the data transmission rate is increased and the modulation rate is also reduced, the bit error increases and the sensitivity deterioration is prevented in the conventional technique.

[0004]

[Table 1]

Table 1 is a combination table of transmission rates and modulation methods in RCR STD-43 "advanced radio calling system". The symbols "11" and "" found in police box 4 in Table 1
In "01", the excursion frequency is as low as 1.6 kHz and the duration is 1/3200 seconds, so the phase of the baseband rotates only ± π. The direct conversion method is used for such a communication system. The leading edge jitter of the decoded signal is 1/2 of the symbol period,
The stable period is as short as 1/2. Furthermore, since the jitter increases due to the frequency deviation between the local oscillation circuit of the receiver and the received radio wave, the stable time of the decoded signal is narrowed. In order to receive the data correctly, it is important to capture the data during the stable period of this data.

Regarding the method of the receiving circuit, the direct conversion method is preferable from the viewpoint of miniaturization of the receiver. The reason is that the channel filter has an advantage that the filter can be integrated into an IC as compared with the other method that requires a solid resonance.

However, since the detection in the direct conversion system is a phase detection system, the decoded data contains a lot of jitter under the influence of the phase difference between the received radio wave and the local oscillation circuit of the reception circuit.

FIG. 5 shows the configuration of a direct conversion type FSK receiving circuit. The signal received by the antenna 1 is amplified by the RF amplifier 2 and then amplified by the first mixer-3,
It is input to the second mixer-4 and is multiplied by the local oscillator signal. 5
Is a local oscillator signal generation circuit, and 6 is a phase circuit, which delays the phase of the local oscillator signal by π / 2. As a result, π is output to the mixers 3 and 4.
An intermediate frequency with a phase difference of / 2 is output. As a result of the local oscillation signal being the same as the frequency of the received radio wave, the center value of the intermediate frequency wave is zero Hz and the displacement frequency of FSK is output. The channel filters 7 and 8 are for removing DC components and out-of-band components from the intermediate frequency output, for example, 5
It has a pass band of 00 Hz to 7 KHz. Numerals 9 and 10 are limiters for saturation amplification of the intermediate frequency and conversion into pulses. 11
Is a data flip-flop having an edge detection type phase detection function. When the intermediate frequencies output from the channel filters 9 and 10 are referred to as Q and I signals respectively, fc is the carrier frequency of the received radio wave, and the same FSK modulation frequency deviation is δ,
When the frequency deviation between the local oscillation frequency of the receiver and fc is ε and the phase difference is ψ, fc + δ, fc− of the transmission frequency signal
Depending on δ, the I and Q signals are as follows:

[0009]

## EQU1 ## I signal = COS (2π (δ ± ε) t ± ψ)

[0010]

## EQU2 ## Q signal = ± SIN (2π (δ ± ε) t ± ψ)

FIG. 6 is a vector diagram showing the Q signal on the X axis and the I signal on the Y axis. The vector OP20 rotates left when the frequency deviation of FSK modulation has a positive sign and rotates right when the frequency deviation has a negative sign. . Angular velocity is

[0012]

[Equation 3] ω ₊ = 2π (δ−ε)

[0013]

[Formula 4] ω ₋ = 2π (δ−ε)

[0014] The edge detection type phase detection circuit detects the rotation direction of the vector OP of FIG. 6 when it passes a certain phase, and determines the pulse value. In the data flip-flop shown in FIG. 5, the pulse falls when the vector OP passes clockwise through the phase of 2 / π + I axis,
-Π / 2 phase-The pulse rises when passing the I axis counterclockwise.

FIG. 7 is a circuit showing a configuration example of a 4-edge detection type phase detection circuit.
The pulse value can be determined by detecting the rotation direction regardless of the direction of passing the + I axis of 2, the -Q axis of -π, and the -I axis of -π / 2. 31 and 32 are saturated I and Q
Signal input terminals 33, 34 are inverters, 35, 3
6, 37, 38 are data flip-flops, 39, 4
Reference numeral 0 is a gate, 41 is a flip-flop, and 42 is an output terminal. This circuit can replace the data flip-flop of FIG.

2 / by new RCR STD-43
4FSK method was established. The conventional 2FSK radio calling method has a data rate of 512 or 1200 bps,
Since the excursion frequency is 4.0 kHz or 4.5 kHz, in the direct conversion type receiving circuit,
The phase of the baseband signal per data bit is 7.5.
π (1200 bps) to 17.5 π (512 bps)
Since it was rotated, the jitter at the leading edge of the data corresponds to the maximum angle of 0.5π when the 4-edge detection type phase detection circuit is used, which is 1/15 to 1/35 of the 1-bit section. It was sufficiently smaller than the stabilization time. Therefore, it suffices to fetch the decoded signal by detecting the edge position of the pulse and delaying it a certain amount.

Table 1 is a combination table of transmission rates and modulation methods in RCR STD-43 "advanced radio calling system". The symbols "11" and "" found in police box 4 in Table 1
In "01", the excursion frequency is as low as 1.6 kHz and the duration is 1/3200 seconds, so that the phase of the baseband is rotated by only ± π. The leading edge jitter of the signal is 1/2 of the symbol period, and the stable period is as short as 1/2. Furthermore, the jitter increases due to the frequency deviation between the local oscillation circuit of the receiver and the received radio wave, so that the decoded signal is stable. In order to receive the data correctly, it is important to capture the data during the stable period of this data.

[0018]

According to the present invention, a switching point of a signal of a received radio wave is detected from a sync signal portion of an FSK signal decoded by a direct conversion type receiving circuit,
We propose a circuit that generates a strobe pulse for data capture immediately before the switching point. The circuit of the present invention may be used for a signal decoded by a superheterodyne receiver circuit.

[0019]

FIG. 2 is a diagram showing the principle of strobe signal generation according to the present invention, in which transmission data "0" and "1" are 1600 bps.
This is a sync signal portion that is repeated in 2FSK. The composite output A is the FSK decoding output by the edge detection type phase detection circuit, and the count value 1A and the count value 2A are the counters 53, 54, 55 and 56 of the strobe signal generation circuit of FIG. 1 which is an embodiment of the present invention. It is a numerical value.

Here, paying attention to the time width X in which the FSK decoded output is "0", the following equation holds for X. τ ₁ is the fall delay time from the composite output transmission data, and τ ₂ is the rise delay time. T is the duration per bit or symbol of transmitted data;

[0021]

[Formula 5] X = T + τ ₂ −τ ₁

[0022]

Τ ₁ + τ ₂ = (ψ / ω ₊ ) + (π / 2−ψ) ω ₋

Here, considering the frequency deviation,

[0024]

(7) ε = 0

[0025]

[Equation 8] _{ω + = ω - = ω0 =} 2π × 4800 = 9600
π (radian / second)

Then,

[0027]

Τ ₁ + τ ₂ = (ψ / ω ₀ ) + (π / 2−ψ) / ω ₀

[0028]

[Equation 10] τ ₁ + τ ₂ = (π / 2) / ω ₀

[0029]

[Formula 11] τ ₁ + τ ₂ = 1/19200 seconds

And becomes a constant value. T is data 1 /
Because it ’s the transmission speed

[0031]

[Equation 12] T = 1/1600 seconds

Therefore

[0033]

X = T + τ ₂ −τ ₁

[0034]

X = T + τ ₂ − (τ ₁ + τ ₂ ) −τ ₂

[0035]

X = (T + τ ₁ + τ ₂ ) + 2τ ₂

[0036]

X = (1/1600 + 1/19200) + 2τ ₂

[0037]

X / 2 = (T + τ ₁ + τ ₂ ) / 2 + τ ₂

[0038]

X / 2 = (1/1600 + 1/19200) / 2 + τ ₂

[0039]

X / 2 = τ ₂ +13/38400

It becomes In order to find the exact switching point of the received radio wave, first measure the section X of the logical value "0" of the decoding signal, and initialize X / 2 at the moment when the logical value switches from "0" to "1". The measurement of the section of the logical value "1" is started as a value, and the measured value always has a fixed relationship with the switching point of the received radio wave.

[0041]

1 is a circuit diagram of a strobe signal generating circuit according to an embodiment of the present invention. Reference numeral 51 is a 4-edge detection type phase detection circuit shown in FIG. 7, 52 is a reference oscillation circuit, 53 and 54 are first counters, and the decoded data output from the 4-edge detection type phase detection circuit 51 is a logical value "0". During the period "", the count of the output of the reference oscillation circuit 52 is measured. The frequency of the oscillator circuit is 76.8 kHz in this example. 55 and 56 are second counters, and at the instant when the decoded data changes from "0" to "1", 1/2 of the count value of the first counters 53 and 54
Is counted as an initial value, and the gates 57 and 58 detect a week when the counted value is predetermined and generate a strobe signal.

In FIG. 2, the count value 1A is 1 / X of the X section.
The count value of the counters 53 and 54, which is measured in units of 76 and 800 seconds, and the count value 2A, the decoded output is the logical value "0" to "1"
At the moment of switching to, the count value of the counter 53, 54 is 1
This is the count value of the counters 55 and 56 which are loaded with / 2 as an initial value and continue counting thereafter. The address is a hexadecimal number indicating the time from the change point of the transmission data as 1/76 and 800 seconds. Decoded outputs B, C, and D are examples of reception / decoding of transmission data with various phase differences. Counters 55 and 56 even if the phases of the decoded data are different
The count values 2A, 2B, 2C, and 2D, which are the contents of, all have the same phase difference with respect to the address.

The data in item Nos. 2 and 4 of Table 1 are 1 /
It changes every 3,200 seconds, which is twice the speed of the sync signal. Therefore, when the synchronizing signal is used as a reference, the signals are switched between 17H and 18H (hexadecimal) in FIG.
To capture stable data, a strobe signal may be generated when the count values of the counters 556 and 56 in FIG. 1 are 2BH.

[0044]

[Table 2]

FIG. 3 and Table 2 are cited from RCR STD-43 Chapter 3, FIG. 3.1-3, and show the structure of the synchronization signal corresponding to item No. 4 of Table 1. The strobe signal of the present invention corresponds to "BS1" and "B", "BS2", "/ BS" in the diagram.
It is calculated in the 2 "portion, and thereafter, it is repeated in 1/1600 seconds or" 1/3200 "seconds according to the data rate based on the internal clock. For item numbers 1, 2, and 3, R
CR STD-43, Chapter 3, Figures 3.1-1 to 3.1, Table 3.
Although described in Nos. 2-1 to 2-3, a strobe signal can be similarly generated for these.

The data has a missing waveform due to the influence of noise or the like. Therefore, the reliability of the data can be further enhanced by comparing the internal counter having a cycle of 1/1600 second and the outputs 59 and 60 of FIG. 1 and averaging the numerical values to determine the timing at which the strobe signal is generated.

FIG. 4 shows an embodiment of an averaging-processed strobe signal generating circuit according to the present invention, in which 101 is the strobe signal input terminal shown in FIG. 1 and 102 is a clock input terminal.
103 is an internal counter, 104 is the same data output, 105
Is an interrupt input terminal of the CPU, 106 is a parallel input terminal, 107 is a parallel output terminal, 108 is a comparator, 1
09 is an averaged strobe output terminal, 110 is a CPU
Is. The CPU 110 performs a calculation for averaging the values of the counter 103 when the strobe signal is input, and outputs the result to the comparator 108. The comparator 108 compares the data with the numerical value of the internal counter to generate a new strobe signal that has been averaged, and outputs the strobe signal to the terminal 109.

[0048]

That is, by using the strobe signal generation method of the present invention, it is possible to accurately predict the switching point of the received radio wave data, and as a result, the influence of jitter in the reception of the received data is reduced. Errors can be reduced.

In the embodiment, the switching point of the received radio wave is predicted from the part of the logical value "0" of the FSK decoded signal, but it can be similarly predicted from the part of "1". It is also clear that the data predicted from the "1" part and the "0" part can be averaged to generate a strobe signal.

According to RCR STD-43, the time data is transmitted at frame zero every cycle of data transmission, and the synchronization with the real time is defined as the rising edge of the first bit of bit synchronization 1. By using the present invention, it is possible to correct the delay of the decoded data caused by the phase difference between the local oscillation signal and the received radio wave in the direct conversion receiving circuit, and as a result, the synchronization with the real time can be performed accurately. You can That is, by using the present invention, it is possible to improve the synchronization accuracy of the clock incorporated in the radio paging receiver. Of course, the present invention can be applied to a radio wave controlled timepiece.

[Brief description of drawings]

FIG. 1 is a circuit diagram of strobe signal generation according to an embodiment of the present invention.

FIG. 2 is a timing diagram showing the principle of strobe signal generation according to the present invention.

FIG. 3 is a configuration diagram of a synchronization signal of an RCD STD-43 which is a target of the present invention.

FIG. 4 is a block diagram of an averaged strobe generation circuit according to an embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional direct conversion receiving circuit.

FIG. 6 is a vector diagram showing the principle of conventional edge detection type phase detection.

FIG. 7 is a circuit diagram of a conventional 4-edge detection type phase detection circuit.

[Explanation of symbols]

 1 antenna 2 amplification circuit 3, 4 mixer 5 local oscillator circuit 6 phase circuit 7, 8 channel filter 9, 10 saturation amplifier 11 phase detection circuit 31 I signal input terminal 32 Q signal input terminal 33, 34 inverter 35, 36, 37, 38, 41 Flip-flop 39, 40 Gate 42 Output terminal 51 4 Edge detection type phase detection circuit 52 Reference oscillation circuit 53, 54 First counter 55, 56 Second counter 57, 58, 61 Gate 59, 60 Strobe signal output terminal 101 Strobe signal input 102 Clock input terminal 103 Internal counter 104 Data output terminal 105 Interrupt input terminal 106 Parallel data input terminal 107 Parallel output terminal 108 Comparator 109 Averaged strobe output terminal 110 CPU

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical display location H04Q 7/14 H04L 7/00 Z

Claims (8)

[Claims] 1. A receiver for receiving digital data by an FSK modulated wave, comprising first means for measuring a time width of a single "0" or "1" of a decoded pulse train consisting of binary signals, Second means for measuring time from the end of the pulse with 1/2 of the time width as an initial value, and third means for generating a strobe pulse when the measured value of the second means reaches a predetermined value. A radio paging receiver comprising: a signal processing circuit that captures data by the strobe pulse. 2. A receiver for receiving digital data by an FSK modulated wave, comprising first means for measuring the time width of a single "0" or "1" of a decoded pulse train consisting of binary signals, Second means for measuring time from the end of the pulse with 1/2 of the time width as an initial value, and third means for generating a strobe pulse when the measured value of the second means reaches a predetermined value. A fourth means for generating a pulse having a frequency equal to the transmission rate of the received data, the fourth pulse generating means being synchronized with the strobe pulse, and the fifth signal processing being performed by the pulse generated by the fourth means. The means is a radio paging receiver characterized by taking in data. 3. Within the scope of claim 2, the fourth pulse generating means is synchronized in the synchronizing signal portion of the digital data, and the fourth means is self-propelled until the next synchronizing signal portion. A radio call receiver characterized by. 4. Within the scope of claim 3, when the data transmission rate of the sync signal part and the data part following it is the integer multiple of the former, the fourth pulse generating means causes the fourth pulse generating means to perform one cycle of the sync signal. A radio paging receiver characterized by generating a plurality of strobe pulses at equal intervals. 5. A radio wave control clock for receiving digital data by an FSK modulated wave, comprising first means for measuring the time width of a single "0" or "1" of a decoded pulse train consisting of binary signals. , Second means for measuring the time from the end of the pulse with 1/2 of the time width as an initial value, and third means for generating a strobe pulse when the measured value of the second means reaches a predetermined value. A timepiece with a radio paging receiver, which is provided with means, and takes in data to a signal processing circuit by the strobe pulse. 6. A first means for measuring the time width of a single "0" or "1" of a decoded pulse train consisting of a binary signal in a radio controlled clock that receives digital data by an FSK modulated wave, Second means for measuring the time from the end of the pulse with 1/2 of the time width as an initial value, and third means for generating a strobe pulse when the measured value of the second means reaches a predetermined value, A fourth means for generating a pulse having a frequency equal to the transmission rate of the received data is provided, the fourth pulse generating means is synchronized by the strobe pulse, and the fifth signal processing means is generated by the pulse generated by the fourth means. Is a clock with a radio paging receiver characterized by capturing data. 7. The method according to claim 6, wherein the fourth pulse generating means is synchronized in the synchronizing signal portion of the digital data,
After that, the fourth means is self-propelled until the next synchronization signal section. 8. The data transmission rate of a synchronizing signal portion and a data portion following the synchronizing signal portion according to claim 7, when the latter is an integral multiple of the former, the fourth pulse generating means is provided with a plurality of pulses per period of the synchronizing signal. A clock with a radio paging receiver, which is characterized in that the strobe pulses of are generated at equal intervals.