JPH08199389A - Electroplating and fine pattern formation - Google Patents

Electroplating and fine pattern formation

Info

Publication number
JPH08199389A
JPH08199389A JP7011968A JP1196895A JPH08199389A JP H08199389 A JPH08199389 A JP H08199389A JP 7011968 A JP7011968 A JP 7011968A JP 1196895 A JP1196895 A JP 1196895A JP H08199389 A JPH08199389 A JP H08199389A
Authority
JP
Japan
Prior art keywords
electrolytic plating
layer
conductive layer
pattern
electrolytic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7011968A
Other languages
Japanese (ja)
Inventor
Wakana Wasa
若菜 和佐
Norihiro Katakura
則浩 片倉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nikon Corp
Original Assignee
Nikon Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nikon Corp filed Critical Nikon Corp
Priority to JP7011968A priority Critical patent/JPH08199389A/en
Publication of JPH08199389A publication Critical patent/JPH08199389A/en
Pending legal-status Critical Current

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Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/30Coatings combining at least one metallic layer and at least one inorganic non-metallic layer
    • C23C28/32Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one pure metallic layer
    • C23C28/322Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one pure metallic layer only coatings of metal elements only
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/30Coatings combining at least one metallic layer and at least one inorganic non-metallic layer
    • C23C28/34Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one inorganic non-metallic material layer, e.g. metal carbide, nitride, boride, silicide layer and their mixtures, enamels, phosphates and sulphates
    • C23C28/345Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one inorganic non-metallic material layer, e.g. metal carbide, nitride, boride, silicide layer and their mixtures, enamels, phosphates and sulphates with at least one oxide layer
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02Electroplating of selected surface areas
    • C25D5/022Electroplating of selected surface areas using masking means
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/22Electroplating combined with mechanical treatment during the deposition

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Metallurgy (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • Mechanical Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Electrochemistry (AREA)
  • Micromachines (AREA)
  • Electroplating And Plating Baths Therefor (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Other Surface Treatments For Metallic Materials (AREA)

Abstract

PURPOSE: To prevent the contamination of an electrolyte or the breaking of a resist pattern by using the main components common both to a base conductive layer and an electroplated film, and using the other components common both to an electropolishing solution and an electroplating solution, at the time of forming a fine pattern by electroplating method. CONSTITUTION: The base conductive layer 2 composed of Ni, a resist layer 4 and an SiO2 film as an intermediate layer 5 are formed on an Si wafer as a substrate 1 and finally an upper resist layer 6 is formed. The upper resist layer 6 is exposed, developed and baked to form the resist pattern 6a, the pattern is transferred to the intermediate layer 5 by using the resist pattern 6a as a mask by dry etching method and, after that, the pattern is transferred to the under resist layer 4 by using the intermediate layer 5a as a mask by dry etching method using gaseous O2 to form an under layer resist pattern 4a. Next, a plasma electrode is connected to the base conductive layer 2 to electropolish and, after an electroplated layer 3 is deposited by using the under layer resist pattern 4a as a mask, the upper resist pattern 6a is stripped and further the intermediate layer pattern 5a and the under layer resist pattern 4a are removed by dry etching method.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電解メッキ方法、およ
び、電解メッキを用いた微細パターン作製方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrolytic plating method and a fine pattern forming method using electrolytic plating.

【0002】[0002]

【従来の技術】現在、微細加工技術としてはイオンミリ
ング法やRIE(リアクティブイオンエッチング)法と
いった真空中にて行なわれるドライプロセスが主流であ
る。しかし、近年になって、マイクロマシンやLSIパ
ターン、X線マスクパターン、ゾーンプレートといった
ような微細加工パターンの作製にも、電解メッキ技術が
応用されてきている。電解メッキ法は一般に大気圧の下
で行なわれるため真空系が不要で、ドライプロセスと比
較すると低コストで微細加工パターンを作製することが
できる。
2. Description of the Related Art At present, as a fine processing technique, a dry process such as an ion milling method or an RIE (reactive ion etching) method performed in a vacuum is mainly used. However, in recent years, the electrolytic plating technique has been applied to the production of microfabrication patterns such as micromachines, LSI patterns, X-ray mask patterns, and zone plates. Since the electroplating method is generally performed under atmospheric pressure, a vacuum system is not required, and a microfabrication pattern can be produced at a lower cost than a dry process.

【0003】最近では製造工程の改良により、このよう
な電解メッキ法を用いて一層微細なパターンや高アスペ
クト比のパターンが形成できるようになっている。たと
えば、微細パターンの形成方法として開示されているも
のに、特願平6ー216133に示す方法がある。
Recently, the manufacturing process has been improved so that a finer pattern and a pattern with a high aspect ratio can be formed by using such an electrolytic plating method. For example, a method disclosed in Japanese Patent Application No. 6-216133 is disclosed as a method for forming a fine pattern.

【0004】図3〜4は上記方法の工程を示す工程図で
ある。まず、基板21上に下地導電層22を形成し(図
3(a))、さらに、下層レジスト層24、中間層2
5、上層レジスト層26の順に、各層を形成する(図3
(b))。次に、露光、現像により所望パターンのレジ
ストパターン26aを形成した後(図3(c))、この
レジストパターン26aをマスクとして、ドライエッチ
法により中間層25をパターニングする(図3
(d))。さらに続けてエッチングを行ない、下層レジ
スト層24をパターニングしたものが、図4(a)に示
す状態である。この後、部分的に露出した下地導電層2
2の露出部分22aに電解メッキ膜を付着させ(図4
(b))、さらにレジストを除去することにより、所望
の微細パターンが形成される(図4(c))。
3 to 4 are process diagrams showing the steps of the above method. First, the base conductive layer 22 is formed on the substrate 21 (FIG. 3A), and then the lower resist layer 24 and the intermediate layer 2 are formed.
5, each layer is formed in order of the upper resist layer 26 (FIG. 3).
(B)). Next, after a resist pattern 26a having a desired pattern is formed by exposure and development (FIG. 3C), the intermediate layer 25 is patterned by the dry etching method using this resist pattern 26a as a mask (FIG. 3).
(D)). Further, etching is performed to pattern the lower resist layer 24, which is the state shown in FIG. After this, the underlying conductive layer 2 partially exposed
An electrolytic plating film is attached to the exposed portion 22a of 2 (see FIG. 4).
(B)) Further, by removing the resist, a desired fine pattern is formed (FIG. 4 (c)).

【0005】しかし、下地導電層の露出部分に電解メッ
キを行なうにあたり、次に述べるような問題がある。ま
ず第1に、中間層25および下層レジスト層をパターニ
ングする際に用いるドライエッチングにより、下地導電
層表面の露出部分22aが変質し、電解メッキが困難に
なるという点である。これは、ドライエッチング法は酸
素などの反応性に富むガスを使用するため、露出した下
地導電層表面の露出部分22aが損傷を受けるためであ
る。たとえば、下地導電層表面が酸化されることにより
導電性を喪失した場合には、電解メッキが析出できなく
なってしまう。
However, there are the following problems in performing electrolytic plating on the exposed portion of the underlying conductive layer. First, the dry etching used when patterning the intermediate layer 25 and the lower resist layer changes the exposed portion 22a of the surface of the underlying conductive layer, which makes electrolytic plating difficult. This is because the dry etching method uses a highly reactive gas such as oxygen, and the exposed portion 22a of the exposed underlying conductive layer surface is damaged. For example, if the surface of the underlying conductive layer is oxidized to lose its conductivity, electrolytic plating cannot be deposited.

【0006】また、ドライエッチング法を用いない製造
工程を選択した場合や、ドライエッチングによって下地
導電層表面が損傷を受けない場合であっても、レジスト
残査が導電層表面に付着し、良好なメッキ膜が得られな
いこともある。湿式現像あるいはドライエッチングなど
の工程を経ても、不要なレジストが完全に除去できず残
留する場合があり、断線などの欠陥の原因にもなる。
Even when a manufacturing process which does not use the dry etching method is selected, or when the surface of the underlying conductive layer is not damaged by the dry etching, the resist residue adheres to the surface of the conductive layer, which is excellent. The plating film may not be obtained. Even after a process such as wet development or dry etching, unnecessary resist may not be completely removed and may remain, which may cause defects such as disconnection.

【0007】ところで、一般的に電解メッキの前工程と
して電解研磨による処理が行なわれている。電解研摩は
硫酸、りん酸、クロム酸などを主成分とする混合溶液
(電解研摩液)中で、被メッキ物を処理することによ
り、被メッキ表面を改質する工程である。電解研摩によ
って、変質層やレジスト残査を除去すると同時に、被メ
ッキ表面を平坦化する。
By the way, in general, a process by electrolytic polishing is performed as a pre-process of electrolytic plating. Electrolytic polishing is a step of modifying the surface to be plated by treating the object to be plated in a mixed solution (electrolytic polishing solution) containing sulfuric acid, phosphoric acid, chromic acid, etc. as the main components. By electrolytic polishing, the deteriorated layer and the resist residue are removed, and at the same time, the plated surface is flattened.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、従来の
電解研摩液を用いた電解研摩をしたのちに電解メッキを
行なう電解メッキ方法においては、以下の問題がある。
まず、電解メッキ前に電解研摩液を完全に除去すること
は困難であり、残留した電解研摩液が電解メッキ液中に
持込まれて電解メッキ液を汚染してしまうという問題が
ある。また、上述の微細パターン作製方法で従来の電解
研磨液を用いた場合には、レジストの電解研摩液に対す
る耐性が低いため、電解研摩によりレジストパターンが
破壊されてしまうという問題もある。
However, there are the following problems in the conventional electrolytic plating method in which electrolytic polishing is performed using electrolytic polishing liquid and then electrolytic plating is performed.
First, it is difficult to completely remove the electrolytic polishing solution before electrolytic plating, and there is a problem that the remaining electrolytic polishing solution is carried into the electrolytic plating solution and contaminates the electrolytic plating solution. Further, when a conventional electropolishing liquid is used in the above-described fine pattern forming method, there is a problem that the resist pattern is destroyed by electropolishing because the resist has low resistance to the electropolishing liquid.

【0009】本発明の目的は、残留した電解研摩液が電
解メッキ液中に混入しても、電解メッキ液を汚染しない
電解メッキ方法を提供することにある。また、本発明の
他の目的は、レジストパターンを破壊せず、残留した電
解研摩液が電解メッキ液中に混入しても、電解メッキ液
を汚染しない微細パターン作製方法を提供することにあ
る。
An object of the present invention is to provide an electrolytic plating method which does not contaminate the electrolytic plating solution even when the remaining electrolytic polishing solution is mixed in the electrolytic plating solution. Another object of the present invention is to provide a method for producing a fine pattern that does not destroy the resist pattern and does not contaminate the electrolytic plating solution even when the remaining electrolytic polishing solution is mixed into the electrolytic plating solution.

【0010】[0010]

【課題を解決するための手段】実施例を示す図1および
図2に対応づけて説明すると、本発明は、下地導電層2
を電解研摩液により処理する工程と、下地導電層2の上
層に電解メッキ液により電解メッキ膜3を形成する工程
とを含む電解メッキ方法に適用される。そして、下地導
電層2の主成分と電解メッキ膜3の主成分とを同一と
し、かつ、電解研摩液と前記電解メッキ液とを同一成分
とすることにより、上述の目的が達成される。また、本
発明は、下地導電層2の上にレジストパターン(4a、
5a、6a)を形成する工程と、レジストパターン(4
a、5a、6a)の間隙に露出する下地導電層2の表面
を電解研摩液により処理する工程と、電解研摩された下
地導電層2の上に電解メッキ液により電解メッキ膜3を
形成する工程とを含む微細パターン形成方法に適用され
る。そして、下地導電層2の主成分と電解メッキ膜3の
主成分とを同一とし、かつ、電解研摩液と電解メッキ液
とが同一成分であることにより上述の目的が達成され
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to FIGS. 1 and 2 showing an embodiment.
Applied to an electrolytic polishing solution and a step of forming an electrolytic plating film 3 on the upper layer of the underlying conductive layer 2 with an electrolytic plating solution. Then, the above-mentioned object is achieved by making the main component of the underlying conductive layer 2 and the main component of the electrolytic plating film 3 the same, and the electrolytic polishing liquid and the electrolytic plating liquid the same. In addition, the present invention provides a resist pattern (4a,
5a, 6a) and the resist pattern (4
a, 5a, 6a), the step of treating the surface of the underlying conductive layer 2 exposed by the electrolytic polishing solution, and the step of forming the electrolytic plating film 3 on the electrolytically polished underlying conductive layer 2 by the electrolytic plating solution. It is applied to a fine pattern forming method including and. The above-mentioned object is achieved by making the main component of the underlying conductive layer 2 and the main component of the electrolytic plating film 3 the same, and the electrolytic polishing liquid and the electrolytic plating liquid being the same component.

【0011】[0011]

【作用】下地導電層2の主成分と電解メッキ液膜の主成
分を同一とし、また、電解研摩液として電解メッキ液と
同一成分の混合溶液を用いるため、電解研摩処理時に電
解研摩液に溶け出す下地導電層2の成分が電解メッキ膜
3の主成分と同一であり、電解研摩液には電解メッキ液
を汚染する不純物成分が混入しない。したがって、電解
メッキ時に電解研摩液が残留していても電解メッキ液を
汚染するおそれがない。また、レジストパターン(4
a、5a、6a)の間隙に電解メッキをする場合にも、
上述の電解研磨液を用いるため、電解メッキ液を汚染す
るおそれがなく、電解メッキ液に耐えるレジスト材料を
用いれば、レジストパターン(4a、5a、6a)を破
壊するおそれがない。
Since the main component of the underlying conductive layer 2 is the same as the main component of the electrolytic plating liquid film, and a mixed solution of the same components as the electrolytic plating liquid is used as the electrolytic polishing liquid, it dissolves in the electrolytic polishing liquid during the electrolytic polishing treatment. The components of the underlying conductive layer 2 to be ejected are the same as the main components of the electrolytic plating film 3, and the electrolytic polishing liquid does not contain an impurity component contaminating the electrolytic plating liquid. Therefore, even if the electrolytic polishing liquid remains during electrolytic plating, there is no risk of contaminating the electrolytic plating liquid. In addition, the resist pattern (4
a), 5a, 6a)
Since the above electrolytic polishing liquid is used, there is no risk of contaminating the electrolytic plating liquid, and if a resist material that withstands the electrolytic plating liquid is used, there is no risk of destroying the resist patterns (4a, 5a, 6a).

【0012】なお、本発明の構成を説明する上記課題を
解決するための手段と作用の項では、本発明を分かり易
くするために実施例の図を用いたが、これにより本発明
が実施例に限定されるものではない。
In the means and means for solving the above problems which explain the constitution of the present invention, the drawings of the embodiments are used for easy understanding of the present invention. However, the present invention is not limited to this.

【0013】[0013]

【実施例】以下、図1および図2を参照して、本発明の
一実施例を説明する。図1(a)〜(d)および図2
(a)〜(d)は本実施例の工程を示す基板断面図であ
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 (a)-(d) and FIG.
(A)-(d) is a board | substrate sectional drawing which shows the process of a present Example.

【0014】まず、200mm角のシリコンウエハ1の
上に下地導電層2としてマグネトロンスパッタ法を用い
てニッケルを12nm厚に成膜した(図1(a))。つ
づいて、下地導電層2の上にジアゾナフトキノン―ノボ
ラック樹脂系レジスト(商品名:AZ−1350、ヘキ
スト社製)をスピンコート塗布したのち、ベーキング
し、0.3μm厚の下層レジスト層4を形成した。その
上に中間層5として、50nm厚の酸化シリコン膜をス
パッタリング法により形成した。最後にPMMAポジ型
レジスト(商品名:OEBR−1000、東京応化製)
をスピンコート塗布したのち、ベーキングし、0.2μ
m厚の上層レジスト層6を形成した(図1(b))。
First, a 12 nm thick nickel film was formed as a base conductive layer 2 on a 200 mm square silicon wafer 1 by magnetron sputtering (FIG. 1A). Subsequently, a diazonaphthoquinone-novolak resin-based resist (trade name: AZ-1350, manufactured by Hoechst) is spin-coated on the underlying conductive layer 2 and then baked to form a lower resist layer 4 having a thickness of 0.3 μm. did. As the intermediate layer 5, a 50 nm-thick silicon oxide film was formed thereon by a sputtering method. Finally, PMMA positive resist (trade name: OEBR-1000, manufactured by Tokyo Ohka)
Spin coat and then bake to 0.2μ
An upper resist layer 6 having a thickness of m was formed (FIG. 1 (b)).

【0015】図1(c)は、上述の上層レジスト層6を
電子線描画法により露光したのち、現像、ベークし、
0.1〜1μmのライン&スペースのレジストパターン
6aを形成した状態を示している。つぎに、レジストパ
ターン6aをマスクとして、CHF3ガスを用いたドラ
イエッチング法により0.1〜1μmのライン&スペー
スのパターンを中間層5に転写した(図1(d))。さ
らに、パターニングされた中間層5aをマスクとして、
2ガスを用いたドライエッチング法により、同様のパ
ターンを下層レジスト層4に転写し、下層レジストパタ
ーン4aを形成した(図2(a))。ドライエッチング
法によって下層レジストが除去された部分では、下地導
電層が露出するとともに、その表面領域に変質部2aが
生じている。また、導電層の表面にはレジスト残査7が
付着している。
In FIG. 1C, the above-mentioned upper resist layer 6 is exposed by an electron beam drawing method, and then developed and baked,
It shows a state in which a resist pattern 6a having a line & space of 0.1 to 1 μm is formed. Next, using the resist pattern 6a as a mask, a line & space pattern of 0.1 to 1 μm was transferred to the intermediate layer 5 by a dry etching method using CHF 3 gas (FIG. 1 (d)). Further, using the patterned intermediate layer 5a as a mask,
A similar pattern was transferred to the lower resist layer 4 by a dry etching method using O 2 gas to form a lower resist pattern 4a (FIG. 2 (a)). In the portion where the lower layer resist is removed by the dry etching method, the underlying conductive layer is exposed and the altered portion 2a is generated in the surface region thereof. Further, the resist residue 7 is attached to the surface of the conductive layer.

【0016】次に、スルファミン酸ニッケル450g/
l、ほう酸30g/l、ラウリル硫酸ナトリウム0.5
g/lの混合水溶液を電解研摩液として電解研摩を行な
った。下地導電層2にプラス電極を接続し、電解研摩条
件として、0.5〜2mA/cm2、ph3〜4、温度
50℃の下、数〜数十秒間の処理を行なった。その結
果、下地導電層2の変質部2aおよびレジスト残査7が
取り除かれた。電解研摩により、下地導電層2は約2n
m研摩されたが、処理前の下地導電層2の厚さ(12n
m)やパターン線幅に比較し十分小さな値であった。こ
のため、下地導電層2の下のシリコンウエハが露出する
部分はなかった。また、レジストパターン(4a、5
a、6a)が剥がれたり、損傷を受けることはなかった
(図2(b))。
Next, 450 g of nickel sulfamate /
1, boric acid 30 g / l, sodium lauryl sulfate 0.5
Electrolytic polishing was performed using a mixed aqueous solution of g / l as an electrolytic polishing liquid. A positive electrode was connected to the underlying conductive layer 2 and subjected to electrolytic polishing conditions of 0.5 to 2 mA / cm 2 , ph 3 to 4, and a temperature of 50 ° C. for several to several tens of seconds. As a result, the altered portion 2a of the underlying conductive layer 2 and the resist residue 7 were removed. By electropolishing, the underlying conductive layer 2 is about 2n
The thickness of the underlying conductive layer 2 before polishing (12n
m) and the pattern line width were sufficiently small. Therefore, there was no portion under the underlying conductive layer 2 where the silicon wafer was exposed. In addition, the resist patterns (4a, 5
a, 6a) was not peeled off or damaged (FIG. 2 (b)).

【0017】上述の下層レジストパターン4aをステン
シルマスクとして、下地導電層上に電解メッキ膜3を析
出させた状態を示したものが図2(c)である。電解メ
ッキ液として、上述の電解研摩液と同一組成の混合液を
用い、下地導電層にマイナスの電極を接続した。1〜4
mA/cm2、ph3〜4、温度50℃の条件下で電解
メッキを行なった。その結果、約0.2μm厚の電解ニ
ッケルが析出した。
FIG. 2C shows a state in which the electrolytic plating film 3 is deposited on the underlying conductive layer using the lower layer resist pattern 4a as a stencil mask. As the electrolytic plating solution, a mixed solution having the same composition as the above electrolytic polishing solution was used, and a negative electrode was connected to the underlying conductive layer. 1-4
Electrolytic plating was performed under the conditions of mA / cm 2 , pH 3 to 4, and temperature of 50 ° C. As a result, electrolytic nickel having a thickness of about 0.2 μm was deposited.

【0018】次に、基板を純水により洗浄し乾燥したの
ち、アセトンを用いて上層レジストパターン6aを剥離
除去した。さらに中間層パターン5aおよび下層レジス
ト層パターン4aをドライエッチ法により除去し、所定
パターンのニッケル膜を得た(図2(d))。
Next, the substrate was washed with pure water and dried, and then the upper resist pattern 6a was peeled off using acetone. Further, the intermediate layer pattern 5a and the lower resist layer pattern 4a were removed by a dry etching method to obtain a nickel film having a predetermined pattern (FIG. 2 (d)).

【0019】以上のように作製したニッケル膜は、膜質
が良好で膜厚の再現性もよい。これは、電解メッキ膜3
の主成分と下地導電層2の材質を同一の金属(ニッケ
ル)とし、かつ、電解研磨液と電解メッキ液とを同一成
分にしたためである。すなわち、前者により、電解研磨
工程で電解研磨液中に溶出する金属イオンと電解メッキ
液中に含有する金属イオンが同一となる。したがって、
電解メッキ工程で、電解メッキ液中に電解研磨液が混入
した場合でも、両液は同一成分であるため電解メッキ液
を汚染することにならないからである。
The nickel film produced as described above has good film quality and good film thickness reproducibility. This is the electrolytic plating film 3
This is because the main component and the material of the underlying conductive layer 2 are the same metal (nickel), and the electrolytic polishing liquid and the electrolytic plating liquid are the same component. That is, by the former, the metal ions eluted in the electrolytic polishing solution in the electrolytic polishing step and the metal ions contained in the electrolytic plating solution become the same. Therefore,
This is because even if the electrolytic polishing solution is mixed in the electrolytic plating solution in the electrolytic plating step, both solutions do not contaminate the electrolytic plating solution because they have the same components.

【0020】なお、本実施例においては多層のレジスト
パターンを用いた場合について説明したが、レジストパ
ターンの作製方法はこれに限定されない。また、本実施
例においてはニッケルメッキの場合について説明した
が、電解メッキで析出しうる他のすべての金属にも適用
できる。他の金属を用いる場合には、該金属に最適な電
解研磨条件や電解メッキ条件を自由に選択することがで
きるため、とくに金属の種類が限定されることはない。
さらに、本発明は、電解メッキの代りに無電解メッキを
行なう場合についても適用できる。
Although the case of using a multilayer resist pattern has been described in the present embodiment, the method for producing the resist pattern is not limited to this. Further, although the case of nickel plating has been described in the present embodiment, it can be applied to all other metals that can be deposited by electrolytic plating. When another metal is used, the optimum electropolishing conditions and electroplating conditions for the metal can be freely selected, and the type of metal is not particularly limited.
Furthermore, the present invention can be applied to the case of performing electroless plating instead of electrolytic plating.

【0021】[0021]

【発明の効果】以上説明したように、本発明によれば、
電解メッキ液成分と電解研摩液成分が同一であり、か
つ、下地導電層の主成分と電解メッキ膜の主成分とが同
一であるため、電解研摩液が残留しても電解メッキ液を
汚染することがない。また、微細パターンを作製する場
合に、レジスト材料の選択にあたって電解メッキ液組成
に対する耐性のみを考慮すれば、電解研摩処理によりレ
ジストパターンが破壊されることがない。
As described above, according to the present invention,
Since the electrolytic plating solution component and the electrolytic polishing solution component are the same and the main component of the underlying conductive layer and the electrolytic plating film are the same, even if the electrolytic polishing liquid remains, the electrolytic plating liquid is contaminated. Never. Further, in the case of producing a fine pattern, if only the resistance to the electrolytic plating solution composition is taken into consideration when selecting the resist material, the resist pattern is not destroyed by the electrolytic polishing treatment.

【図面の簡単な説明】[Brief description of drawings]

【図1】本実施例の微細パターン作製方法を示す工程図
である。
FIG. 1 is a process drawing showing the method for producing a fine pattern of the present embodiment.

【図2】図1に続く工程を示す工程図である。FIG. 2 is a process drawing showing a process that follows FIG.

【図3】従来例の微細パターン作製方法を示す工程図で
ある。
FIG. 3 is a process drawing showing a conventional fine pattern manufacturing method.

【図4】図3に続く工程を示す工程図である。FIG. 4 is a process drawing showing a process that follows FIG.

【符号の説明】[Explanation of symbols]

2 下地導電層 3 電解メッキ膜 2 Underlayer conductive layer 3 Electroplating film

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 下地導電層を電解研摩液により処理する
工程と、前記下地導電層上に電解メッキ液により電解メ
ッキ膜を形成する工程とを含む電解メッキ方法におい
て、 前記下地導電層の主成分と前記電解メッキ膜の主成分と
が同一であり、かつ、前記電解研摩液と前記電解メッキ
液とが同一成分であることを特徴とする電解メッキ方
法。
1. An electrolytic plating method comprising: a step of treating an underlying conductive layer with an electrolytic polishing solution; and a step of forming an electrolytic plating film on the underlying conductive layer with an electrolytic plating solution, the main component of the underlying conductive layer. And the main component of the electrolytic plating film is the same, and the electrolytic polishing liquid and the electrolytic plating liquid are the same component.
【請求項2】 前記下地導電層の主成分と前記電解メッ
キ膜の主成分とがニッケルであり、かつ、前記電解研摩
液と前記メッキ液とがスルファミン酸ニッケルを含有す
ることを特徴とする請求項1の電解メッキ方法。
2. The main component of the underlying conductive layer and the main component of the electrolytic plating film are nickel, and the electrolytic polishing liquid and the plating liquid contain nickel sulfamate. Item 1 is an electrolytic plating method.
【請求項3】 下地導電層上にレジストパターンを形成
する工程と、前記レジストパターンの間隙に露出する前
記下地導電層の表面を電解研摩液により処理する工程
と、電解研摩された前記下地導電層の上に電解メッキ液
により電解メッキ膜を形成する工程とを含む微細パター
ン作製方法において、 前記下地導電層の主成分と前記電解メッキ膜の主成分と
が同一であり、かつ、前記電解研摩液と前記電解メッキ
液とが同一成分であることを特徴とする微細パターン作
製方法。
3. A step of forming a resist pattern on the underlying conductive layer, a step of treating the surface of the underlying conductive layer exposed in the gaps of the resist pattern with an electrolytic polishing liquid, and the electrolytically polished underlying conductive layer. In the method for producing a fine pattern, which comprises a step of forming an electrolytic plating film on the above with an electrolytic plating liquid, the main component of the underlying conductive layer and the main component of the electrolytic plating film are the same, and the electrolytic polishing liquid. And a method for producing a fine pattern, wherein the electrolytic plating solution and the electrolytic plating solution have the same components.
【請求項4】 前記下地導電層の主成分と前記電解メッ
キ膜の主成分とがニッケルであり、かつ、前記電解研摩
液と前記メッキ液とがスルファミン酸ニッケルを含有す
ることを特徴とする請求項3の微細パターン作製方法。
4. The main component of the underlying conductive layer and the main component of the electrolytic plating film are nickel, and the electrolytic polishing liquid and the plating liquid contain nickel sulfamate. Item 3. A method for producing a fine pattern according to item 3.
JP7011968A 1995-01-27 1995-01-27 Electroplating and fine pattern formation Pending JPH08199389A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7011968A JPH08199389A (en) 1995-01-27 1995-01-27 Electroplating and fine pattern formation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7011968A JPH08199389A (en) 1995-01-27 1995-01-27 Electroplating and fine pattern formation

Publications (1)

Publication Number Publication Date
JPH08199389A true JPH08199389A (en) 1996-08-06

Family

ID=11792426

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7011968A Pending JPH08199389A (en) 1995-01-27 1995-01-27 Electroplating and fine pattern formation

Country Status (1)

Country Link
JP (1) JPH08199389A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010081275A1 (en) * 2008-12-30 2010-07-22 北京大学 Micro machining method for a substrate on an underlay

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010081275A1 (en) * 2008-12-30 2010-07-22 北京大学 Micro machining method for a substrate on an underlay

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