JPH08195970A - Video signal processor - Google Patents

Abstract

PURPOSE: To miniaturize a processor and to accelerate a conversion speed by directly converting digital RGB color data into digital composite video data by a semiconductor memory storing a conversion system beforehand. CONSTITUTION: The digital RGB data 252-254 are converted into the digital composite video data 258-260 by the matrix conversion ROM 231 of the semiconductor memory storing the conversion system of the digital RGB data. Among the digital composite video data, luminance signals (Y signals) 258 are analog converted in a D/A converter 235 as they are and red difference signals (R-Y signals) 259 and blue difference signals (B-Y signals) 260 are digitally modulated in digital balanced modulation circuits 238 and 239 and then, analog converted in the D/A converters 236 and 237. By this constitution, this processor is miniaturized, the conversion speed is accelerated and conversion accuracy is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention uses a digital-analog converter to convert digital RGB data into a CRT.
A composite video signal to be displayed on a display device (eg, NTS NTS
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device for converting into C format) and a video device including the same.

[0002]

2. Description of the Related Art As a conventional video signal processing device, for example, a dedicated monitor device is provided with R (red), G (green) and B (blue).
There is a device that outputs an analog signal representing the amplitude value of each color to display a predetermined image in color.

This video signal processing apparatus stores image data in a video RAM, reads image data for each pixel from the video RAM, and stores R, G, B color data using the image data as an address signal. The color data RAM is addressed and the color data read from this RAM is D / A converted to obtain analog RGB.
Generate a signal. A color image can be displayed by outputting this analog RGB signal to the monitor device.

When a composite video signal (combodit video signal) conforming to the NTSC system is output, an operation is performed based on the R, G, B color data output from the color data RAM, and a brightness signal is obtained from the operation result. And two color difference signals were created to obtain a composite video signal.

As another example, digital RGB color data is once converted into analog RGB color data by using a D / A converter.
A signal is converted, and these three signals are added and subtracted in an analog manner to generate a luminance signal (Y), a red color difference signal (RY), and a blue color difference signal (BY) to obtain a composite video signal. Was there.

[0006]

However, according to the conventional video signal processing device, since the luminance signal and the color difference signal are obtained by calculation for each pixel, the device becomes large in size, the power consumption increases, and the conversion speed increases. It had problems such as being slow.

When performing analog processing, NT
In both the SC method and the PAL method, it is difficult to handle a high-quality composite signal because it is a highly accurate analog signal.

It is an object of the present invention to reduce the size of a device, reduce power consumption, improve conversion speed, in a video signal processing device.
The purpose is to improve conversion accuracy.

Another object of the present invention is a MOS which has not been available in the past.
It is to provide a modulation circuit suitable for a digital integrated circuit and enable generation of a high-quality composite video signal with few harmonic components.

Another object of the present invention is a MOS which has not been hitherto known.
By providing a color burst signal generation circuit suitable for digital integrated circuit, it is possible to generate a high quality composite video signal.

Another object of the present invention is a MOS which has not been hitherto known.
By providing a digital-analog converter suitable for digital integrated circuit, it is possible to generate a high-quality composite video signal with extremely small carrier leak and phase shift.

[0012]

A video signal processing device of the present invention is a conversion device for converting a color difference signal represented by a digital value designating a color of each dot on a display screen into a color difference signal represented by an analog value. In the video signal processing device including means, the conversion means includes a color burst signal generation circuit, and the color burst signal generation circuit is responsive to the frequency of the color burst signal subcarrier during the color burst signal generation period. The maximum and minimum values of the color burst signal are output alternately, and during the color burst signal generation period,
It is characterized in that an intermediate value between the maximum value and the minimum value of the color burst signal is output.

Further, the color burst signal generation circuit includes a first terminal for supplying a maximum value of the color burst signal, a second terminal for supplying a minimum value of the color burst signal, and the first and the first terminals. Two resistance means connected in series between two terminals, each connected between the connection point of the first terminal, the second terminal and the resistance means and the output terminal of the color burst signal. And a switch means.

Further, the conversion means further comprises a balanced modulation circuit for performing balanced modulation of the two color difference signals represented by the digital value, and a first digital-analog conversion for the luminance signal represented by the digital value. And a second and a third digital-analog converter for the two color difference signals represented by the digital values output from the balanced modulation circuit, and the second and the third digital-analog converters. The converter outputs an intermediate value of analog output during a period other than the display period, and the output terminals of the first, second and third digital-analog converters and the color burst signal generation circuit are It is commonly connected to a bipolar transistor through a resistance means that determines an output level, and a composite video signal formed by combining the signals is output from the bipolar transistor. The door to wherein there.

Furthermore, the video equipment of the present invention comprises the video signal processing device, a video display controller for providing image data to the video signal processing device, a video data storage device for storing the image data, and the video signal processing. Interface means for transmitting the composite video signal output from the device to the display device.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION The video signal processing apparatus of the present invention will be described in detail below.

FIG. 1 shows the entire system of a video equipment for displaying an image based on image data on a CRT screen. However, the sound generator is omitted. Reference numeral 101 is a CPU that controls the whole. A program for controlling the entire system is stored in the ROM 102, and data, calculation results, etc. are temporarily stored in the RAM 103. 104
Is a video signal processing device (video color encoder) of the present invention, and 105 is a video display controller for providing image data to the video signal processing device 104.
The image data is data of sprite (moving image) and background (background), and is a video RAM (VRAM) 1
It is stored in 06. The video signal processing device 104 generates an analog RGB signal as an output A and a composite video signal as an output B, and outputs the interfaces 107, 1
It is supplied to the television receiver 109 via 08 and an image is displayed. The analog RGB signal is directly C as a dedicated monitor.
The RT and the composite video signal are given to the CRT via the receiving circuit. With the configuration of FIG. 1 described above, an image based on the image data can be displayed on the CRT screen of the television receiver 109.

FIG. 2A shows an embodiment of the video signal processing device 104 shown in FIG. 221 is the CPU 101
A data bus for transferring data to and from (Fig. 1).
22 is a video display controller 105 (FIG. 1)
A data bus for transferring data to and from. The data on the data bus 221 is input to the address register 224 and the color table RAM 226, and the data on the data bus 222 is input to the address selector 225. The address selector 225 selects one of the data of the address register 224 and the data of the data bus 222 as an address signal. Reference numeral 226 is a color table RAM (color palette) for storing color data. The read color data is a dot clock with a color code sent from the display controller 105 for designating the color of each dot on the display screen as an address. Is latched by the latch circuit 227 in accordance with Latch circuit 227
Color data is D / A converted by the D / A converters 228, 229 and 230 for each basic color of R, G and B,
Alternatively, the luminance signals Y and R− are stored in the matrix ROM 231 that stores the signal conversion matrix, that is, the signal conversion method.
It is converted into Y and BY color difference signals. 232 is C
Address signals A0 to A2, a chip select signal CS, a write signal WR, a read signal RD, an output control signal CESEL and the like are input from the PU1 to receive the address register 22.
4, address selector 225, color table RAM2
26, a latch circuit 227, a control signal generation circuit 233, and the like. The control signal generation circuit 233 inputs the oscillation signal of, for example, 21.47727 MHz from the oscillation circuit 23A, and outputs the horizontal and vertical synchronization signals HSYN.
C, VSYNC, dot clock CK, color difference signal subcarrier, etc. are output. Both sync signals HSYNC, VSYNC,
The dot clock CK is also supplied to the video display controller 105. D / A converters 228, 2
29 and 230 are digital RGB from the latch circuit 227.
The signal is received and converted into an analog RGB signal, and the sync signal composite circuit 234 composites and outputs the horizontal and vertical sync signals. The analog RGB signal and the composite synchronizing signal are output from the analog RGB signal output circuit 241A. Balance modulation circuits 238 and 239 are matrix ROMs
The color difference signals R-Y and B-Y from the H.
The color difference signal subcarriers different from each other by 0 ° digitally perform balanced modulation. The balanced modulated RY and BY signals and the luminance signal Y are D / A converters 235, 236 and 23.
D / A conversion is performed at 7.

Further, the burst circuit 240 and the D / A converter 242 to which the burst generating subcarrier is input are 8 to 8 during the back porch period of the horizontal blanking period including the horizontal synchronizing signal.
A burst signal is output by inserting 9 cycles. The luminance signal Y is superposed with the synchronizing signal by the D / A converter 235. The luminance signal Y, the color difference signals RY and BY, and the burst signal are output at a predetermined phase and a predetermined timing, and converted into a composite video signal by the synthesizing circuit 241B.

FIG. 2 (b) is a diagram in which the main part of the present invention is extracted from FIG. 2 (a). Digital RGB color data is provided for each 1 bit, for a total of 3 bits. Then
It is possible to express a total of eight colors by combining the three primary colors. On the other hand, the digital composite video data consists of 3 bits for the Y signal, 3 bits for the BY signal, and 3 bits for the RY signal, for a total of 9 bits.

In FIG. 2B, digital RGB data indicated by 252, 253, and 254 are converted into 25 by the signal conversion matrix of the matrix ROM 231.
It is converted into digital composite video data indicated by 8, 259 and 260. Table 1 below shows the correspondence between digital RGB data and digital composite video data.
Shown in

[0022]

[Table 1]

The binary numbers in the table are data processed in the video signal processing device of the present invention. On the other hand, 10
The decimal number indicates an analog value when D / A conversion is performed on binary data. In order to facilitate understanding of the present invention, analog values are represented by decimal numbers.

Of the digital composite video data, 258 Y signals are D / A converted as they are.
The RY signal of 59 and the BY signal of 260 are 238 and 2
It is digitally balanced-modulated by the digital balancing circuit 39 and then D / A converted.

Next, a concrete embodiment of the matrix ROM 231 of FIG. 2 is shown in FIG. In this example, each of the digital RGB color data has 3 bits, and a total of 9 bits are provided. Then, it is possible to represent a total of 512 colors by combining the three primary colors. On the other hand, the digital composite video data is Y
The signal is composed of 5 bits, the RY signal is composed of 5 bits, and the BY signal is composed of 5 bits, that is, a total of 15 bits.

In FIG. 3, the matrix ROM 231
Is a semiconductor memory device in which data for 512 colors is stored in advance. Table 2 shows data stored in the semiconductor memory device for 50 representative colors out of 512 colors. Black +7 colors x 7 gradations is a typical 50 colors.

Here, a method of converting RGB color data into a luminance signal Y will be described. As is well known, the luminance signal Y is obtained by the equation (1).

Y = 0.3R + 0.59G + 0.11B (1) 0 ≦ R ≦ 1, 0 ≦ G ≦ 1, 0 ≦ B ≦ 1, 0 ≦ Y ≦ 1 This equation (1) is expressed as 0 ≦ Y ′ ≦ 31, 0 ≦ R ′ ≦ 7, 0 ≦
To use in the range of G'≤7, 0≤B'≤7, 31
Multiply by / 7 to convert to Y '= 1.33R' + 2.61G '+ 0.49B' ... (1) '.

Next, the color difference signal RY is obtained from the following equation.

R−Y = R− (0.3R + 0.59G + 0.11B) = 0.7R−0.59G−0.11B (2) 0 ≦ R ≦ 1, 0 ≦ G ≦ 1, 0 ≦ B ≦ 1, −0.7 ≦ R−
Y ≦ 0.7 This equation (2) is expressed by −15 ≦ R′−Y ′ ≦ 15, 0 ≦ R ′ ≦
7, 0 ≦ G ′ ≦ 7, 0 ≦ B ′ ≦ 7 Multiply by 15 / 0.7 × 7 for use, R′−Y ′ = 2.14R′−1.80G′−0. 34B '... (2)' Next, the color difference signal BY is obtained from the following equation.

B−Y = B− (0.3R + 0.59G + 0.11B) = − 0.3R−0.59 G + 0.89B ... (3) 0 ≦ R ≦ 1, 0 ≦ G ≦ 1, 0 ≦ B ≦ 1, −0.89 ≦ B
−Y ≦ 0.89 This equation (3) is expressed by −15 ≦ B′−Y ′ ≦ 15, 0 ≦ R ′ ≦
For use in the range of 7, 0 ≦ G ′ ≦ 7, 0 ≦ B ′ ≦ 7, multiply by 15 / 0.89 × 7 to obtain B′−Y ′ = − 0.72R′−1.42G ′. + 2.14B '... (3)' The values of the luminance signal and the color difference signal are obtained based on the above formulas (1) ', (2)', and (3) ', and the rounded values are shown in Table 2 below.
Shown in

[0032]

[Table 2]

The decimal numbers used in the table are R,
G, B → Y, R−Y, and B−Y are numerical values used to facilitate understanding, and are actually processed as binary data.

FIG. 4 shows a so-called vector display result obtained by converting the above-mentioned representative digital RGB color data of 50 colors into digital composite video data by the matrix ROM. That is, FIG. 4 defines BY on the horizontal axis and RY on the vertical axis, and the values of BY in Table 2 and R
It is a plot of the -Y value. It will be understood from FIG. 4 that various kinds of colors can be expressed by combining the values of the signals.

Digital RGB color data is applied to the nine address selection signal (address signal) input terminals of the semiconductor memory device. By performing the read operation of the semiconductor memory device, the 15 signal output terminals have: a luminance signal (Y signal) of 5 bits, a red color difference signal (RY signal) of 5 bits, and a blue color difference signal (B). -Y signal) is divided into 5 bits and output. With such a circuit configuration, digital composite video data corresponding to digital RGB color data can be obtained. 302 in FIG.
Is a flip-flop for adjusting the time shift between the data, and the data for each dot is latched in synchronization with the dot clock 306 obtained from the control unit 232 of FIG. However, if the read time of the semiconductor memory device is sufficiently faster than the cycle of one dot of data, the flip-flop is unnecessary.

Next, a first embodiment of the balanced modulation circuits 238 and 239 of FIG. 2 will be described.

The digital balanced modulation circuit will be described by taking the RY signal as an example. FIG. 5 shows an example of a 3-bit digital balanced modulation circuit. Reference numeral 530 is a pre-modulation data input terminal output from the matrix ROM 231, 531 is a modulation clock input terminal, and 532 is a post-modulation data output terminal connected to the D / A converter 236. 533 is an inverter, 5
34 is an AND gate and 535 is an OR gate. 53
When the logic of the modulation clock of 1 is 1, a signal having the same logic value as the data input from 530 is output to the output terminal 532, but when the logic of the modulation clock 531 is 0, it is input from the 530 to the output terminal. A signal having an inverse logic value to that of the data is output. Table 3 shows the relationship between the data before modulation and the data after modulation for the above eight colors. FIG. 7 is a waveform diagram showing the operating state of the circuit of FIG. Terminal 531 of FIG.
7 (a) (c) is input to the output terminal 532, the normal logic value and the inverted logic value of the data input from the terminal 530 are output as shown in FIG. 7 (b) (d). To be done. FIG. 6 is also a diagram showing the operating state of the circuit of FIG. When the clock of FIG. 6A is input to the terminal 531 of FIG. 5 and the data (expressed in decimal number) as shown in FIG. 6B is input to the terminal 530, the terminal 532 of FIG. c)
The data like is output.

[0038]

[Table 3]

In the above table and FIGS. 6 and 7, the data is expressed by using decimal numbers, but in reality, the data is processed as binary numbers.

By inputting the chrominance signal subcarrier (3.58 MHz in the NTSC system and 4.43 MHz in the PAL system) to the modulation clock input terminal 531, it is possible to obtain a chrominance signal output that is balanced-modulated.

By dividing the frequency of the clock signal having, for example, twice the frequency of the chrominance signal subcarrier, two chrominance signal subcarriers that are 90 degrees out of phase can be created. One is the modulation clock of the RY signal and the other is the B-
By using it as the modulation clock of the Y signal, as shown in FIG. 6, modulated outputs of the RY signal and the BY signal can be obtained.

Next, a second embodiment of the balanced modulation circuits 238 and 239 of FIG. 2 will be described. The digital balanced modulation circuit will be described by taking the RY signal as an example. FIG. 8 shows an example of a 5-bit digital balanced modulation circuit. (The exact same circuit as in FIG. 8 is needed for the BY signal.)
Reference numerals 30 to 834 denote pre-modulation data input terminals output from the matrix ROM 231. 830 is a high-order bit, and weights are sequentially reduced from 831 to 834.
4 is the least significant bit. 835-839 is D / A
It is a post-modulation data output terminal connected to the converter 236, and 835 is a higher-order bit, the weight is gradually reduced from 836 to 839, and 839 is the lowest-order bit. 8
Reference numeral 40 is a modulation clock input terminal to which the color difference signal subcarrier is input, and 841 is a modulation zero signal input terminal to which the modulation zero signal generated at the phase change point of the color difference signal subcarrier is input. When the logic of the modulation clock is 1, a signal having the same logical value as the input signal is output to the output terminal, but when the logic of the modulation clock is 0, a signal having the opposite logical value to the input signal is output to the output terminal. . Then, when the logic of the modulation zero signal is 1, 835 is logic 1, 836 to 8 regardless of the input state.
39 outputs a logic 0. A color difference signal before modulation input to the balanced modulation circuit of the present invention, a color difference signal subcarrier serving as a modulation clock, a modulation zero signal generated at a phase change point of the color difference signal subcarrier, and a balance based on these signals. Table 4 below shows the relationship between the modulated color difference signal and the analog value after D / A conversion by the D / A converter 236.

The outputs 835 to 839 in FIG.
It is input to the D / A converter of FIG. 12 which will be described later. 835 to 1232, 836 to 1233, 83
7 to 1234, 838 to 1235, 839 to 123
6 are input respectively. The modulation zero signal of 841 is shown in FIG.
It is also input to 1231 of 2.

[0044]

[Table 4]

Therefore, when the logic of the modulated zero signal is 1, the analog value output from the D / A converter 236 becomes zero. However, in the table, the D / A converter output is -1.5
This is an example when the amplitude is from (V) to 1.5 (V), and the D / A conversion output when the logic of the modulation zero signal is 1 is generally (maximum output level of D / A conversion output − It is defined as the minimum output level of the D / A conversion output) / 2, that is, the median of the D / A conversion outputs. For example, a frequency six times as high as the color difference signal subcarrier frequency is applied to the clock signal input terminal 255,
The frequency is divided by the control signal generation circuit 233, and the frequency is divided into FIG.
By generating the pulses of (b), FIG. 9 (d), and FIG. 9 (e),
The pulse shown in FIG. 9A is converted into an RY modulation clock signal, as shown in FIG.
The pulse of (b) is RY modulation zero signal, the pulse of FIG. 9 (d) is BY modulation clock signal, the pulse of FIG. 9 (e) is balanced modulation, and the balanced modulation is performed. By D / A converting the subsequent color difference signals, the RY analog output of FIG. 9C and the BY analog output of FIG. 9F can be obtained. By such an operation, a balanced modulation circuit capable of outputting a positive value, zero, that is, a central value, a negative value and three values is realized. The RY modulation clock and B
-The Y modulation clocks are 9
The color difference signal subcarriers are 0 ° out of phase.

Next, an embodiment of the burst signal generating circuit 240 and the burst D / A converter 242 shown in FIG. 2 will be described. FIG. 10 shows a circuit example of the burst signal generation circuit 240 and the burst D / A converter 242.
Burst signal generation circuit 240 and burst D / A converter 2
42 constitutes a color burst signal generation circuit. The burst signal generation circuit 240 uses the digital color burst signal 2
40A is output. 1032 burst high level to 1
Apply a low burst level to 034. Resistance element 103
By using resistors of the same value for 5 and 1036,
At the midpoints of 1035 and 1036, the midpoint voltage of the burst high level and the burst low level is generated. A signal whose logic becomes 0 (a signal shown in FIG. 11A) only during a period of generating a burst signal is added to 1030, and a subcarrier signal for burst generation (a signal shown in FIG. 11B) is added to 1031. By adding, the analog burst data 267 (signal shown in FIG. 11C) is obtained by the operation shown in Table 5.

In FIG. 10, 1037 is an inverter,
1038 is NOR, 1040, 1042, 1044
P channel Metal Oxid Semico
nductor Field Effect Trans
istor (MOSFET), 1041, 1043, 1
Reference numeral 045 is an N channel MOSFET. The pair of MOSFETs form a transmission gate.

[0048]

[Table 5]

Next, an embodiment of the D / A converters 236 and 237 will be shown. FIG. 12 shows a circuit example of the D / A converter. A blanking signal indicating the display period is input to 1230. When the blanking signal is 1, it is outside the display period. The same modulation zero signal as 841 in FIG. 8 is input to 1231. The modulated color difference signals output to 835 to 839 of FIG. 8 are input to 1232 to 1236 as described above. Inverter 1243, NAND1241
Constitutes a decoder, and outputs 0 to one of the NORs 1242 by the logic of 1232 to 1236. N
The OR 1247 outputs 0 when it is outside the display period and when the color difference signal subcarrier changes. Upon receipt of this output, NOR124
2 outputs all 0s. Therefore, at this time, a pair of MOSFs connected to the center of the dividing resistor composed of the resistor 1244
ET is turned on, and the median value of high level and low level is output to 1238. On the other hand, when the output of the NOR 1247 is 1, one of the NORs 1242 that inputs the output of the decoder outputs 1 and an analog output corresponding to the logic of 1232 to 1236 is obtained at 1238.

That is, in the D / A converter of the present invention, when the blanking signal is logic 1, or the modulation zero signal is logic 1.
In the case of, it outputs the high level and the low level middle value. In other cases, any one set of P-channel MOSFET 1245 and N-channel MOSFE determined by the value of the digital data after balanced modulation of 1232 to 1236.
T1246 becomes conductive and the corresponding level is output. When there is no color difference component (that is, when achromatic color such as black), the digital data before balanced modulation is 10000 (2
Susumu). This data is balanced and modulated 10,000
Although the data is (binary) and 01111 (binary), the D / A converter of the present invention outputs the central values of high level and low level, which are the same as those at the time of blanking. FIG.
An analog output waveform is shown in FIG. It can be seen from FIG. 13 that the phase of the analog output waveform is determined by the phase of the modulated zero signal and is not related to the amplitude of digital data. Moreover, since the switching of the balanced modulation is always performed in the modulation zero state, transiently incorrect data is not output.

Next, a circuit example of the synthesis circuit 241B in FIG. 2 will be shown. Digital R-balanced with digital Y signal
The Y signal, the digital BY signal, and the digital color burst signal are converted into analog signals by independent D / A converters, and are combined by the combining circuit of 241B to output a composite video signal.

FIG. 14 is a circuit diagram showing an embodiment of the synthesis circuit 241B shown in FIG. The Y signal, the RY signal, the BY signal, and the color burst signal converted into the analog value are input to the base of the 1438 bipolar transistor and combined with the 1436 resistance element.
The composite video signal is output to the terminal 5.

By synthesizing the Y signal, the RY signal, the BY signal, and the color burst signal in the configuration shown in FIG. 14, by adjusting each resistance value of 1436 in FIG. The phase and amplitude of the signal can be adjusted independently, and the hue adjustment and correction on the CRT display are possible.

[0054]

As described above, according to the present invention, digital RGB
Since the color data can be directly converted into the digital composite video data without being converted into the analog signal, the conversion with high stability and high accuracy can be performed. Further, according to the conventional technology, the place where the D / A converter, the analog adder / subtractor circuit, and the A / D converter are required is replaced with the semiconductor memory device, so that the device can be downsized, the power consumption can be reduced, and the speed can be increased. It is possible to plan.

Moreover, since the composite video data of different tones can be obtained for the same RGB color data by changing the stored contents of the semiconductor memory device, the displayable colors can be displayed independently for each color, and the Y signal, There is also an effect that the RY signal and the BY signal can be adjusted independently.

Further, according to the first embodiment of the balanced modulation circuit of the present invention, the balanced modulation of the two color difference signals can be performed by the digital circuit. Therefore, even if the MOS digital integrated circuit is used, both the amplitude and the phase angle are accurate. It is possible to provide a video signal processing device that generates a high quality composite video signal that has not been obtained in the past.

Further, according to the second embodiment of the balanced modulation circuit of the present invention, in digital balanced modulation, the D / A converted output of the modulated data has a positive value, a central value, Since the output is close to a sine wave because the balanced modulation is performed so that it has three negative values, it has less harmonic components than a mere square wave, and is a high-quality composite image that could not be obtained in the past. A video signal processing device that generates a signal can be provided.

Further, according to the color burst signal generation circuit of the present invention, the high level (maximum value) and the low level (minimum value) of the color burst signal are alternately generated by the MOS digital circuit to generate the color burst signal. By not outputting the intermediate level when not doing so, it has become possible to provide a video signal processing device that generates a composite video signal having both excellent amplitude characteristics and phase characteristics.

According to the D / A converter of the present invention, the carrier level does not occur at all because the output level becomes a constant value when there is no blanking state or color difference component. In addition, no phase shift occurs due to the difference in amplitude,
Moreover, since a phenomenon in which incorrect data is transiently output (glitch phenomenon) does not occur at all, it becomes possible to generate a high-quality composite video signal which has not been available in the past.

Further, according to the synthesizing circuit of FIG. 14 of the present invention, the luminance signal, the two color difference signals and the color burst signal can be D / A converted and adjusted by four independent D / A converters. A high quality composite video signal can be obtained by synthesizing the composite video signal by any means (for example, a resistor) to obtain the composite video signal. In addition, it is possible to adjust and correct the hue, and it is possible to faithfully reproduce the color information.

[Brief description of drawings]

FIG. 1 is a block diagram showing a color image processing system constituting a video device.

2A and 2B are block diagrams showing a video signal processing device of the present invention.

FIG. 3 is a diagram showing a matrix ROM of the present invention.

FIG. 4 is a diagram showing a vector display result by the matrix ROM of FIG.

FIG. 5 is a diagram showing a first embodiment of a balanced modulation circuit of the present invention.

6A to 6C are waveform charts showing an operating state of the balanced modulation circuit of FIG.

7A to 7D are waveform charts showing the operating state of the video signal processing device having the balanced modulation circuit of FIG.

FIG. 8 is a diagram showing a second embodiment of the balanced modulation circuit of the present invention.

9A to 9F are waveform charts showing operating states of the balanced modulation circuit of FIG.

FIG. 10 is a diagram showing a color burst signal generation circuit of the present invention.

11A to 11C are diagrams showing an operating state of the color burst signal generation circuit of FIG.

12A to 12E are diagrams showing a digital-analog converter of the present invention.

13 is a diagram showing an operating state of the digital-analog converter shown in FIG.

FIG. 14 is a diagram showing a synthesis circuit of the present invention.

[Explanation of symbols]

101 ... CPU 102 ROM 103 RAM 104 Video signal processing device (video color encoder) 105 Video display controller 106 ... Video RAM 107, 108 Interface 109 Television receiver 221, 222 Data bus 224 Address register 225 Address selector 226 ... Color table RAM 227 ... Latch circuit 228, 229, 230 ... D / A converter 231, ... Matrix ROM 232 ... 233 ... Control signal generation circuit 23A ... Oscillation circuit 234 ... Synchronous signal composite circuit 235, 236, 237 ...・ D / A converters 238, 239 ・ ・ Balanced modulation circuit 240 ・ ・ ・ ・ Burst signal generation circuit 240A ・ ・ ・ Digital color burst signal 241A ・ ・ ・ Analog RGB signal output circuit 241B ・ ・・ ・ Combining circuit 242 ・ ・ Burst D / A converter 251 ・ ・ Sync signal input terminal 252 ・ ・ Digital R color data input terminal 253 ・ ・ ・ ・ Digital G Color data input terminal 254 ··· Digital B color data input terminal 255 ··· Clock signal input terminal 258 ··· Digital Y data 259 ··· Digital RY data 260- ・ Digital BY data 264- ・ Analog Y data 265- ・ ・ Analog RY data 266- ・ ・ ・ ・ ・B-Y data 267..Analog burst data 269 ..... Composite video signal output terminal 270 ..... R-Y balanced modulation color difference signal carrier signal 271 .. Color difference signal carrier signal for BY balanced modulation 272 .. Burst signal control signal 273 .. Subcarrier signal for burst generation 302 .. Flip-flop 303 ..・ Digital R color data input terminal 304 ・ ・ ・ ・ ・ ・ Digital G color data input terminal 305 ・ ・ Digital B color data input terminal 306 ・ ・ ・ ・ ・ ・ Dot clock input terminal 307・ Digital Y data 308 ・ ・ Digital RY data 309 ・ ・ Digital BY data 310 ・ ・ Address input terminal of semiconductor memory device 311 ··· Data output terminal of semiconductor memory device 530 ··· Data input terminal before modulation 531 ··· Modulation clock input terminal 532 ··· Data output terminal after modulation 830 , 831, 832, 833, 834 ··· pre-modulation data input terminal 835, 836, 837, 838, 839 · · post-modulation data output terminal 840 ··· modulation clock input terminal 841 ··· modulation Zero signal input terminal 1030 ··· Burst signal control signal input terminal 1031 ··· Burst generation subcarrier signal input terminal 1032 ··· Burst high level input terminal 1033 ···・ Analog burst data output terminal 1034 ・ ・ ・ ・ ・ ・ Burst low level input terminal 1035, 1036 ・ Resistance element 1037 ・ ・ ・ ・ ・ ・ Inverter Circuit 1038 ... NOR circuit 1040 P-channel MOSFET Q1 1041 N-channel MOSFET Q2 1042 P-channel MOSFET Q3 1043 N channel MOSFET Q4 1044 P channel MOSFET Q5 1045 N channel MOSFET Q6 1230 Blanking signal input terminal 1231 Zero modulation signal input Terminal 1232 ··· Digital data input terminal after balanced modulation (most significant bit) 1233 ··· Digital data input terminal after balanced modulation (upper bit) 1234 ··· Digital data after balanced modulation Input terminal (middle-order bit) 1235 ··· Digital data after balanced modulation Input terminal (lower bit) 1236 ··· Digital data input terminal after balanced modulation (least significant bit) 1237 ··· Analog output high level input terminal 1238 ··· Analog output terminal 1239 ·・ ・ ・ ・ ・ Analog output low level input terminal 1241 ・ ・ ・ ・ ・ 5 input NAND circuit 1242 ・ ・ ・ ・ ・ 2 input NOR circuit 1243 ・ ・ ・ ・ ・ Inverter circuit 1244 ・ ・ ・ ・ ・ Resistance Element 1245 ··· P-channel MOSFET 1246 ··· N-channel MOSFET 1247 ··· 2-input NOR circuit 1431 ··· Analog Y data input terminal 1432 ··· -Analog RY data input terminal 1433 --- Analog BY data input terminal 1434 --- Analog verse Data input terminal 1435 ...... composite video signal output terminal 1436 ...... resistive element 1437 ...... capacitive element 1438 ...... npn-type bipolar transistor

[Procedure amendment]

[Submission date] October 19, 1995

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a block diagram showing a color image processing system constituting a video device.

2A and 2B are block diagrams showing a video signal processing device of the present invention.

FIG. 3 is a diagram showing a matrix ROM of the present invention.

FIG. 4 is a diagram showing a vector display result by the matrix ROM of FIG.

FIG. 5 is a diagram showing a first embodiment of a balanced modulation circuit of the present invention.

6A to 6C are waveform charts showing an operating state of the balanced modulation circuit of FIG.

7A to 7D are waveform charts showing the operating state of the video signal processing device having the balanced modulation circuit of FIG.

FIG. 8 is a diagram showing a second embodiment of the balanced modulation circuit of the present invention.

9A to 9F are waveform charts showing operating states of the balanced modulation circuit of FIG.

FIG. 10 is a diagram showing a color burst signal generation circuit of the present invention.

11A to 11C are diagrams showing an operating state of the color burst signal generation circuit of FIG.

FIG. 12 is a diagram showing a digital-analog converter of the present invention.

13 is a diagram showing an operation state of the digital-analog converter in FIG.

FIG. 14 is a diagram showing a synthesis circuit of the present invention.

[Explanation of Codes] 101 ... CPU 102 ... ROM 103 ... RAM 104 ... Video signal processing device (video color encoder) 105 ... ··· Video display controller 106 ··· Video RAM 107, 108 · · Interface 109 ··· TV receiver 221, 222 · · Data bus 224 ··· Address register 225 ··· ... Address selector 226 ... Color table RAM 227 ... Latch circuit 228, 229, 230 ... D / A converter 231 ... Matrix ROM 232 ... ... Control unit 233 ... Control signal generation circuit 23A ... Oscillation circuit 234 ... Synchronous signal composite circuit 235, 2 6, 237 ... D / A converter 238, 239 ... Balanced modulation circuit 240 ... Burst signal generation circuit 240A ... Digital color burst signal 241A ... Analog RGB signal output Circuit 241B ···: Synthesis circuit 242 ··· Burst D / A converter 251 ··· Sync signal input terminal 252 ··· Digital R color data input terminal 253 ··· ... Digital G color data input terminal 254 ... Digital B color data input terminal 255 ... Clock signal input terminal 258 ... Digital Y data 259 ... Digital RY data 260 ... Digital BY data 264 ... Analog Y data 265 .. Analog RY data 266.・ ・ ・ ・ Analog BY data 267 ・ ・ ・ ・ Analog burst data 269 ・ ・ Composite video signal output terminal 270 ・ ・ ・ ・ R-Y balanced modulation color difference signal carrier signal 271 ・... BY color balance modulation color difference signal carrier signal 272 ... Burst signal control signal 273 ... Burst generation subcarrier signal 302 ... Flip-flop 303・ ・ ・ ・ ・ Digital R color data input terminal 304 ・ ・ ・ ・ ・ Digital G color data input terminal 305 ・ ・ ・ ・ ・ ・ Digital B color data input terminal 306 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Dot clock input terminal 307 ・・ ・ ・ ・ ・ Digital Y data 308 ・ ・ ・ ・ ・ Digital RY data 309 ・ ・ ・ ・ Digital BY data 310 ・ ・ ・ ・ Semiconductor memory device Address input terminal 311 ..- Data output terminal of semiconductor memory device 530 ..- Data input terminal before modulation 531 ..- Modulation clock input terminal 532 ..- Data after modulation Output terminals 830, 831, 832, 833, 834 .. Pre-modulation data input terminals 835, 836, 837, 838, 839 .. Post-modulation data output terminals 840 ..... Modulation clock input terminals 841 .. ..Modulation zero signal input terminal 1030..burst signal control signal input terminal 1031 ........ sub-carrier signal input terminal for burst generation 1032 .... burst high level input terminal 1033 ..・ ・ ・ ・ Analog burst data output terminal 1034 ・ ・ ・ ・ ・ ・ Burst low level input terminal 1035, 1036 ・ Resistance element 1037 ・ ・··· Inverter circuit 1038 ··· NOR circuit 1040 ··· P channel MOSFET Q1 1041 ··· N channel MOSFET Q2 1042 ··· P channel MOSFET Q3 1043 · N-channel MOSFET Q4 1044 P-channel MOSFET Q5 1045 N-channel MOSFET Q6 1230 Blanking signal input terminal 1231 Modulation zero signal input terminal 1232 ・ ・ ・ ・ ・ ・ Balanced modulation digital data input terminal (most significant bit) 1233 ・ ・ ・ ・ ・ ・ Balanced modulation digital data input terminal (upper bit) 1234 ・ ・ ・ ・ ・ ・ Balanced After modulation digital data input terminal (middle bit) 1235 ··· After balanced modulation Digital data input terminal (lower bit) 1236 ··· Digital data input terminal after balanced modulation (least significant bit) 1237 ··· Analog output high level input terminal 1238 ··· Analog output terminal 1239 ... Analog output low level input terminal 1241 .. 5-input NAND circuit 1242 ..... 2-input NOR circuit 1243 ..... Inverter circuit 1244 .. -Resistance element 1245 ... P-channel MOSFET 1246 ...- N-channel MOSFET 1247 ... 2-input NOR circuit 1431 ... Analog Y data input terminal 1432 ... ... Analog RY data input terminal 1433 ... Analog BY data input terminal 1434 ... Na log burst data input terminal 1435 ...... composite video signal output terminal 1436 ...... resistive element 1437 ...... capacitive element 1438 ...... npn-type bipolar transistor

 ─────────────────────────────────────────────────── ─── Continuation of the front page (31) Priority claim number Japanese Patent Application Sho 62-230207 (32) Priority date Sho 62 (1987) September 14 (33) Priority claim country Japan (JP) (31) Priority Claim number Japanese patent application Sho 62-230205 (32) Priority date Sho 62 (1987) September 14 (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese patent application Sho 62-230202 (32) Priority Nissho 62 (1987) September 14 (33) Priority claiming country Japan (JP) (72) Inventor Akira Nakata 3-3-5 Yamato, Suwa City, Nagano Seiko Epson Corporation (72) Inventor Nakamura Atsushi Seiko Epson Co., Ltd. 3-3-5 Yamato, Suwa City, Nagano Prefecture

Claims (4)

[Claims] 1. A video signal processing device comprising a conversion means for converting a color difference signal represented by a digital value designating a color of each dot on a display screen into a color difference signal represented by an analog value, wherein the conversion means. Includes a color burst signal generation circuit, wherein the color burst signal generation circuit alternates between a maximum value and a minimum value of the color burst signal according to the frequency of the color burst signal subcarrier during the color burst signal generation period. A video signal processing device, which outputs the intermediate value between the maximum value and the minimum value of the color burst signal outside the period of generating the color burst signal. 2. The color burst signal generation circuit comprises: a first terminal for supplying a maximum value of the color burst signal; a second terminal for supplying a minimum value of the color burst signal; Two resistance means connected in series between two terminals, and each connected between the connection point of the first terminal, the second terminal and the resistance means and the output terminal of the color burst signal. The video signal processing apparatus according to claim 1, further comprising a switch means. 3. The conversion means further comprises a balanced modulation circuit that balance-modulates the two color difference signals represented by the digital value, and a first digital-analog conversion for the luminance signal represented by the digital value. And a second and a third digital-analog converter for the two color difference signals represented by the digital values output from the balanced modulation circuit, the second and the third digital-analog The converter outputs an intermediate value of analog output during a period other than the display period, and the output terminals of the first, second and third digital-analog converters and the color burst signal generation circuit are It is commonly connected to a bipolar transistor through a resistance means that determines an output level, and a composite video signal formed by combining the signals is output from the bipolar transistor. The video signal processing device according to claim 1, characterized by: 4. The video signal processing device according to claim 3, a video display controller for providing image data to the video signal processing device, a video data storage device for storing the image data, and an output from the video signal processing device. And an interface means for transmitting the composite video signal to the display device.