JPH08194648A - Storage device - Google Patents

Abstract

PURPOSE: To preferentially check the error of data not to be accessed from a processor. CONSTITUTION: This device is provided with a cell array 103 for storing execution time information in addition to a cell array 101 for storing data codes and a cell array 102 for storing ECC, a control part 105 executes the error check to the designated data code in response to read access from the processor, and the execution time information corresponding to executed data is updated into system time information. Further, a time information check part 106 retrieves the contents of execution time information in the cell array 103 in a designated period, data that the execution time information in matched with the system time information, namely, the data that the lapse of time from the last execution of the error check is the longest is extracted and the error check is executed to these data. Namely, the date not to be accessed from the processor are preferentially extracted by the memory scrambling operation of the time information check part 106 and the error checks of there data are executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device, and more particularly to a storage device suitable for use as a highly reliable memory having an error detection / correction function for data on the memory by using a parity bit or an error correction code. Regarding the device.

[0002]

2. Description of the Related Art In a processing device or the like having a processor and a storage device, data associated with access by the processor is stored in the storage device. However, the bits representing the data code stored in the memory may be inverted due to radiation or noise. Therefore,
A parity bit that represents even or odd number of “1” in the bit that represents the data code, or an ECC (Error Correctin) represented by a Hamming SEC / DED code.
g Code) to the data code,
A highly reliable storage device having an error detection / correction function of data stored in a memory has been proposed.

Error detection of data stored in memory /
The correction is performed by performing an error check (parity check / ECC check) on the data when the processor reads / writes the data from / to the memory. However, if bit inversion accumulates for data that the processor does not access for a long time, the data error detection / correction capability due to parity bits or ECC may be exceeded.

Therefore, in order to prevent accumulation of bit inversion,
For example, "David A. Rennel and
Hyeongil Kim, “VLSI Implim
entation of A Self-exerci
Sing Memory System ”, Proc. 2
1st Int. Symp. Fault-Tole
rant Computing (FTCS-21),
pp. 170-177 (1991) ”, a device for periodically performing error checking on all data stored in the memory is proposed in addition to the access to the memory by the processor. That is, in addition to the memory access from the processor, a memory scrubbing method is employed in which all data is sequentially and periodically subjected to a parity check for a RAM chip. When an error is found in the data by the parity check, the data codes of all the addresses of the line in which the error occurred are taken out one by one from the RAM chip and the ECC check is performed. If the error can be corrected, the data Corrections are being made. Note that, as a technique related to this type of technique, there are JP-A 1-112599 and JP-A 63-269233.

[0005]

However, in the above-mentioned conventional technique, all the data in the memory are periodically error-checked separately from the access to the memory by the processor. Although it can be suppressed to some extent, the memory scrubbing cycle becomes longer as the memory capacity increases due to the higher integration of the LSI. If the memory scrubbing cycle becomes long, bit reversal errors exceeding the error detection / correction capability may accumulate during that period, and the reliability of the memory deteriorates.

An object of the present invention is to provide a storage device capable of error checking by giving priority to data not accessed by a processor.

[0007]

To achieve the above object, the present invention provides a data storage means for storing a plurality of data and an error correction code for storing an error correction code for correcting an error of each data. A storage unit, an execution time information storage unit that stores, as execution time information, a history relating to the execution of an error check for each data, and a long elapsed time after executing the error check by searching the information in the execution time information storage unit. Extraction means for preferentially extracting the execution time information, and error check according to the error correction code for the data corresponding to the execution time information extracted by the extraction means and the data designated by the access from the processor The storage device comprises an error check executing means. Further, the present invention is intended to specify a data storage means for storing a plurality of data, an error correction code storage means for storing an error correction code for correcting an error of each data, and an execution time of an error check for each data. System time information generation means for generating system time information, execution time information storage means for storing execution time information indicating execution time of error check for each data in association with the system time information for each data, and execution time Retrieval means for sequentially retrieving each execution time information stored in the information storage means is compared with the execution time information retrieved by the retrieval means and the system time information generated by the system time information generating means to determine a match between them. The comparison determination means and the data and the process corresponding to the execution time information for which the determination result of the matching is obtained by the comparison determination means. It is for the specified data that constitute it have a storage device and a error check execution means for executing an error check in accordance with the error correction code by an access from.

In constructing the storage device, as the system time information generating means, one having a function of sequentially generating system time information for specifying the execution time of error correction for each data at a specified cycle is used. Alternatively, the search unit may be configured to have a function of sequentially searching each execution time information stored in the storage unit for the execution time information at a specified cycle. Further, the execution time information storage means may be configured to have a function of storing execution time information indicating execution time of error correction for each data in association with each data. In addition to the above-mentioned elements, the execution time information for updating the execution time information corresponding to the error-corrected data to the system time information generated by the system time information generating means on condition that the error correction executing means performs the execution. It can also be configured with an update means.

The following elements can be added in constructing each of the storage devices.

(1) Based on the execution result of the error check execution means, there is a check bit storage means for storing a check bit indicating whether or not an error check is executed in association with each execution time information, and the search means is a check bit. The check bit of the storage means retrieves only the execution time information indicating that the error check has not been executed.

(2) Based on the execution result of the error check execution means, there is a check bit storage means for storing a check bit indicating whether or not the error check is executed in association with each execution time information, and a search cycle designated by the search means. Reset means for resetting all the check bits of the check bit storage means to a bit indicating that error check has not been executed each time the search is completed, and the search means has a check bit of the check bit storage means indicating that error check has not been executed. Only the execution time information is retrieved.

(3) The error check execution means executes a process of transferring data designated by access to the processor as a process in parallel with the execution of the error check.

(4) Parity bit storage means for storing a parity bit for detecting an error in each data, and whether or not there is an error in the data designated by the access from the processor according to the parity bit of the parity bit storage means. The error check executing unit includes an error detecting unit that detects an error, and the error check executing unit executes an error check only on data for which an error is detected by the error detecting unit among the data accessed by the processor.

(5) Parity bit storage means for storing a parity bit for detecting an error in each data, and whether or not there is an error in the data designated by the access from the processor according to the parity bit of the parity bit storage means. The error check executing unit includes an error detecting unit for detecting, and the error check executing unit executes an error check on the data designated by the access from the processor in parallel with the error detecting process of the error detecting unit.

[0015]

According to the above-mentioned means, the data accessed from the processor is subjected to the error check. At this time, when the history related to error check execution is stored as execution time information, the content of this execution time information is searched,
The execution time information having a long elapsed time after the error check is executed is preferentially extracted, and the data corresponding to the extracted execution time information is error checked. That is, the data not accessed by the processor is preferentially error-checked. Therefore, even if the data capacity increases, the error check intervals for all the data are smoothed, and the accumulation of bit inversion errors can be suppressed.

Further, when the error check is executed for the data accessed from the processor and the execution time of the error check is stored in association with the system time information, the execution time information is sequentially searched and the searched execution is executed. The time information and the system time information are compared. At this time, when the contents of both match, it is determined that the data has passed the most time since the error check was performed last time, and the error check is performed on this data. That is, the data not accessed by the processor is preferentially checked for errors. Therefore, even if the memory capacity increases, the error check intervals for all data are smoothed, and it is possible to suppress the accumulation of bit inversion errors.

Further, since the data accessed from the processor is transferred to the processor as it is without waiting for the execution result of the error check, the overhead due to the error check can be made substantially zero.

Further, since the error check according to the error correction code is executed only on the data in which the error is detected by the error detection using the parity bit, a faster memory scrubbing operation can be realized.

Further, since the error detection process using the parity bit and the error check using the error correction code are executed in parallel, the error check is performed on the data in which the error due to the parity bit is detected. Since it becomes possible to make a correction, it is possible to prevent the processor from being stopped.

[0020]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an overall configuration diagram of a storage device according to the present invention. In FIG. 1, the memory device 10 is a cell array 10
1, 102, 103, an address decoder 104, a memory-ECC control unit 105, and a time information check unit 106, and the address decoder 104, the cell array 101, and the time information check unit 106 mutually pass through an address line 107. It is connected. Further, the address decoder 104 is connected to the memory-ECC control unit 105 via an address line 108. The memory-ECC control unit 105 is connected to the cell arrays 101 and 102 via a data line 109 and a control line 110, and a control line 114.
The time information check unit 106 is connected via.
The time information check unit 106 is connected to the cell array 103 via the data line 111 and the address line 113. In addition, the memory-ECC control unit 105 uses an external address /
It is connected to the processor via a data bus 115 and an external control bus 116.

The cell array 101 is configured as a data storage means for storing various data, and the cell array 10
Reference numeral 2 is configured as an error correction code storage means for storing an ECC (error correction code). The memory-ECC control unit 105 is configured as an error check execution unit, and writes data in the cell array 101 or reads data written in the cell array 101 in response to an access from the processor. Further, the time information check unit 1 performs an error check on the accessed data according to the error correction code.
The error check is executed according to the command from 06.

That is, as shown in FIG. 2, when the time information checking unit 106 starts the memory scrubbing operation and selects the check destination address (step 30).
01), the data code of the selected address is taken out from the cell array 101 and the error correction code is taken out from the cell array 102 (step 3002). Then, ECC control (error detection / error correction according to the error correction code) is performed on the fetched data code (step 3003). At this time, when the ECC control is successful, that is, when the error is not detected in the data code or when the error is detected but can be corrected, the process returns to step 3001 and the memory scrubbing operation is continued. In this case, the data code whose error has been corrected in accordance with the detection of the error is written in the cell array 101 in the corrected state. On the other hand, when ECC control fails, that is, EC
If an error is detected by the C check, but the error cannot be corrected, a memory fault occurs (step 3004).

The cell array 103, as shown in FIG.
The execution time information storage means for storing the 2-bit execution time information 1031 and the check bit storage means for storing the 1-bit check bit 1032 are configured. That is, the cell array 103 stores the history regarding the execution of the error check as the execution time information 1031 in association with the data. The time information check unit 106 that executes the memory scrubbing operation on the cell array 103 includes the system time information generation unit 10
61, a memory scrubbing control unit 1062, a comparison determination unit 1063, and an execution time information updating unit 1064. The system time information generation unit 1061 includes a memory scrubbing control unit 1062 and an execution time information update unit 106.
4 through the control lines 1065 and 1066, respectively, and the memory scrubbing control unit 1062 is connected to the comparison determination unit 1
063 and the control line 1068. Further, the system time information generation unit 1061 is the comparison determination unit 106.
3 and the data line 1067.

The system time information generating unit 1061 is composed of, for example, a counter, and constitutes a system time information generating unit for generating 2-bit system time information at a designated cycle in accordance with a command from the memory scrubbing control unit 1062. It has become. The memory scrubbing control unit 1062 uses the execution time information 1031 and the check bit 1
A search means for sequentially searching for 032 is configured. The comparison / determination unit 1063 constitutes a comparison / determination unit that compares the execution time information 1031 retrieved by the memory scrubbing control unit 1062 with the system time information and determines whether the two match. The execution time information updating unit 1064 is an execution time information updating unit that updates the execution time information corresponding to the error-checked data to the system time information, and the memory scrubbing control unit 1062.
Check bit 1 every time the search cycle specified by
A reset means for resetting all 032 to a bit indicating that error correction has not been executed is configured.

Next, the memory scrubbing operation using the error check execution time information will be described with reference to the flowchart of FIG.

First, in addition to the data accessed from the processor, the execution time information 1031 is sequentially accessed from the beginning of the address to the rear of the cell array 103 in accordance with the execution of the memory scrubbing controller 1062. At this time, it is determined whether the check bit 1032 of the data code to be checked is ON (data of "1"), that is, whether the check has been completed (step 400).
1). When the check bit 1032 is OFF (“0” data), that is, when the check is not completed, the execution time information 1031 and the system time information are compared and determined by the comparison determination unit 1
The determination is made at 063 (step 4002). At this time, when the contents of both match, this execution time information 1031
Is the execution time information corresponding to the data having the longest elapsed time from the execution of the error check, the error check is executed for the data corresponding to the execution time information, and the execution time information 1031 The check bit 1032 is changed from OFF to ON (step 4003), and the operation of selecting the check destination address ends.

On the other hand, when it is determined in step 4001 that the check bit is ON, or when the contents of the two do not match in step 4002, the memory scrubbing control unit 1062 sets the check target to the data code of the next address. Shift processing is performed (step 4004). In this case, when shifting, it is checked whether the final address on the memory is exceeded or not. If the final address is not exceeded, the data code of the shifted address is accessed, and the process returns to step 4001 to repeat the same operation ( Step 4005).

On the other hand, in step 4005, when the access by the memory scrubbing controller 1062 exceeds the final address, the system time information generator 106.
The system time information generated by 1 is updated (step 4006). For example, when the value of the system time information up to now is "10", it is updated to "11". After that, all bits of the check bit 1032 are reset to OFF according to a command from the execution time information updating unit 1064 (step 4007). Next, the data code at the start address of the memory is accessed as the check target (step 4
008), and returns to the process of step 4001. The value of the system time information to be updated is expressed by a periodic function, so that the data code whose execution time information is not changed is selected in a substantially constant period.

As described above, in this embodiment, when the error check is performed on the data accessed by the processor and the data extracted by the memory scrubbing operation, the execution time information 10 corresponding to each data is obtained.
31 is updated to the system time information. Moreover, since the system time information is updated at the specified cycle, the data for which the execution time information has been updated is stored as a history of error check execution until the system time information becomes the original time. It indicates the longest time information as the elapsed time. Therefore, even if the data is not frequently accessed from the memory, it is always selected if the execution time information matches the system time information, and the data that is frequently accessed by the processor has new execution time information. Depending on the scrubbing control, there will be less extraction.

Therefore, according to the present embodiment, since the data not accessed by the processor is prioritized for error checking, the error checking intervals for all the data can be smoothed even if the memory capacity increases. Therefore, the accumulation of bit inversion errors can be suppressed, and the reliability of the storage device can be improved.

In the above embodiment, the memory-EC
By providing a plurality of ECC control units in the C control unit 105, it is possible to further shorten the interval for performing error checking of each data code.

Next, the operation for executing the data transfer process associated with the read access as a process in parallel with the error check will be described with reference to the flowchart of FIG.

First, when the processor issues a read access command, a specified address is output from the address decoder 104, and a data code specified by the address is extracted from the cell arrays 101 and 102 (steps 3101 and 3102). Then, the fetched data code is sent from the memory-ECC control unit 105 to the processor via the external address / data bus 115 (step 3103). At this time, in parallel with the processing of step 3103, the memory-ECC control unit 105 executes ECC control for the data code sent to the processor (step 3003). At this time, if there is no error in the data code, information indicating that there is no error in the data code is sent to the processor, and the read access operation ends. In the process of step 3003, when there is an error in the data code, the data code sent to the processor is incorrect, so the processor is stopped (step 3104).

On the other hand, the time information checking unit 106 that has received the designated address in the processing of step 3101, in parallel with the processing of step 3102, stores the execution time information of the data code of the designated address in the cell array 102.
Update information. That is, the execution time information 1031 is updated with the system time information. Further check bit 103
Set 2 to ON. With the above processing, the processing in this routine ends.

Regarding the write access to the storage device 10 by the processor, the memory-ECC control unit 10
By providing the buffer in 5, the write access overhead by ECC control can be made zero. After addressing for write access, in parallel with the normal write operation, the process of step 3105, that is, in the cell array 103 for storing the execution time information of the data code of the designated address is performed in the same manner as the read access. Update information.

According to this embodiment, when the processor makes a read access to the storage device 10, the storage device 1
Since the data taken out from 0 is sent directly to the processor without waiting for the check result of the error check, the error check overhead can be made substantially zero.

Further, according to this embodiment, the memory-EC
The C control unit 105 and the time information checking unit 106 can prevent the read / write access speed from decreasing by prioritizing the read / write access from the processor to the storage device 10 over the memory scrubbing control.

Next, another embodiment of the present invention will be described with reference to FIG.

The storage device 10A of the present embodiment is provided with a cell array 121 for storing parity bits and a memory-ECC / parity control unit 105A instead of the control unit 105. Since it is the same as that of No. 1, the same parts are denoted by the same reference numerals and the description thereof will be omitted.

The cell array 121 constitutes a parity bit storing means for storing a parity bit, and the control section 105A constitutes an error check executing means and an error detecting means for detecting the presence or absence of an error according to the parity bit. Is configured.

Next, the memory scrubbing operation when the parity bit is added to the data code will be described with reference to the flowchart of FIG.

First, when a check destination address is selected by a command from the time information check unit 106 (step 3001), the selected address is the address decoder 1.
04 to the cell arrays 101, 102 and 121. Then, the data code specified by the address is taken out from each cell array 101, 102, 121 (step 3002A). When the data code is taken out by the control unit 105A, parity control (error detection by parity check) for the data code is executed (step 30021). At this time, when the parity control is successful, that is, when no error is detected in the data code,
Returning to step 3001, the memory scrubbing operation is continued. On the other hand, if the parity control fails, that is, if an error is detected by the parity check, the control unit 1
With 05A, ECC control for data code (error detection by error check according to error correction code /
Error correction) is executed (step 3003). At this time, the ECC control is successful, and if an error is detected in this case and the error can be corrected, the corrected data code is written back to the memory, and the process returns to step 3001 to continue the memory scrubbing operation. On the other hand, when the ECC control is unsuccessful, that is, when the error cannot be corrected by the ECC check, the process in this routine is ended as a memory fault (step 3004).

In the memory scrubbing operation of the present embodiment, when data error checking is performed, first parity control is performed, and error correction is performed only on data in which an error is found by parity control by ECC control. Therefore, while there is no error in the data code, the memory scrubbing operation proceeds only by the parity control. In general, parity control can be executed in a shorter time than ECC control. For this reason,
As compared with the memory scrubbing operation shown in FIG. 2, a faster memory scrubbing operation can be realized.

Therefore, according to the present embodiment, it is possible to further shorten the interval for performing the error check of each data code, and it is possible to accumulate bit inversion errors in the data code that exceed the error detection / error correction capability. Therefore, the reliability can be further reduced, and the reliability of the storage device 10A can be further enhanced.

Next, the operation when the parity control and the ECC control are executed in parallel with the read access of the processor will be described with reference to the flowchart of FIG.

First, when a read access is started from the processor to the memory device 10A, the designated address is transferred to the cell arrays 101, 102, 121 and the time information check unit 106, and the address is designated (step 3101). . When the address is specified, the cell array 10
The specified data code is extracted from 1, 102, 121 (step 3102A). When the data code is extracted, the control unit 105A executes parity control (error detection by parity check) on the extracted data code (step 30321). At this time, when the parity control is successful, that is, when no error is detected in the data code, this data code is sent to the processor via the external address / data bus 115, and the read access operation is completed. On the other hand, when the parity control is unsuccessful, that is, when an error is detected by the parity check, this data code is not output to the outside, and the control result of the ECC control in step 3003 is waited (step 3106).

In parallel with the parity control in step 30021, the control section 105A executes ECC control for the fetched data code (step 3003).
In this ECC control, when no error is detected in the retrieved data code, the read access operation is completed successfully. On the other hand, when an error is detected in the data code, but the error can be corrected, the ECC control end wait in step 3106 is released, the corrected data code is sent to the processor in step 3003, and the read access operation is completed. To do. The EC of step 3003
When the C control fails, that is, an error is detected and the error cannot be corrected, the processor is stopped (step 3104).

On the other hand, in parallel with the processing of step 3102A, the time information check unit 1 which receives the designated address
06 updates the execution time information of the cell array 103, which stores the execution time information regarding the data code of the specified address, to the system time information. Check bit 10
Set 32 to ON. This completes the processing in this routine.

The read access operation of the memory device 10A in this embodiment is slower than the read access operation shown in FIG. 5 because of the parity control. However, since the parity control can be executed in a shorter time than the ECC control, the read access time can be shortened as compared with the conventional one. Further, in the read access operation shown in FIG. 5, if there is an error in the data code, the processor is stopped, but in the read access operation in this embodiment, even if there is an error in the parity bit, the ECC is executed. Since the corrected data can be sent to the processor after waiting for the control result, the ECC
Regarding error data that can be corrected by control, the processor can be operated in the same read access time as the conventional system without stopping.

In the memory device 10A shown in FIG. 6, the memory scrubbing operation and the access operation to the memory device 10A such as a processor are performed in addition to the processes described in the flowcharts of FIGS. 7 and 8. It is also possible to realize the processing by combining the above and the processing by combining the processing of FIG. 7 and FIG.

In the above-mentioned embodiment, the temporary storage device is mainly described as the storage device, but not only the temporary storage device but also the n-th order storage device (n is an integer of 1 or more) such as CACHE memory and disk device. Is also applicable.

[0053]

As described above, according to the present invention, data corresponding to execution time information having a long elapsed time after execution of error check is added to each data by adding execution time information indicating a history of execution of error check. Even if the memory capacity increases, the error check interval for all data can be smoothed and the accumulation of bit inversion errors can be suppressed because the error check is executed with priority on the code. , Can contribute to the improvement of reliability.

Further, according to the present invention, in response to the read access from the processor, the data designated by the read access is directly transferred to the processor without waiting for the check result of the error check. Can be made substantially zero, and a reduction in read access speed can be prevented.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram showing an embodiment of a storage device according to the present invention.

FIG. 2 is a flowchart illustrating a memory scrubbing operation of a storage device.

FIG. 3 is a specific configuration diagram of a cell array and a time information check unit.

FIG. 4 is a flowchart illustrating a method of selecting a check destination address.

FIG. 5 is a flowchart illustrating a read access to a memory of a processor.

FIG. 6 is an overall configuration diagram of a storage device showing another embodiment of the present invention.

7 is a flowchart for explaining a memory scrubbing operation of the storage device shown in FIG.

8 is a flow chart for explaining a read access operation of a processor for the storage device shown in FIG.

[Explanation of symbols]

 10, 10A storage device 101, 102, 103, 121 cell array 104 address decoder 105 memory-ECC control unit 105A memory-ECC / parity control unit 106 time information check unit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Michi Sato 7-1-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory (72) Inventor Shinya Otsuji 7-chome, Omika-cho, Hitachi-shi, Ibaraki No. 1 in Hitachi, Ltd. Hitachi Research Laboratory

Claims (9)

[Claims] 1. A data storage means for storing a plurality of data, an error correction code storage means for storing an error correction code for correcting an error in each data, and a history of execution of an error check for each data and an execution time. The execution time information storage means stores each data as information, the extraction means for searching the information in the execution time information storage means and preferentially extracting the execution time information having a long elapsed time after the error check is executed, and the extraction means of the extraction means. A storage device comprising: error check execution means for executing an error check according to the error correction code on data corresponding to execution time information by extraction and data designated by access from a processor. 2. A data storage means for storing a plurality of data, an error correction code storage means for storing an error correction code for correcting an error of each data, and an execution time of an error check for each data. System time information generation means for generating system time information, execution time information storage means for storing execution time information indicating execution time of error check for each data in association with the system time information for each data, and execution time Retrieval means for sequentially retrieving each execution time information stored in the information storage means is compared with the execution time information retrieved by the retrieval means and the system time information generated by the system time information generating means to determine a match between them. Comparison determination means, data and processor corresponding to execution time information for which a determination result of coincidence is obtained by the comparison determination means A storage device including error check execution means for executing an error check according to the error correction code on data designated by access from the storage device. 3. A data storage means for storing a plurality of data, an error correction code storage means for storing an error correction code for correcting an error in each data, and an execution time of an error check for each data. System time information generating means for sequentially generating the system time information of a specified cycle, and execution time information storage for storing the execution time information indicating the execution time of the error check for each data in association with the system time information for each data. Means, a retrieval means for sequentially retrieving each execution time information stored in the execution time information storage means at a designated cycle, execution time information by the retrieval of the search means and system time information generated by the system time information generation means. Comparison determining means for comparing and comparing the two and execution time information for which a determination result of matching is obtained by the comparison determining means A storage device comprising: an error check executing means for executing an error check according to the error correction code on the data corresponding to the above and the data specified by the access from the processor. 4. A data storage means for storing a plurality of data, an error correction code storage means for storing an error correction code for correcting an error of each data, and an execution time of an error check for each data. System time information generating means for sequentially generating system time information of a specified cycle, execution time information storage means for storing execution time information indicating execution time of error check for each data in association with each data, and execution time Retrieval means for sequentially retrieving each execution time information stored in the information storage means at a specified cycle, and the execution time information retrieved by the retrieval means and the system time information produced by the system time information producing means are compared to compare the two. The comparison and determination means for determining the match, and the data and the process corresponding to the execution time information for which the determination result of the match is obtained The error check execution means executes an error check according to the error correction code on the data specified by the access from the server, and corresponds to the data for which the error check has been executed on condition that the error check execution means executes the error check. And a execution time information updating means for updating the execution time information to the system time information generated by the system time information generating means. 5. A check bit storage means for storing a check bit indicating whether or not an error check is executed based on the execution result of the error check execution means in association with each execution time information, and the search means stores the check bit storage. 5. The storage device according to claim 2, wherein the check bit of the means retrieves only execution time information indicating that the error check has not been executed. 6. A check bit storage means for storing a check bit indicating whether or not an error check is executed based on the execution result of the error check execution means in association with each execution time information, and a search cycle designated by the search means ends. And a reset means for resetting all the check bits of the check bit storage means to a bit indicating that the error check has not been executed, and the search means executes the check bit of the check bit storage means indicating that the error check has not been executed. The storage device according to claim 3, wherein only the time information is retrieved. 7. The error check execution means executes a process of transferring data designated by an access to a processor as a process in parallel with the execution of the error check, according to claim 1, 2, 3, 4, 5 or 6. Storage device. 8. A parity bit storage means for storing a parity bit for detecting an error in each data, and the presence / absence of an error is detected in accordance with the parity bit of the parity bit storage means for the data designated by the access from the processor. 3. The error check executing means for performing error check, wherein the error check executing means executes error check only on the data accessed by the processor for which an error is detected.
The storage device according to 3, 4, 5 or 6. 9. A parity bit storage means for storing a parity bit for detecting an error in each data, and the presence / absence of an error is detected in accordance with the parity bit of the parity bit storage means for the data designated by the access from the processor. An error check means for performing error check on data designated by access from a processor in parallel with the error detection processing of the error detection means.
The storage device according to 4, 5, or 6.