JPH08194485A - Musical tone synthesizing device - Google Patents

Abstract

PURPOSE: To provide a musical tone synthesizing device which can make pitch control smoothly without generation of turbulence in the damping time over the whole sound ranges. CONSTITUTION: When judgement is such that the key code KC for a key pushed lies on the side nearer the treble region than the key zone dividing point BP, a CPU instructs a DSP so that a pitch control is conducted in accordance with the total delay amount of a delay circuit 2 and all-pass filters 4-1, 4-2. When judgement is such that the key code lies on the bass region side, on the other hand instruction is given so that the pitch control is conducted in compliance with the total delay amount of the delay circuit 2 and an interpolating apparatus 21. Thereby the pitch control can be performed smoothly without generating turbulence in the damping time over the whole sound ranges.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a musical sound synthesizing apparatus for synthesizing a decaying sound such as a percussion instrument sound.

[0002]

2. Description of the Related Art In recent years, various musical tone synthesizers have been developed which operate a model simulating the sounding mechanism of a natural musical instrument to synthesize a musical tone of a natural musical instrument. Among the musical tone synthesizers of this type, a configuration in which an adder 1, a delay circuit 2 and a filter 3 are connected in a closed loop as shown in FIG. . Note that such a configuration is called a "delayed feedback system".

In this figure, the delay circuit 2 is composed of a shift register, and the shift register is
It has flip-flops of the number of stages corresponding to the number of bits of the digital signal supplied from the adder 1. A clock is supplied to each flip-flop every sampling period τs. That is, the delay time τp by the delay circuit 2 corresponds to the time Nτs obtained by multiplying the sampling period τs by the number N of shift register stages. The filter 3 imparts a desired attenuation characteristic to the signal circulating in the closed loop.

In such a musical sound synthesizer, for example, an analog signal containing many frequency components such as a noise signal is PCM-coded for each sampling period τs, and the resulting time-series digital signal is input signal. And
This input signal is input to the adder 1 and then input to the delay circuit 2
Is supplied to the filter 3 via the, and is fed back to the adder 1 to circulate in the closed loop.

Now, ignoring the phase delay of the filter 3,
The time required for the input signal to make one round in the closed loop is equal to the delay time τp. In this case, the gain frequency characteristic of the closed loop has a maximum point at a frequency that is an integral multiple of the fundamental frequency f ₁ = 1 / τp. Since the closed loop gain is set to a value slightly smaller than "1",
The signal circulating in the loop is gradually attenuated. And
The output of the adder 1 is extracted during this attenuation process, and this is output to D / A
If converted, it becomes an attenuated signal containing the fundamental wave and harmonics having an integral multiple frequency. In other words, according to the above configuration, like the musical tone generated during actual string striking, a musical tone signal in which the fundamental wave and its harmonics are excited and whose amplitude gradually attenuates over time. That is why.

By the way, in the device having the configuration shown in FIG. 9, the delay time τp can be set only to an integral multiple of the above-described sampling period τs. Therefore, when the delay time τp needs to be a value deviating from an integral multiple of the sampling period τs, as shown in FIG.
An all-pass filter 4 is inserted between the filter 3 and the filter 3. The all-pass filter 4 shown in this figure is a first-order digital filter and includes adders 41 and 42 and a multiplier 4
3, 44 and a delay circuit 45. The delay circuit 45 has the same configuration as the delay circuit 2 described above, and is supplied with a clock every sampling period τs.

In this all-pass filter 4, the adder 4
The signal of the multiplier 44 is added to the output signal of the delay circuit 2 by 1. The output of the adder 41 is input to the adder 42 via the delay circuit 45, is multiplied by the multiplication coefficient −α by the multiplier 43, and is input to the adder 42. The output of the delay circuit 45 is multiplied by the multiplication coefficient α by the multiplier 44 and input to the adder 41. Then, the adder 42 adds the output of the delay circuit 45 and the output of the multiplier 43, and supplies the result to the filter 3. As the multiplication coefficients “α” and “−α” of the multipliers 43 and 44 described above, values between −1 and 1 are used.

The all-pass filter 4 having the above structure is
It is expressed by the transfer function H (z) shown in the following equation (1). That is, H (z) = α + z ^-1 + 1 + αz ^-1 (1) Here, when the frequency characteristic F (ω) of the all-pass filter 4 expressed by the above formula (1) is obtained, as is well known,
By replacing “z” in the expression (1) with exp (−jωτs), it is expressed by the following expression (2). F (ω) = α + exp (-jωτs) / 1 + α · exp (-jωτs) (2)

Next, since the gain frequency characteristic G (ω) of the all-pass filter 4 is equal to the absolute value of the above equation (2), G (ω) = | F (ω) | = 1. This allows
The gain of the all-pass filter 4 is "1" at all frequencies, which is the reason why it is called "all-pass". The phase delay P (ω) of the filter 4 has an angular frequency ω of Nyquist angular frequency ω _n = 2πfs / 2 (f
s: Sampling frequency), and when the phase angle ωτs is close to “0”, it is expressed by the approximate expression of the following expression (3). That is, P (ω) ≈ (1-α) ωτs / (1 + α) (3)

The equivalent delay time τa of the all-pass filter 4 is expressed by the following equation (4). τa = P (ω) / ω (4) Therefore, when an approximate delay time τa is obtained from the equation (4) and the equation (3), τa≈ (1-α) τs /
It becomes (1 + α). That is, the all-pass filter 4
Can adjust its own delay time τa by appropriately setting the above-mentioned multiplication coefficient α.
However, when τa changes almost linearly with respect to α, the change range of τa that can be considered is limited, and at most 0 ≦ τa
≦ 2τs. After all, in the closed loop including the components 1 to 4 shown in FIG. 10, the total delay time τ = τp + τa
, The resonance frequency of the closed loop changes, and the pitch of the attenuated sound circulating in the closed loop is controlled.

[0011]

In the conventional tone synthesizer described above, the pitch can be controlled by changing the multiplication coefficient α of the all-pass filter 4 to change the delay amount in the closed loop. On the other hand, when the multiplication coefficient α of the all-pass filter 4 is changed significantly, the delay characteristic of the entire closed loop also changes greatly, and an unharmonious musical sound containing more harmonics than necessary is synthesized,
As a result, there is a possibility that the instrument will no longer be preferable.

That is, as the limit for controlling the multiplication coefficient α of the all-pass filter 4 to change the delay amount, only the range of about 0 to 2 delay stages can be controlled with good linearity. Further, complicated processing is required to control the number of stages of the delay circuit 2 and the coefficient α of the all-pass filter 4 so that the output of the all-pass filter is not discontinuous. When the delay amount is changed by controlling the multiplication coefficient α of the all-pass filter 4, it is possible to obtain a moderate amount of change in the pitch in the high range, but in the low range, there is almost no change in the pitch with the single-stage all-pass filter 4. Can't get In the mode in which the delay time τp is controlled by performing weighted interpolation on the number of delay stages of the delay circuit 2, pitch control can be performed in a wide range, but the configuration for interpolating the number of stages itself forms a low-pass filter. Then, there is also a disadvantage that the decay time is not constant.

After all, the conventional tone synthesizer having the all-pass filter 4 has a problem that the pitch cannot be smoothly controlled without causing disturbance in the decay time in the entire tone range. Therefore, the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a musical tone synthesizer capable of smoothly controlling the pitch without causing disturbance in the decay time in the entire musical range.

[0014]

In order to achieve the above object, in the invention described in claim 1, a delay means for delaying an input signal by an integer number of stages in accordance with a sampling cycle, and outputting the delay signal are provided. An all-pass filter that delays and outputs a small number of stages, and a musical sound synthesizer that forms a delayed feedback loop using the output of the all-pass filter as the input signal is inserted in the loop and interpolates the output of the delay unit. Set the interpolation means and the range dividing point that divides the sound range into the high range and the low range, and determine whether the pitch to be pronounced is the high range side or the low range side with this range division point as the boundary. Determination means for determining, and a first pitch control means for performing pitch control according to the total delay amount of the delay means and the all-pass filter when the determination means determines the high frequency side,
When the determination unit determines that the low frequency side, the second pitch control unit for controlling the pitch according to the total delay amount of the delay unit and the interpolation unit.

According to the second aspect of the invention, a delay means for delaying the input signal by an integer number of stages and outputting it, and a plurality of delay units cascade-connected to the delay means for outputting the output of the delaying means with a decimal stage delay. Corresponding to the specified pitch, the closed-loop means having the all-pass filter as the input signal, the excitation signal generating means for supplying the excitation signal to the closed-loop means in response to a performance operation, A fractional stage delay amount of the delay amount D to be distributed to the plurality of all-pass filters, and each of the plurality of all-pass filters and the integer stage delay of the delay unit so that the total delay amount of the closed loop means becomes the delay amount D. And a pitch control means for controlling the coefficient.

[0016]

According to the present invention, when the pitch to be sounded is higher than the range dividing point, the pitch control is performed according to the total delay amount of the delay means and the all-pass filter, while the low range side is controlled. In the case of, the pitch control is performed according to the total delay amount of the delay means and the interpolation means. As a result, it becomes possible to perform pitch control smoothly without disturbing the decay time in the entire tone range.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. A. Overall Configuration FIG. 1 is a block diagram showing the overall configuration of an embodiment according to the present invention. In this figure, 10 is a CPU that controls each part of the apparatus, and its operation will be described later. 11
Is a ROM in which various control programs read by the CPU 10, various microprograms used in the DSP 15 described later, and tone color data are stored. A RAM 12 is used as a work area of the CPU 10 and temporarily stores various register values and calculation results.

Reference numeral 13 denotes an operation section on which various panel switches or auxiliary operators are arranged. The operation unit 13 has, for example, a switch for designating an all-pass filter coefficient c or a low-pass filter coefficient, which will be described later, a setting switch such as a switch for designating a tone color, and continuously variably controlling the pitch of a generated tone. An auxiliary operator such as a pitch bender is provided. The operation unit 13 generates operation information according to the operation of the setting switch or the auxiliary operator and supplies the operation information to the CPU 10 via the system bus. Reference numeral 14 denotes a performance operator that generates performance information such as key-on / key-off, key code KC or touch in response to a performance operation.

Reference numeral 15 is a digital signal processor (hereinafter abbreviated as DSP) which functions as a musical tone synthesizer,
It is composed of the components 15a to 15f. Reference numeral 15a is a microprogram RAM, which is RA by the CPU 10.
The microprogram read from M12 is stored. 15b is a first parameter data RAM, C
The tone parameter such as tone color data read from the ROM 11 is stored by the PU 10. Reference numeral 15c is a second parameter data RAM in which parameters, such as all-pass coefficients α and γ and an interpolation coefficient β, which will be described later, are written by the CPU 10 and which change with time during tone synthesis. The meanings of these coefficients α, γ and β will be described later.

A data interpolating unit 15d interpolates and outputs the all-pass coefficients α and γ read from the second parameter data RAM 15c so as not to change abruptly. Reference numeral 15e is an arithmetic processing unit. This arithmetic processing unit 15e
On the basis of the microprogram read from the microprogram 15a, performs arithmetic processing for musical tone synthesis by the "delayed feedback method" according to the first and second parameters described above, and generates a musical tone output WD. 1
Reference numeral 5f is a data register for temporarily storing the calculation processing result and the like performed in the calculation processing unit 15e. 16 is the DS
P15 is a delay RAM that gives a delay time required for the tone synthesis processing executed by P15. 17 is a D / A converter, DS
The tone output WD supplied from P15 is converted into an analog signal, and this is output as a tone signal W from the speaker SP.

Next, FIG. 2 is a block diagram showing a musical tone synthesis model realized by the arithmetic processing of the DSP 15 described above. The same parts as those of the conventional example shown in FIG. The description is omitted. The configuration shown in this figure is different from the conventional example in that an all-pass filter 4-1 for generating a fractional delay corresponding to a sounding pitch at the time of key-on.
And an all-pass filter 4-2 that generates a fractional-stage delay corresponding to the pitch bend operation, and an interpolator 21 that smoothes an integer-stage delay is provided in front of the all-pass filter 4-1 and further a coefficient multiplier. 21 is the adder 1
Is provided between the low pass filter 3 and the low pass filter 3 to control the closed loop gain.

The integer stage delay referred to here is a delay corresponding to the sampling clock φs, and corresponds to the number of stages of the shift register. On the other hand, the fractional stage delay is a delay amount smaller than the sampling clock φs and represents a delay of one shift register or less. In the following description, the integer stage delay is “Di” and the decimal stage delay is “Df”.
It is written as.

In FIG. 2, the excitation waveform generator 20 generates a noise signal in response to the key-on signal KON to excite the closed loop. The signal φs input to the generator 20 is the system clock. The delay circuit 2 sets N stages of integer stage delay Di corresponding to the delay control signal N.
The interpolator 21 includes a delay register 21a and a coefficient multiplier 21.
b and 21c and an adder 21d, the coefficients β and (1-β) given to the coefficient multipliers 21b and 21c.
The delay change in the previous stage is smoothed according to the value of. The all-pass filter 4-1 gives a decimal step delay according to the all-pass coefficient α given corresponding to the sounding pitch at the time of key-on.

The all-pass filter 4-2 has APF ₁ to.
APFs ₁₀ are connected in cascade and each APF is designed to generate a fractional delay corresponding to the pitch bend operation amount.
_The all-pass coefficient γ is given to _{1 to} APF ₁₀ . The low-pass filter 3 is composed of, for example, an FIR type digital filter, and performs low-pass filtering at a cutoff frequency corresponding to the supplied filter coefficient LC while keeping the delay time at a constant value D. The coefficient multiplier 22 adjusts the closed loop gain according to the control signal G.

In the above structure, the noise signal output from the excitation waveform generator 20 is delayed by an integer number of stages by the delay circuit 2 and then delayed by a small number of stages by the interpolator 21, and then the all-pass filter 4-1. , 4-2 are sequentially delayed by a fractional stage. The signal thus delayed by the integer stage / fractional stage is subjected to tone color adjustment through the low-pass filter 3, the loop gain is adjusted by the coefficient multiplier 21, and then delayed through the adder 1 again. In such a closed loop, when a signal circulates, a decaying sound having a pitch corresponding to the delay amount of the entire loop is synthesized.

That is, the pitch of the tone signal circulating in the closed loop is calculated by the delay time of the delay circuit 2 and the delay time of the interpolator.
It is the reciprocal of the sum of the delay times of the all-pass filters 4-1 and 4-2 and the delay time of the low-pass filter 3. Although such a basic operation is the same as the above-mentioned conventional example, a point peculiar to the present application is that pitch control is performed for each sounding range, as described later.

B. Schematic operation of the embodiment Next, the schematic operation of the embodiment having the above configuration will be described with reference to FIG. First, when the power is turned on in this embodiment, the CPU 10 reads the control program from the ROM 11 and activates the main routine shown in FIG. When the main routine is activated, the processing of the CPU 10 proceeds to step Sa1. In step Sa1, various registers are reset to initial values and the DSP 15 is instructed to load a predetermined microprogram. In step Sa1, the coefficients α, β and γ described above are each reset to zero.

When the initialization is performed in step Sa1, the processing of the CPU 10 proceeds to step S1.
Go to a2. In step Sa2, in order to detect the operation states of the operation unit 13 and the performance operator 14, each key or setting switch is scanned and a flag corresponding to each setting state is set in the register. Then, step Sa3
When the process advances to step 1, a tone color selection setting process called a voice process is performed. In this voice processing, the tone color data corresponding to the setting state of the tone color switch detected in step Sa2 is read from the ROM 11 and stored in a predetermined area of the first parameter data RAM 15b or R
The initial values of the all-pass coefficients α and γ and the interpolation coefficient β read from the OM 11 are stored in the second parameter data RAM 15c. As a result, the preparation for tone synthesis is completed on the DSP 15 side.

Next, in step Sa4, when a key-on event occurs, the generation of a musical tone corresponding to the key code KC generated in response to a performance operation is instructed. Details of this key-on processing will be described later. Next, when proceeding to the next step Sa5, based on a key-off routine described later, when a key-off event occurs, a key-off parameter for attenuating the musical tone produced at the time of key-on at a predetermined rate is generated, and the process proceeds to the next step Sa6.
In step Sa6, the operation amount m of the pitch bend wheel m
Pitch bend processing for continuously variably controlling the sounding pitch in accordance with the above, and subsequently, in step Sa7, processing for adding sound effects such as reverb and delay is performed. After that, the processing of the CPU 10 is performed again in step Sa.
Returning to step 2, the above operation is repeated.

C. Operation of Various Routines Here, the operation of various routines called in the main routine and the operation of the DSP 15 that synthesizes the attenuated sound under the instruction of the CPU 10 will be sequentially described. Operation of key-on processing routine When the processing of the CPU 10 proceeds to step Sa4 described above,
The routine shown in FIG. 4 is started, and the process proceeds to step Sb1. First, in step Sb1, it is determined whether a key-on event has occurred. Here, when the key-on event has not occurred, the determination result is “NO”,
Return to the main routine. On the other hand, when the player performs a key depression operation and a key-on event occurs as a result, the determination result is "YES", and the next step Sb2
Proceed to.

In step Sb2, the key code KC of the depressed key is converted into the note frequency F, and the following step Sb
The process proceeds to b3. When the process proceeds to step Sb3, the CPU
Reference numeral 10 calculates the delay time Ds of the entire closed loop from the relationship of fs / F (fs: sampling frequency, F: frequency number). Then, the integer part of the delay time Ds becomes the above-mentioned integer stage delay Di, and the decimal part becomes the decimal stage delay Df. Then, when the process proceeds to step Sb4, APF _{1 to} AP
The initial delay amount of the all-pass filter 4-2 formed from F ₁₀ is subtracted from the integer stage delay Di to calculate the delay stage number N. As a result, the number of delay stages of the delay circuit 2 is determined.

Then, in step Sb5, the all-pass coefficient α of the all-pass filter 4-1 corresponding to the fractional delay Df is calculated based on the following equation (5). α = (1−Df) / (1 + Df) (5) After that, the CPU 10 advances the processing to step Sb6, and sets the tone parameter such as the delay stage number N, the all-pass coefficient α, and the key-on signal KON obtained as described above. It is sent to the DSP 15 side. The number of delay stages N and the all-pass coefficient α
Musical tone parameters that change over time such as are stored in the second parameter data RAM 15c (see FIG. 1). As a result, the DSP 15 is given the parameters necessary for the tone generation, and the tone is generated according to the tone synthesis operation described later.

Operation of Key-Off Processing Routine When the processing of the CPU 10 proceeds to step Sa5 described above,
The routine shown in FIG. 5 is started, and the process proceeds to step Sc1. In step Sc1, it is determined whether a key-off event has occurred. Here, if it is not the key-off event, the determination result is "NO", and this routine is completed and returns to the main routine. On the other hand, if the generated event is a key-off event, the determination result here is "YES", and the process proceeds to the next step Sc2. When proceeding to step Sd2, the CPU 10 generates various key-off parameters for dumping the envelope generator at a predetermined rate, and sends them to the DSP 15 side. As a result, the DSP 15, which is the sound source, attenuates the musical sound being produced at a predetermined rate and then silences it.

Operation of Pitch Bend Processing Routine Next, it is assumed that the pitch bender is operated while a musical tone is being produced at a pitch corresponding to the key code KC of the depressed key. Then, the pitch bend processing routine shown in FIG. 6 is activated and step Sd1 is executed. The pitch bender is an auxiliary operator that smoothly changes the pitch of the generated musical sound. First, in step Sd1, it is determined whether or not the operation amount m applied to the pitch bender wheel as a performance operation is the same as the previous operation, that is, whether or not the operation has been performed. Here, the operation amount m
When there is no change, it is considered that the operation has not been performed and the determination result is “YES”, the routine is completed, and the process returns to the main routine (see FIG. 3) described above.

On the other hand, when the manipulated variable m changes,
The determination result is “NO”, and the process proceeds to the next Step Sd2. In step Sd2, the detected operation amount m (-1 to 1
Value) and the note frequency F described above, F '= F.e
A new note frequency F ′ is calculated based on the relational expression represented by xp (s · m). Note that s in the above equation is a pitch bender sensitivity parameter.

Next, when the process proceeds to step Sd3, the delay amount Ds of the entire closed loop corresponding to the new note frequency F'obtained in this way is obtained, and the delay amount Ds is obtained in the same manner as step Sb3 described above. An integer part delay Di and a decimal part delay Df of Ds are obtained. Subsequently, in step Sd4, the initial delay amount of the all-pass filter 4-2, that is, APF _{1 to} AP, is calculated from the obtained integer delay Di.
By subtracting "10" stage partial as the total delay amount of F _10, and stores in the register the value as a delay stage number N of the delay circuit 2.

Next, in step Sd5, the CPU 1
0 determines whether or not the key code KC of the depressed key has a lower pitch relationship than the preset key range dividing key BP. Here, if the pitch relation is lower than the key range dividing key BP, the determination result is “YES”, the flow proceeds to step Sd6, and the fraction delay Df obtained in step Sd3.
Is the interpolation coefficient β. Then, when the operation proceeds to the next step Sd7, the delay stage number N and the interpolation coefficient β in this case are set to the DSP1.
Send to the 5 side. As a result, pitch control corresponding to the pitch bender operation amount m when a key having a lower pitch relationship than the key range dividing key BP is being sounded is performed.

On the other hand, when the key code KC of the depressed key has a higher pitch relationship than the preset key range dividing key BP, the determination result of the above step Sd5 becomes "NO", and the process proceeds to step Sd8. Proceed. In step Sd8, the fraction delay Df obtained in step Sd3 is set to A
The delay amount (1 + Df / 10) per one is calculated by dividing the number of PF _{1 to} APF ₁₀ by 10, and from this, based on the above-mentioned expression (5), (1 + Df is added to Df of expression (5)).
/ 10) may be substituted.) All-pass coefficients γ of APF ₁ to APF _{1 0} are calculated. Then, the next step Sd
Proceeding to 9, the delay stage number N and the all-pass coefficient γ in this case
And are sent to the DSP 15 side. As a result, pitch control corresponding to the pitch bender operation amount m when a key having a higher pitch relationship than the key range dividing key BP is being sounded is performed.

Operation of DSP 15 Next, a DSP for synthesizing musical sounds according to a microprogram
The operation of 15 will be described with reference to FIG. First,
As described above, when the CPU 10 instructs the micro program to be read at the time of initialization, the DSP 1
Reference numeral 5 loads the program from the microprogram RAM 15a and activates the routine shown in FIG. As a result, the processing of the DSP 15 proceeds to step Se1. In step Se1, it is detected whether or not a key-on event has occurred. Here, when the key-on event is detected, the determination result is “YES”, and the process proceeds to step Se2.

At step Se2, a tone generation setting process is performed so as to produce a tone at a pitch corresponding to the key code KC of the depressed key. The tone generation setting process is a process for forming a tone synthesis algorithm in accordance with the integer stage delay N, the all-pass coefficients α, γ, or the interpolation coefficient β generated in the above-described key-on processing routine or pitch bend processing routine. Then, after this, the process proceeds to step Se3,
A tone output WD is generated based on a tone synthesis algorithm. The tone synthesis algorithm operates as follows.

That is, for example, an initial excitation waveform is generated by a white noise signal having a constant power spectral density and injected into the closed loop, and the number of delay stages of the delay circuit 2 is determined based on the integer stage delay N transferred from the CPU 10 side. Set and delay the noise signal by an integer number of stages. And
Since the output of the delay circuit 2 is delayed by the fractional part Df, CP
The all-pass filter coefficient α given by U10 is used as the all-pass filter 4-1 or the all-pass filter 4
The coefficient γ is set to -2, and the interpolation coefficient β is set to the interpolator 21 according to the pitch control mode.

Next, the set all-pass filter 4
Based on the above, filtering with a decimal delay or low-pass filtering by the low-pass filter 3 to which the filter coefficient LC corresponding to the set tone color number is added is applied, and the result is multiplied by the loop gain. After that,
By repeating such a process and circulating it in the closed loop, a musical tone having a desired pitch is formed.

If the event supplied from the CPU 10 is a key-off event, the process proceeds from step Se4 to step Se5, and the envelope generator is operated at a predetermined rate according to various key-off parameters generated in the key-off processing routine. Sound generation end processing such as dumping is performed.

As described above, according to the above-described embodiment, the plurality of all-pass filters 4-1 and 4-2, and the interpolator 21 provided between the all-pass filter 4-1 and the delay circuit 2 are provided. When the key range dividing key BP for dividing the range into the range and the high range is set as a boundary, and pitches higher than the range dividing key BP are continuously changed by a pitch bender or the like, the delay circuit 2 has N stages. After delaying, all-pass filter 4-
Pitch control is performed by sequentially delaying a fractional number of stages from APF ₁ to APF ₁₀ forming 2. That, APF ₁ ~APF _{1 0} Linearity may have limited range for controlling the delay amount with respect to the change of the coefficients ( "1-step" in the number of delay stages in terms of proximity). Therefore, 10 stages of the integer delay Di are realized by APF ₁ to APF ₁₀ , and the decimal delay Df is 10 APF ₁ to APF.
Df / n is distributed to PF ₁₀ . on the other hand,
When a pitch lower than the key range dividing key BP is continuously changed by a pitch bender or the like, the interpolator 21 smoothly interpolates the integer delay and the decimal delay to perform pitch control. As a result, it becomes possible to smoothly control the pitch without causing any disturbance in the decay time in the entire sound range.

D. Modified Example Next, a modified example of the present invention will be described with reference to FIG. FIG. 8 shows a DS for synthesizing musical sounds corresponding to frequency numbers.
It is a block diagram which shows the functional model of P15, The element same as the Example shown in FIG. In this figure, reference numeral 50 is a frequency number accumulator, which accumulates a frequency number FNO, which is phase information, and outputs an integer part INT and a decimal part FRA.
C, a carry signal CK of the accumulated value integer part is generated. The frequency number accumulator 50 has its accumulated value reset in response to the key-on pulse KOP synchronized with the key-on signal KON. Reference numerals 51 and 52 are interpolators each including a delay element, a multiplier and an adder.

According to the above configuration, the configuration itself of FIG. 8 realized by the microprogram of the DSP 15 operates according to the carry signal CK of the integral part accumulated value of the frequency number FNO, that is, the clock signal corresponding to the pitch. Therefore, the sampling frequency of the synthesized tone changes according to the pitch. In such a case, since the musical sound data WD output from the DSP 15 is output at a constant sampling frequency φs, the interpolators 51 and 52 linearly interpolate the outputs of the closed loops according to the fractional part FRAC of the frequency number FNO accumulated value. The smooth tone data WD corresponding to the constant sampling frequency φs is output. When the pitch control according to the present invention is applied to the DSP having such a calculation sampling timing mode, the pitch is smoothly controlled in the entire tone range without disturbing the decay time even in the tone number synthesizer. It will be possible.

In this embodiment, since APF ₁ to APF ₁₀ are used only in the region where the linearity of the delay change is good (the delay amount is in the vicinity of "1" in terms of the number of stages), A of a plurality of stages (10 stages) is used.
Although the fractional delay Df is distributed to PF _{1 to} APF ₁₀ ,
There is no limit to the number of steps. Further, in this embodiment, the APF
_{Although the} fractional part delay Df is equally distributed to _{1 to} APF _10, it may not be evenly distributed. Furthermore, in the above-described embodiment, the pitch control in the sound source of the delay feedback system is used, but the present invention is not limited to this, and it is also possible to apply it to sound effect processing such as chorus and flanger that modulates according to the delay time. is there. Even in this case, the waveform does not become discontinuous, and smooth control can be realized.

Further, in the above embodiment, the "pitch bend" is taken as an example of the pitch (pitch) control, but it can be used in place of "portamento".
Further, although the low-pass filter 3 (see FIG. 3) is a non-recursive (FIR) digital filter in this embodiment, it may be a known recursive (IIR) digital filter. In this case, when the filter characteristic is changed by various operators such as Joystick, the change in delay time due to the filter is corrected.

Further, in the above-mentioned embodiment, the all-pass filter 4-2 is formed of APF ₁ to APF ₁₀ , but the present invention is not limited to this, and a plurality of stages may be connected in cascade. Further, in the above embodiment, the integer stage delay N, the all-pass coefficients α and γ, and the interpolation coefficient β are calculated for each key-on event. Instead of this, these tone parameters are calculated in advance for each key. A table may be created and read out for each key-on event. By doing so, the processing speed can be increased.

[0050]

According to the present invention, when the pitch of the depressed key is higher than the range dividing point, the pitch control is performed according to the total delay amount of the delay means and the all-pass filter group. On the other hand, when the pitch is on the low frequency side, the pitch is controlled according to the total delay amount of the delay means and the interpolation means, so that the pitch is smoothly controlled without disturbing the decay time in the entire frequency range. be able to.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment according to the present invention.

FIG. 2 is a block diagram showing a functional model of the DSP 15 in the embodiment.

FIG. 3 is a flowchart for explaining the operation of a main routine in the embodiment.

FIG. 4 is a flowchart for explaining the operation of a key-on processing routine in the embodiment.

FIG. 5 is a flowchart for explaining the operation of a key-off processing routine in the embodiment.

FIG. 6 is a flowchart for explaining the operation of a pitch bend processing routine in the embodiment.

FIG. 7 is a flowchart for explaining the operation of the DSP 15 in the same embodiment.

FIG. 8 is a block diagram showing a configuration of a modified example according to the present invention.

FIG. 9 is a diagram for explaining a conventional example.

FIG. 10 is a diagram for explaining a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Adder, 2 ... Delay circuit (delay means), 3 ... Low-pass filter, 4-1 and 4-2 ... All-pass filter (all-pass filter), 10 ... CPU (discrimination means), 11 ...
ROM, 12 ... RAM, 15 ... DSP (first and second
Pitch control means), 21 ... Interpolator (interpolation means), 22 ... Coefficient multiplier.

Claims (2)

[Claims] 1. A delay means for delaying and outputting an input signal by an integer number of stages according to a sampling cycle, and an all-pass filter for delaying the output of this delay means by a fractional number of stages and outputting the output of the all-pass filter. In a musical sound synthesizer that forms a delayed feedback loop that uses an input signal, an interpolating means that is inserted in the loop and interpolates the output of the delaying means, and a range dividing point that divides a sounding range into a high range and a low range. Setting means for determining whether the pitch to be pronounced is on the high-frequency side or the low-frequency side with this range dividing point as a boundary; and when the determination means determines the high-frequency side, the delay First pitch control means for controlling the pitch according to the total delay amount of the means and the all-pass filter, and the total delay amount of the delay means and the interpolation means when the determination means determines the low frequency side According to Musical tone synthesizing apparatus characterized by comprising a second pitch control means for pitch control. 2. A delay unit for delaying and outputting an input signal by an integer number of stages, and a plurality of all-pass filters cascade-connected to the delay unit for delaying and outputting the output of the delay unit by a small number of stages. Closed loop means that uses the output of an all-pass filter as the input signal, excitation signal generation means that supplies an excitation signal to the closed loop means in response to a performance operation, and a decimal stage delay amount of a delay amount D corresponding to a specified pitch. And pitch control means for controlling an integer stage delay of the delay means and each coefficient of the plurality of all-pass filters so that the total delay amount of the closed loop means becomes the delay amount D. A musical sound synthesizing apparatus comprising: