JPH08190448A - Data processing system - Google Patents

Abstract

PURPOSE: To use a peripheral device which does not have a special circuit constitution for hot-line insertion and extraction and enable the peripheral device to be extracted and inserted without stopping the system by providing a bus switch between an input/output bus and each peripheral device and controlling the switch. CONSTITUTION: Bus switches 15-1...15-n consisting of MOS switches for connecting and disconnecting respective peripheral devices 13-1...13-n and the input/output bus 14 are connected between them, and those bus switches 15-1...15-n are controlled with bus disconnection signals 16-1...16-n from a central processor 11. To extract the peripheral device 13-1, the bus disconnection signal 16-1 is asserted which controls the bus switch 15-1 connecting the input/output bus 14 and peripheral device 13-1 from the central processor 11, thereby turning off the bus switch. Consequently, the signal level variation of the bus switch on the side of the peripheral device is never transmitted to the bus side and the peripheral device 13-1 can be extracted in safety even when the system is in operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system and, in addition to removal of a peripheral device when a failure occurs, peripheral device replacement and additional peripheral device connection can be performed without stopping the system, which is excellent in maintainability. Data processing system.

[0002]

2. Description of the Related Art A data processing system such as a computer system has become an essential part of social life as the information-oriented society has permeated. In such a computer society, stopping the computer system has a great influence on the society. Therefore, it is important to perform data processing without stopping the computer system. However, in the conventional computer system, when the peripheral device is replaced or a new peripheral device is added, the computer system is temporarily stopped and the work is performed. Recently, hot-plug technology has made it possible to insert and remove peripheral devices while the system continues to operate. Insertion of such peripherals,
As a removal method, for example, in Japanese Patent Laid-Open No. 2-125314, at the time of inserting a peripheral device, the signal transmission to the bus of another peripheral device is prevented, and the other peripheral device is attempted to be inserted. A method is described in which, after stopping the transmission of a signal onto the bus of the device, the output driver is allowed to stabilize before removal.

[0003]

In the above-mentioned conventional example, there is a problem that the configuration in the peripheral circuit device to be hot-swapped becomes complicated.

An object of the present invention is to provide a system capable of removing and inserting a peripheral device without stopping the system by using the peripheral device having no special circuit configuration for hot-plugging and unplugging. is there.

Another object of the present invention is to provide a system at a low cost because the system can be simply constructed by using such a peripheral device.

[0006]

The features of the present invention for attaining the above-mentioned object are a central processing unit including a memory, an input / output bus connecting the central processing unit and a plurality of peripheral devices, and an input / output bus of the input / output bus. A bus arbiter for controlling transactions, comprising a bus switch between the peripheral device and an input / output bus, and a bus switch connected to the central processing unit, the bus arbiter, and a bus switch control terminal for controlling the control switch. And a control means.

[0007]

A bus switch is provided between the input / output bus and each peripheral device, and the system part that continuously operates controls this switch to electrically disconnect the operating part and the insertion / removal part so that the peripheral device can be inserted / removed. To do. When the bus switch is controlled, the bus arbitration is interrupted, and after the bus switch is switched, the bus signal is settled, and then the bus arbitration is restarted.

According to the present invention, when the peripheral device is removed, the peripheral device is electrically disconnected by the bus switch and then the power switch of the peripheral device is turned off. When the peripheral device is inserted, the power switch is turned on after the peripheral device is inserted. It is connected by a bus switch. As described above, even in a system that uses a peripheral device that does not have a special circuit configuration for hot-swap, a system in which the input / output bus and the peripheral device are connected by a bus switch allows the system to continue operating. By controlling the bus switch that connects any peripheral device, the operating part and the insertion / removal part can be electrically separated, and the system itself that continues to operate can protect the system from problems that occur when the peripheral device is inserted / removed. . In addition, the continuously operating system itself generates a signal indicating that the signal on the bus during bus switch control is invalid for other peripheral devices, so that the signal on the bus during bus switch control causes other The peripheral device does not malfunction and the peripheral device can be removed and inserted without stopping the system, and a low-cost system using a peripheral device that is generally in circulation can be realized.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of a data processing system according to an embodiment of the present invention. The data processing system 10 includes one central processing unit 11, a bus arbiter 12, and one or
A plurality of peripheral devices 13-1, 13-2, ... 13-n are connected via the input / output bus 14, and the respective devices operate while communicating with each other via the input / output bus 14. Further, a bus switch constituted by a MOS switch for connecting and disconnecting each peripheral device 13-1, 13-2, ... 13-n (n is a natural number) and the input / output bus 14 respectively. 15-1, 15-2, ... 15-n are connected to the bus switches 15-1, 15-2,
15-n are controlled by bus disconnection signals 16-1, 16-2, ... 16-n from the central processing unit 11. If it is desired to remove the peripheral device 13-1, a bus disconnection signal 16-1 for controlling the bus switch 15-1 connecting the input / output bus 14 and the peripheral device 13-1 from the central processing unit.
Is asserted and the bus switch is turned off. As a result, the signal level fluctuation on the peripheral device side of the bus switch is not transmitted to the bus side at all, and the peripheral device 13-1 can be safely removed even while the rest of the system including the bus is operating. Further, if the peripheral device 13-2 is desired to be inserted, after the peripheral device 13-2 is inserted, the bus disconnection for controlling the bus switch 15-2 connecting the input / output bus 14 and the peripheral device 13-2 from the central processing unit. By negating the signal 16-2 and turning on the bus switch, the peripheral device 13-2 is connected to the input / output bus 14 without causing a sudden signal level fluctuation (noise). As a result, the peripheral device 13-2 can be inserted and connected without causing the system to malfunction.

FIG. 2 shows a more detailed block diagram of the data processing system of the embodiment of the present invention. The central processing unit 11 is
Processor 21, memory 22, memory controller 23,
It is composed of a bus switch control unit 24. Normally, the processor 21 performs a write operation to the memory 22 and a read operation from the memory 22 via the memory control unit 23, and each peripheral device 1
3-1 and 13-2 are communicated. But,
Removal and replacement of the peripheral device due to a failure in the peripheral device,
Alternatively, when the peripheral device is additionally inserted, a command for switching the bus switch is issued to the bus switch control unit 24. The bus switch control unit 24 instructs the bus arbiter 12 to suspend and restart the arbitration by the bus arbitration suspend signal 25 which is a signal for suspending the bus arbitration when the bus switch is switched. From the bus arbiter 12, which device (the central processing unit 11 and each peripheral device 13-
1, 13-2) receives a bus use permission signal 29 indicating whether the bus is used. In addition, the bus switch control unit 2
No. 4 temporarily generates noise on the input / output bus 14 when the bus switch is switched. Therefore, in order to prevent malfunctions of the peripheral devices 13-1 and 13-2 due to the noise, the peripheral devices 13-1 and 13-2 are prevented. -2, signals 26-1 and 26-2 indicating that the bus signal line is invalid are generated. As a matter of course, if the signal level of the bus is stable, the signal line 26-
Reference numerals 1 and 26-2 indicate that the bus signal is valid. The peripheral devices 13-1 and 13-2 are connected to the power source 27, respectively.
Power is supplied from -1, 27-2 and power switch 28
The power is turned on and off by -1, 28-2. When removing the peripheral device, power switches 28-1, 28-2
Is turned off, and when the peripheral device is inserted, after the peripheral device is inserted, the power switches 28-1 and 28
-2 is turned on.

FIG. 3 shows a flow chart of bus disconnection control according to the embodiment of the present invention. This is the bus switch control unit 24 when a bus disconnection request is generated in response to a peripheral device removal request.
Is the operation. When the bus disconnection request is generated, the bus switch control unit 24 asserts the bus arbitration suspension signal 25 to the bus arbiter 12 to instruct the bus arbitration suspension (step 31). Normally, the bus arbiter 12 responds to a bus use permission request signal (a signal (not shown)) to the input / output bus 14 of the central processing unit 11 and each of the peripheral devices 13-1, 13-2, ... Permission signal (signal not shown)
Is asserted, but the bus arbitration suspend signal 2
5 is asserted, during that time, a bus use permission request for the input / output bus 14 of the central processing unit 11 and each of the peripheral devices 13-1, 13-2, ... 13-n is newly added to the bus use permission request. Do not assert the enable signal. When the bus arbitration interruption signal 25 is asserted, the bus switch control unit 24 checks the presence / absence of the device currently using the bus (step 32). This is done by checking the bus use permission signal output by the bus arbiter 12. If there is the device currently using the bus, wait for the end of the currently executed transaction, that is, the end of the bus use (step 3).
3). As described above, while the bus arbitration suspension signal 25 is asserted, the bus arbiter 12 does not assert the bus use permission signal to the device after the currently executed transaction is completed. After confirming that there is no device using the bus, the bus switch control unit 24 turns off the bus switch that connects the peripheral device (step 34) and disconnects the peripheral device. At this time, in order to prevent malfunction of each peripheral device due to noise that is temporarily generated due to a change in load capacitance caused by turning off the bus switch on the input / output bus 14, the bus switch control unit setstles the bus signal. Until that time (one bus cycle in the embodiment), signals 26-1 and 26-2 indicating whether the bus value is valid or invalid are outputted to the peripheral device (step 35). When the signal on the bus is settled, the signals 26-1 and 26-2 indicating whether the value of the bus is valid or invalid are output to the peripheral device as valid, and the bus arbitration interruption signal 25 is negated. The bus arbiter 12 restarts the bus arbitration (step 36) and restarts the normal operation.

FIG. 4 shows a flow chart of the bus connection control according to the embodiment of the present invention. This is the operation of the bus switch control unit 24 when a bus connection request is generated due to the insertion of a peripheral device. When a bus connection request is generated, the bus switch control unit asserts the bus arbitration interruption signal 25 to the bus arbiter to instruct the bus arbitration interruption (step 41). Normally, the bus arbiter 12 includes the central processing unit 11 and the peripheral devices 13-1, 13-2, ...
In response to a bus use permission request signal (not shown signal) for the I / O bus 14 of 13-n, a bus use permission signal (not shown signal) is asserted for any of the devices, but the bus arbitration suspension signal 25 is asserted. Then, during that time, the central processing unit 11 and each peripheral device 13
In response to the bus use permission request to the input / output buses 14 of -1, 13-2, ... 13-n, the bus use permission signal is not newly asserted for the bus use permission request. The bus switch control unit 24 uses the bus arbitration interruption signal 25.
Is asserted, the presence or absence of the device currently using the bus is checked (step 42). This is done by checking the bus use permission signal output by the bus arbiter 12. If there is a device currently using the bus, end the transaction currently being executed,
That is, it waits for the end of use of the bus (step 43). As described above, while the bus arbitration suspension signal 25 is asserted, the bus arbiter 12 does not assert the bus use permission signal to the device after the currently executed transaction is completed. The bus switch control unit confirms that the device using the bus is not present, and then turns on the bus switch connecting the peripheral device (step 4).
4) Connect the peripheral device. At this time, the input / output bus 14
In order to prevent the peripheral device from malfunctioning due to noise that is temporarily generated by a change in the load capacitance caused by turning on the bus switch, the bus switch control unit 24 waits until the bus signal is settled. (1 bus cycle in the example), the signal indicating invalidity is output to the peripheral device by signals 26-1 and 26-2 indicating whether the bus value is valid or invalid (step 45). When the signals on the bus have settled, the signals 26-1 and 26-2 indicating whether the value of the bus is valid or invalid are output to each peripheral device as valid and the bus arbitration interruption signal 25 is negated. The bus arbiter 12 restarts the bus arbitration (step 46) and restarts the normal operation.

FIG. 5 shows a flow chart of a procedure for removing the peripheral device according to the embodiment of the present invention. With reference to FIG. 2 as an example, when it is desired to remove the peripheral device 13-1, a removal request for the peripheral device is issued to the processor 21 (step 51).
The processor 21 determines whether or not the peripheral device can be removed (step 52). In the processor 21, if the peripheral device is operating normally and it becomes impossible to continue operation as a system due to removal, the peripheral device is terminated as unremovable and the removal request for the peripheral device is canceled. To do. If the processor 21 determines that the peripheral device can be removed, the bus switch 15-1 is turned off to disconnect the peripheral device (step 53). Here, the bus disconnection signal 16-1 is asserted in accordance with the bus disconnection control procedure shown in FIG.
5-1 turns off. This completes the disconnection of the peripheral device (step 54). When the disconnection is completed, the peripheral device and the power source 27-
The power switch 28-1 for connecting 1 is turned off (step 55). After the power switch is turned off, the processing peripheral device is removed (step 56) to complete the removal of the peripheral device without stopping the system.

FIG. 6 shows a flow chart of the procedure for inserting and connecting the peripheral device according to the embodiment of the present invention. Referring to FIG. 2 as an example, when the peripheral device 13-1 is in a removed state and it is desired to insert and connect the peripheral device, the peripheral device is first inserted into the data processing system 10 (step 61). When the insertion is completed, the power switch 28-1 connecting the peripheral device and the power supply 27-1 is turned on to turn on the power of the peripheral device (step 62). When the power switch is turned on, a connection request for the peripheral device is issued to the processor 21 (step 63). When the processor 21 issues a connection request for the peripheral device, the bus switch 15-
1 is turned on and the peripheral device is connected (step 6).
4). Here, according to the bus connection control procedure shown in FIG. 4, the bus disconnection signal 16-1 is negated and the bus switch 15-1 is turned on. This completes the connection of the peripheral device (step 65). As can be seen from this series of steps, any peripheral device can be inserted and connected to the system without stopping the system.

FIG. 7 is a part of a time chart showing an example of normal operation of the data processing system having the configuration of FIG.
First, the signals not shown in FIG. 2 in FIGS. 7, 8 and 9 will be described. The bus clock is an operation clock (60 ns in the example) for performing communication using the bus, and the bus disconnection requests (13-1) and (13-2) are input / output to / from the peripheral devices 13-1 and 13-2. It is a request to disconnect from the bus 14, and bus connection requests (13-1), (13
-2) is a connection request to the input / output bus 14 to the peripheral devices 13-1 and 13-2, and the bus use right request (11),
(13-1) and (13-2) are requests for the right to use the input / output bus 14 from the central processing unit 11 and the peripheral devices 13-1 and 13-2 to the bus arbiter 12, and the bus use permission is given.
(11), (13-1), (13-2) are bus arbiters 12
Central processing unit 11 and peripheral devices 13-1 and 13-2
Permission to use the I / O bus 14 for
The data is an address and data transferred on the input / output bus, and the transfer end signal is a signal indicating the end of the transfer using the input / output bus. Next, FIG. 7 will be described. First, in cycle number 1, the peripheral device 13-1 asserts a bus use right request (13-1) to the bus arbiter 12. Bus arbiter 1 in cycle number 2
2 permits the peripheral device 13-1 to use the bus (13-
1) is asserted. In cycle number 3, the peripheral device 13-2 asserts the bus use right request (13-2) to the bus arbiter 12. In addition, the peripheral device 13
-1 receives the bus use permission (13-1), negates the bus use right request (13-1), and transfers addresses and data in cycle numbers 3, 4, and 5. In cycle number 5, the peripheral device 13-1
Asserts a transfer end signal indicating the end of transfer. In cycle number 6, the bus arbiter 12 receives the transfer end signal, and grants the bus use permission from the peripheral device 13-1 to the peripheral device 1.
Assert for 3-2. In cycle number 7, the peripheral device 13-2 receives the bus use permission (13-2) and negates the bus use right request (13-2), and transfers the address and data in cycle numbers 7, 8 and 9. I do. In cycle number 9, the peripheral device 13-2 asserts the transfer end signal indicating the end of transfer. In cycle number 10, the bus arbiter 12 receives the transfer end signal and negates the bus use permission (13-2). Further, the operation is continuously performed even after the cycle number 11.

FIG. 8 is a part of a time chart showing an example of the operation of the data processing system configured as shown in FIG. 2 when the bus is disconnected. In cycle number 1, the peripheral device 13-
1 to the bus arbiter 12 requesting the bus right (13
-1) is asserted. In cycle number 2, the bus arbiter 12 asserts the bus use permission (13-1) to the peripheral device 13-1. In cycle number 3, the peripheral device 13-2 asserts the bus use right request (13-2) to the bus arbiter 12. Also, a bus disconnection request to the peripheral device 13-1 (13-1)
Is asserted. Further, the peripheral device 13-1 receives the bus use permission (13-1) and requests the bus use right (13-
1) is negated and cycle numbers 3, 4, 5
At, the address and data are transferred. In cycle number 4, the bus switch control unit 24 receives the bus disconnection request (13-1) and asserts the bus arbitration interruption signal 25 to the bus arbiter 12.
In cycle number 5, the peripheral device 13-1 asserts a transfer end signal indicating the end of transfer. Further, the bus arbiter 12 receives the bus arbitration suspension signal 25 and suspends the bus arbitration. In cycle number 6, the bus arbiter 12 receives the transfer end signal, negates the bus use permission (13-1), and at the same time, the bus use permission (11), (13-1), (13-
Do not assert 2). In cycle number 7, the bus switch control unit 24 asserts the bus disconnection signal 16-1 in response to the fact that the bus use permission is not asserted in any of the devices, turns off the bus switch 15-1, and turns on the peripheral device. 13-1 is in a separated state.
At this time, the load capacitance on the input / output bus changes and noise occurs in the signal on the input / output bus. Therefore, the bus switch control unit 24 asserts bus signal line invalidations 26-1 and 26-2 to the peripheral devices 13-1 and 13-2. In cycle number 8, the bus switch control unit 24 negates the bus arbitration interruption signal 25 and instructs the bus arbiter to restart the bus arbitration. Also,
The bus disconnection request (13-1) is negated by asserting the bus disconnection signal 16-1. In cycle number 9, the bus arbiter restarts the bus arbitration. In cycle number 10, the bus arbiter 12 permits the peripheral device 13-2 to use the bus (1
3-2) is asserted. In cycle number 11, the peripheral device 13-2 receives the bus use permission (13-2) and negates the bus use right request (13-2), and in the cycle numbers 11 and 12, the address and
Transfer data. Further, the operation is continuously performed after the cycle number 12 and thereafter. FIG. 9 is a part of a time chart showing an example of the operation of the data processing system configured as shown in FIG. 2 when the bus is connected. Peripheral device 13 in cycle number 1
-1 to bus arbiter 12 request bus usage right (1
3-1) is asserted. At this time, the peripheral device 13-2
Is in the disconnected state, and the bus disconnection signal 1
6-2 is asserted. In cycle number 2, the bus arbiter 12 asserts the bus use permission (13-1) to the peripheral device 13-1. Cycle number 3
At the bus connection request to the peripheral device 13-2 (13
-2) is asserted. In addition, the peripheral device 13-1 is
When the bus use permission (13-1) is received, the bus use right request (1
3-1) and the cycle number 3,
Addresses and data are transferred at 4 and 5. In cycle number 4, the bus switch control unit 24 receives the bus connection request (13-2) and asserts the bus arbitration interruption signal 25 to the bus arbiter 12. In cycle number 5, the peripheral device 13-1 asserts a transfer end signal indicating the end of transfer. Further, the bus arbiter 12 receives the bus arbitration suspension signal 25 and suspends the bus arbitration. In cycle number 6, the bus arbiter 12 receives the transfer end signal,
The bus use permission (13-1) is negated, and the bus use permission (11), (13-1), (13) is given to the device.
-2) is not asserted. In cycle number 7, the bus switch control unit 24 negates the bus disconnection signal 16-2 in response to the fact that the bus use permission is not asserted in any of the devices, the bus switch 15-2 is turned on, and the peripheral device is turned on. 13-2 is in a connected state.
At this time, the load capacitance on the input / output bus changes and noise occurs in the signal on the input / output bus. Therefore, the bus switch control unit 24 asserts bus signal line invalidations 26-1 and 26-2 to the peripheral devices 13-1 and 13-2. Further, the bus right request (13-1) is asserted from the peripheral device 13-1 to the bus arbiter 12. Cycle number 8
At, the bus switch control unit 24 negates the bus arbitration interruption signal 25 and instructs the bus arbiter to restart the bus arbitration. Further, the bus connection request (13-2) is negated because the bus disconnection signal 16-2 is negated. Cycle number 9
At, the bus arbiter resumes bus arbitration. In cycle number 10, the bus arbiter 12 asserts the bus use permission (13-1) to the peripheral device 13-1.

In cycle number 11, the peripheral device 13
-1 receives the bus use permission (13-1), negates the bus use right request (13-1), and transfers addresses and data in cycle numbers 11 and 12. Further, the operation is continuously performed after the cycle number 12 and thereafter.

In the above-described embodiment of the present invention, the central processing unit and the bus arbiter are independent of each other.
There is no problem even if the bus arbiter is provided in the central processing unit.

[0020]

EFFECTS OF THE INVENTION According to the present invention, (1) the peripheral device does not have a special circuit configuration for hot-plugging and unplugging by controlling the bus switch for connecting the peripheral device by the system for continuous operation. Since the system can be connected and disconnected, and the system can be protected from problems when the peripheral device is removed or inserted, hot plugging and removal of the peripheral device can be reliably performed.

(2) Since a general peripheral device having no special circuit configuration for hot-plugging / unplugging can be used, a low-cost system can be constructed.

(3) During control of the bus switch, the system that continuously operates generates a signal that invalidates the signal on the bus until the signal on the bus stabilizes. The system will not malfunction even if the bus signal is received.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a data processing system according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a data processing system according to the embodiment of this invention.

FIG. 3 is a flowchart of bus disconnection control according to the embodiment of this invention.

FIG. 4 is a flow chart of bus connection control according to the embodiment of the present invention.

FIG. 5 is a flowchart of a procedure for removing a peripheral device according to the embodiment of this invention.

FIG. 6 is a flow chart of a procedure of inserting and connecting a peripheral device according to the embodiment of the invention.

FIG. 7 is a time chart diagram during normal operation of the data processing system.

FIG. 8 is a time chart diagram when the bus of the data processing system is disconnected.

FIG. 9 is a time chart diagram when the bus of the data processing system is connected.

[Explanation of symbols]

10 ... Data processing system, 11 ... Central processing unit, 12
... bus arbiter, 13-1, 13-2, 13-n ... peripheral device, 14 ... input / output bus, 15-1, 15-2, 15-
n ... Bus switch, 16-1, 16-2, 16-n ... Bus disconnection signal, 21 ... Processor, 22 ... Memory, 2
3 ... Memory control unit, 24 ... Bus switch control unit, 25 ...
Bus arbitration interruption signal, 26-1, 26-2
... Bus signal line invalid, 27-1, 27-2 ... Power supply, 28-
1, 28-2 ... Power switch.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshihiro Miyazaki 5-2-1, Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Omika factory

Claims (8)

[Claims] 1. A central processing unit including a memory, an input / output bus connecting the central processing unit and a plurality of peripheral devices, and a bus arbiter for controlling transactions of the input / output bus. A data processing system comprising: a bus switch between the input and output buses; and a bus switch control means for controlling the central switch, the bus arbiter, and the bus switch control terminal and controlling the control switch. 2. The bus switch according to claim 1, wherein the bus switch is a MOS.
A data processing system comprising a switch, wherein the bus switch control means generates a signal for turning off the bus switch when removing the peripheral device and for turning on the bus switch when inserting the peripheral device. 3. A bus switch control means according to claim 1, wherein the bus switch control means interrupts bus arbitration before turning off the bus switch, waits for completion of a transaction currently being executed on the bus, and turns off the bus switch after completion. The data processing system is characterized in that the bus arbitration is restarted after a certain period of time when the signal of the bus settles down. 4. The bus switch control means according to claim 1, wherein when the bus switch is turned off, a signal indicating that the value of the bus at that time is invalid for a certain period of time until arbitration is restarted is sent to each peripheral device. A data processing system characterized by being generated. 5. The bus switch control means according to claim 1, before the bus switch is turned on, interrupts the bus arbitration, waits for the end of the transaction currently being executed on the bus, and turns on the bus switch after the end. The data processing system is characterized in that the bus arbitration is restarted after a certain period of time when the signal of the bus settles down. 6. The bus switch control means according to claim 4, wherein when the bus switch is turned on, a signal indicating that the value of the bus at that time is invalid for a fixed time until arbitration is restarted is given to each peripheral device. A data processing system characterized by being generated. 7. The device according to claim 1, wherein each of the plurality of peripheral devices has a power source, and when removing the peripheral device, first turn off the bus switch,
After that, the power switch of the peripheral device is turned off, and then the peripheral device is removed. 8. The peripheral device according to claim 1, wherein each of the plurality of peripheral devices has a power source, and when the peripheral device is inserted, first, the peripheral device is inserted and a power switch of the peripheral device is inserted. Is turned on, and then the bus switch is turned on to complete the insertion of the peripheral device.