JPH08186778A - Display control circuit and liquid crystal television - Google Patents

Abstract

PURPOSE: To keep the vibration of a master clock at a least necessary proper level where no reception disturbance is produced by outputting such a master clock through a control amplifier to compensate the reduction of amplitude that is caused by the band characteristic of an LPF. CONSTITUTION: In a display controller 15, the master clock generated by a PLL circuit 20 based on a horizontal synchronizing signal is inputted to a control amplifier 1 via a buffer 3. The amplitude of the master clock is controlled by the amplifier 1 and the master clock is sent to an LPF 23. A control part 2 sends a gain control signal to the amplifier 1 based on the frequency information on the master clock to change the gain of the amplifier 1. Then the part 2 controls the amplitude of the master clock at a fixed level. The master clock having its controlled amplitude has the reduction of amplitude due to the band characteristic of the LPF 23 when the master clock passes through this LPF. In this case, however, such a master clock is outputted from the amplifier 1 to compensate the reduction of amplitude. As a result, the vibration of the master clock is kept at a least necessary proper level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control circuit and a liquid crystal television using the display control circuit.

[0002]

2. Description of the Related Art A conventional display control circuit of a liquid crystal television will be described with reference to FIG. The display control circuit of the liquid crystal television shown in FIG. 5 is a voltage controlled oscillator (VCO).
A horizontal synchronizing signal is taken in by a PLL circuit 20 including a PLL 21 and a PLL filter 22 to generate a master clock, and the master clock is passed through a low-pass filter 23 including a resistor R ₁ , a capacitor C ₁ , a coil L, and a capacitor C _{2 for} liquid crystal display. It is designed to be supplied to blocks. The low-pass filter 23 is used to prevent digital noise included in the master clock from causing radiation noise in the RF tuner system and causing reception noise.

The above-mentioned master clock means a relationship that the number of clocks of the video signal generated by the PLL circuit 20 based on the horizontal synchronizing signal in one horizontal scanning period is substantially equal to the number of pixels in the horizontal direction of the display panel. Is.

During normal reception of a good video signal, the horizontal synchronizing signal is stable and its frequency is about 15.73 KH.
Therefore, in the case of a liquid crystal display panel having 320 horizontal pixels, the master clock frequency is 15.73 KHz × 400 = 6.3 MHz. Here, the frequency of the master clock is set to 400 times the frequency of the horizontal synchronization signal because {1 horizontal scanning period time (64 μs) / 1 horizontal scanning period video display time} × 3
This is due to the calculation of 20.

[0005]

However, during actual channel selection or in an environment of a weak electric field (below the synchronization sensitivity), a lot of noise is introduced into the horizontal synchronization signal, and the horizontal synchronization signal has a frequency of 1
It will be more than 5.73 KHz. Therefore, the frequency of the master clock also rises to about 10 MHz depending on the capture range of the PLL circuit 20.

When such a master clock is passed through the low-pass filter 23 shown in FIG. 4, a sufficient amplitude level is obtained at 6.3 MHz as shown in FIG. There is a problem that α occurs, which makes it impossible to obtain a sufficient amplitude level, which causes malfunction of the display block. Conversely, if the characteristics of the low-pass filter 23 are reduced (the band is widened) so as to obtain an amplitude level that does not cause a malfunction, there is a problem in that reception interference increases this time.

Therefore, the present invention is to provide a display control circuit capable of maintaining the amplitude level of the master clock at the minimum necessary proper level without causing reception interference, and a liquid crystal television using this display control circuit. It is intended.

[0008]

According to the first aspect of the present invention,
In a display control circuit that generates a master clock based on a horizontal synchronizing signal by a PLL circuit and uses this master clock to control a display block through a low-pass filter, a gain that adjusts the amplitude of the master clock from the PLL circuit and sends to the low-pass filter. A variable amplitude adjusting circuit and a gain control circuit that sends a gain control signal to the amplitude adjusting circuit based on frequency information of the master clock to change the gain and control the amplitude of the master clock to a constant level are provided. It is a feature.

According to a second aspect of the present invention, a PLL circuit generates a master clock based on a horizontal synchronizing signal, and the master clock is output during channel selection in a display control circuit for controlling a display block through a low pass filter. A filter characteristic changing circuit for changing the characteristic of the low-pass filter based on the search signal to control the amplitude of the master clock to a constant level is provided.

According to a third aspect of the present invention, the display control circuit according to the first or second aspect generates a master clock based on a horizontal synchronizing signal output from a television circuit, and the master clock is passed through a low pass filter. The configuration is used for controlling the display block.

The invention according to claim 4 is characterized in that the master clock generated by the display control circuit according to any one of claims 1 to 3 is supplied to a liquid crystal display block.

According to a fifth aspect of the present invention, a television circuit, a sync separation circuit for extracting a horizontal synchronization signal from a television signal received by the television circuit, and a P
In a liquid crystal television provided with a display control circuit for generating a master clock based on a horizontal synchronizing signal by an LL circuit and using this master clock for control of a liquid crystal display block through a low pass filter, the display control circuit is configured to operate from the PLL circuit. A gain adjustment variable amplitude adjusting circuit that adjusts the amplitude of the master clock and sends it to a low-pass filter, and sends a gain control signal to the amplitude adjusting circuit based on the frequency information of the master clock to change the gain to change the amplitude of the master clock. And a gain control circuit for controlling to a constant level.

According to a sixth aspect of the present invention, there is provided a television circuit, a sync separation circuit for extracting a horizontal synchronization signal from a television signal received by the television circuit, and P.
In a liquid crystal television provided with a display control circuit which generates a master clock based on a horizontal synchronizing signal by an LL circuit and uses this master clock to control a liquid crystal display block through a low pass filter, the display control circuit is a liquid crystal television. It is characterized in that a filter characteristic changing circuit for controlling the amplitude of the master clock to a constant level by changing the characteristic of the low-pass filter based on the search signal output during channel selection is characterized.

[0014]

In the display control circuit according to the first aspect of the present invention, the variable gain amplitude adjusting circuit adjusts the amplitude of the master clock from the PLL circuit and sends the adjusted master clock to the low-pass filter. A gain control signal is sent to the amplitude adjusting circuit based on the frequency information to change the gain and control the amplitude of the master clock to a constant level. As a result, it is possible to control the display block while maintaining the amplitude level of the master clock at the minimum necessary proper level that does not cause reception interference.

In the display control circuit according to claim 2, P
The master clock generated by the LL circuit is used for controlling the display block through a low pass filter.
At this time, the filter characteristic changing circuit changes the characteristic of the low-pass filter based on the search signal output during tuning to control the amplitude of the master clock to a constant level.
As a result, the display block can be controlled while maintaining the amplitude level of the master clock at the minimum necessary proper level that does not cause reception interference, as in the first aspect of the invention.

According to a third aspect of the present invention, the display control circuit according to the first or second aspect generates a master clock based on a horizontal synchronizing signal output from a television circuit, and the master clock is passed through a low pass filter. Since the configuration is used for controlling the display block, the amplitude level of the master clock generated based on the horizontal synchronizing signal output from the television circuit is maintained at the minimum necessary proper level that does not cause reception interference. Then, the display block can be controlled.

According to a fourth aspect of the present invention, the master clock is such that the amplitude level output from the display control circuit according to the first to third aspects is maintained at a necessary minimum proper level that does not cause reception interference. Is used for controlling the liquid crystal display block, the liquid crystal display block can be stably operated without malfunction.

A liquid crystal television set according to a fifth aspect of the present invention is a television circuit, a sync separation circuit for extracting a horizontal synchronization signal from a television signal received by the television circuit, and a master circuit based on the horizontal synchronization signal by a PLL circuit. A display control circuit that generates a clock and uses this master clock to control a liquid crystal display block through a low-pass filter is provided, and the amplitude of the master clock from the PLL circuit is adjusted by an amplitude adjustment circuit with a variable gain in this display control circuit. To the low pass filter. At this time, the gain control circuit sends a gain control signal to the amplitude adjusting circuit based on the frequency information of the master clock to change the gain and control the amplitude of the master clock to a constant level. As a result, it is possible to control the liquid crystal display block while maintaining the amplitude level of the master clock at the minimum necessary proper level that does not cause reception interference.
The liquid crystal display block in this liquid crystal television can be operated stably without malfunction.

A liquid crystal television set according to claim 6 is a television circuit, a sync separation circuit for extracting a horizontal synchronization signal from a television signal received by the television circuit, and a master circuit based on the horizontal synchronization signal by a PLL circuit. It is equipped with a display control circuit that generates a clock and uses this master clock to control the liquid crystal display block through a low-pass filter.The filter characteristic changing circuit in this display control circuit provides a search signal output during tuning of the liquid crystal television. Based on this, the characteristics of the low-pass filter are changed so that the amplitude level of the master clock is maintained at a necessary minimum proper level that does not cause reception interference and is sent to the liquid crystal display block. Operates the liquid crystal display block stably without malfunction It is possible.

[0020]

EXAMPLES Examples of the present invention will be described in detail below. The display control circuit 15 of this embodiment shown in FIG. 1 is provided between a low-pass filter 23 and a PLL circuit 20 including a voltage-controlled oscillator 21 and a PLL filter 22 similar to the conventional example. The control amplifier 1 is an amplitude adjusting circuit that adjusts the amplitude of the master clock from the circuit 20 and sends it to the low-pass filter 23, and the gain control of the control amplifier 1 based on the frequency information of the master clock from the PLL circuit 20. A control unit 2 that is a gain control circuit that sends a signal to change the gain of the control amplifier 1 to control the amplitude of the master clock to a constant level, and a buffer 3 connected between the PLL circuit 20 and the control amplifier 1. It has.

The operation of the display control circuit 15 shown in FIG. 1 will be described below. In the display control circuit 15, the PL
The master clock generated by the L circuit 20 based on the horizontal synchronizing signal is input to the control amplifier 1 via the buffer 3, and the amplitude of the master clock is adjusted by the control amplifier 1 and sent to the low-pass filter 23. At this time, The control unit 2 sends a gain control signal to the control amplifier 1 based on frequency information of the master clock to change the gain and control the amplitude of the master clock to a constant level. The master clock whose amplitude is controlled to a constant level in this way has a decrease in amplitude due to the band characteristic of the low-pass filter 23 when passing through the low-pass filter 23. A master clock having an amplitude that compensates for this decrease. Is output from the control amplifier 1, it is possible to maintain the amplitude level of the master clock sent to the display block at a necessary minimum proper level that does not cause reception interference.

Next, referring to FIG. 2, another embodiment of the present invention.
Will be explained. The display control circuit 16 shown in FIG.
Similar resistance R₁, Capacitor C₁, Coil L, conden
SA C ₂The low-pass filter 23 consisting of
It has an extremely simple structure with a further circuit (switch) 10.
It is a feature. That is, the low-pass filter 23
Capacitor C in₂Shown during tuning between the ground and the ground
Not output from tuning control IC
Operating based on the reach signal (usually the mute signal)
Sensor C₂Characteristics changing circuit that connects and disconnects between the ground and ground
10 are connected.

According to the display control circuit 16 shown in FIG. 2, the search signal output from the tuning control IC during the channel selection period is considered in consideration of the disturbance of the horizontal synchronizing signal during the normal channel selection. Based on this, the filter characteristic changing circuit 10 disconnects the capacitor C ₂ from the ground and changes the band characteristic of the low pass filter 23 to control the amplitude of the master clock to a constant level. As a result, the amplitude level of the master clock can be maintained at the minimum necessary proper level that does not cause reception interference with a simpler configuration than the display control circuit 15 shown in FIG.

Next, an embodiment of a liquid crystal television using the display control circuit 15 shown in FIG. 1 will be described with reference to FIG. The liquid crystal television shown in FIG. 3 has an antenna 11 for receiving television broadcast waves, a tuner 12 for tuning the television signal received by the antenna 11, and a television signal tuned by the tuner 12. And a sync separation circuit 14 for extracting a horizontal sync signal from the television signal received by the television circuit 13, and a master clock is generated based on the horizontal sync signal extracted by the sync separation circuit 14. The display control circuit 15 having the configuration shown in FIG. 1 for outputting the master clock and the liquid crystal display block 17 which is display-controlled by the master clock from the display control circuit 15 are provided.

The operation of the liquid crystal television shown in FIG. 3 will be described below. Antenna 1 in this LCD television
The television broadcast radio wave received by 1 is tuned by the tuner 12, amplified by the television circuit 13, detected and demodulated, and sent to the liquid crystal display block 17. As a result, a television image is displayed on the screen of the liquid crystal display block 17, but at this time, the sync separation circuit 14 extracts a horizontal sync signal from the television signal received by the television circuit 13, It is sent to the display control circuit 15.

The display control circuit 15 inputs the master clock generated by the PLL circuit 20 based on the horizontal synchronizing signal to the control amplifier 1 via the buffer 3 as in the case described above. The amplitude of the master clock is adjusted and sent to the low pass filter 23. At this time, the control unit 2 sends a gain control signal to the control amplifier 1 based on the frequency information of the master clock to change the gain and control the amplitude of the master clock to a constant level. As a result, the amplitude level of the master clock sent to the liquid crystal display block 16 is maintained at the minimum necessary proper level that does not cause reception interference, and the malfunction of the liquid crystal display block 17 is eliminated. Good quality images can be displayed on the screen of 17.

In the liquid crystal television shown in FIG. 3,
Although the case where the circuit having the configuration shown in FIG. 1 is used as the display control circuit 15 has been described, the display control circuit 16 shown in FIG.
It is of course possible to configure a liquid crystal television using. In this case, as in the case of the liquid crystal television shown in FIG. 3, the master clock generated by the PLL circuit 20 based on the horizontal synchronizing signal is the low-pass filter 2.
The signal is sent to the liquid crystal display block 17 through 3 and at this time, based on a search signal output from a tuning control IC (not shown) during the channel selection period of the liquid crystal television, the filter characteristic changing circuit 10 causes the capacitor C ₂ Is disconnected from the ground, and the band characteristic of the low-pass filter 23 is changed to control the amplitude of the master clock to a constant level. As a result, the amplitude level of the master clock can be maintained at the necessary minimum proper level that does not cause reception interference with a simpler configuration than the liquid crystal television shown in FIG. 3, and malfunction of the liquid crystal display block 17 is eliminated. Thus, a good quality image can be displayed on the screen of the liquid crystal display block 17.

[0028]

According to the first aspect of the present invention, it is possible to provide a display control circuit capable of maintaining the amplitude level of the master clock at the minimum necessary proper level without causing reception interference.

According to the second aspect of the present invention, the amplitude level of the master clock can be maintained at the minimum necessary proper level that does not cause reception interference, as in the first aspect of the invention, with a simpler configuration. A display control circuit capable of providing the display control circuit can be provided.

According to the third aspect of the invention, the master clock whose amplitude level is maintained at the minimum necessary proper level without causing reception interference is displayed based on the horizontal synchronizing signal output from the television circuit. A display control circuit that can be used for block control can be provided.

According to the invention described in claim 4, the display control circuit according to claims 1 to 3 provides a master clock whose amplitude level is maintained at a necessary minimum proper level without causing reception interference. The liquid crystal display block can be controlled, and the liquid crystal display block can be operated stably without malfunction.

According to the fifth aspect of the invention, the liquid crystal display block can be controlled in a state in which the amplitude level of the master clock is maintained at the minimum necessary proper level that does not cause reception interference. A liquid crystal television capable of stably operating a display block without malfunction and displaying a high-quality image can be provided.

According to the invention of claim 6, a liquid crystal display block can be stably operated without malfunction by using a display control circuit having a simpler structure than that of the invention of claim 5, and a high quality image can be obtained. A liquid crystal television capable of displaying can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a display control circuit of the present invention.

FIG. 2 is a block diagram showing another embodiment of the display control circuit of the present invention.

FIG. 3 is a block diagram of a liquid crystal television including the display control circuit according to the present embodiment.

FIG. 4 is a waveform diagram showing a state in which the amplitude level of the master clock is lowered in the display control circuit of the conventional liquid crystal television.

FIG. 5 is a block diagram showing a display control circuit of a conventional liquid crystal television.

[Explanation of symbols]

 1 Control Amplifier 2 Control Section 3 Buffer 11 Antenna 12 Tuner 13 Television Circuit 14 Sync Separation Circuit 15 Display Control Circuit 16 Display Control Circuit 17 Liquid Crystal Display Block 20 PLL Circuit 21 Voltage Controlled Oscillator 22 PLL Filter 23 Low Pass Filter

Claims (6)

[Claims] 1. A display control circuit for generating a master clock based on a horizontal synchronizing signal by a PLL circuit and using this master clock for controlling a display block through a low pass filter, by adjusting the amplitude of the master clock from the PLL circuit. A variable gain amplitude adjustment circuit for sending to a low-pass filter; and a gain control circuit for sending a gain control signal to the amplitude adjustment circuit based on frequency information of the master clock to change the gain to control the amplitude of the master clock to a constant level. A display control circuit characterized by being provided. 2. A display control circuit for generating a master clock based on a horizontal synchronizing signal by a PLL circuit and using the master clock for controlling a display block through a low pass filter, based on a search signal output during channel selection. A display control circuit comprising a filter characteristic changing circuit for changing the characteristic of the filter to control the amplitude of the master clock to a constant level. 3. The display control according to claim 1, wherein a master clock is generated based on a horizontal synchronizing signal output from the television circuit, and the master clock is supplied to the control of the display block through a low pass filter. circuit. 4. The display control circuit according to claim 1, wherein the master clock is supplied to a liquid crystal display block. 5. A television circuit, a sync separation circuit for extracting a horizontal synchronizing signal from a television signal received by the television circuit, and a PLL circuit for generating a master clock based on the horizontal synchronizing signal, and the master clock. And a display control circuit for controlling the liquid crystal display block through a low-pass filter, wherein the display control circuit adjusts the amplitude of the master clock from the PLL circuit and sends the variable gain to the low-pass filter. An adjusting circuit and a gain control circuit for controlling the amplitude of the master clock to a constant level by sending a gain control signal to the amplitude adjusting circuit based on frequency information of the master clock to change the gain. LCD television. 6. A television circuit, a sync separation circuit for extracting a horizontal synchronizing signal from a television signal received by the television circuit, and a PLL circuit for generating a master clock based on the horizontal synchronizing signal, and the master clock. In a liquid crystal television provided with a display control circuit for controlling the liquid crystal display block through a low-pass filter, the display control circuit displays the characteristics of the low-pass filter based on a search signal output during tuning of the liquid crystal television. A liquid crystal television characterized by comprising a filter characteristic changing circuit for controlling the amplitude of the master clock to a constant level.