JPH08186193A - Circuit substrate and semiconductor device using it - Google Patents

Abstract

PURPOSE: To suppress partial discharge from occurring and to prevent insulation deterioration by providing a means for short-circuiting an insulation capacitance component on a circuit substrate. CONSTITUTION: A semiconductor chip 107 and a support substrate 101 are insulated by an insulation plate 104. Namely, an insulation capacitance component 113 (Cd) is generated at a space between a metal foil 102 at a region 111 and the insulation plate 104 outside an insulation capacitance constituent 114 (CA1 ) in the region 111 which is not joined to an insulation capacitance component 112 (CA2 ) in a region 110 which is joined to a metal foil 102. Cd is connected in series to a parallel circuit consisting of CA1 and CA2 . When a voltage V1 116 is applied to a module, a voltage (Vd) is applied to Cd in a circuit where the Cd is simply connected to a parallel circuit consisting of CA1 and CA2 . At this time, when a space for forming the Cd is, for example, an air layer, Vd increases and a partial discharge occurs. However, the Cd is short-circuited, e.g. by a conductor layer 109 and Vd can be reduced, thus suppressing partial discharge.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board and a semiconductor device using the same, and more particularly to a structure of a high breakdown voltage semiconductor module which achieves high reliability by suppressing partial discharge.

[0002]

2. Description of the Related Art Conventionally, there has been known a power semiconductor module in which power semiconductor elements such as an insulated gate bipolar transistor (IGBT), a diode, a gate turn-off thyristor (GTO) and a transistor are sealed in an insulating container. In such a module, the metal support substrate portion and the current conducting portion are electrically insulated from each other for the convenience of use. That is, the insulating substrate is mounted on the supporting substrate with solder or a metal brazing material, and the semiconductor element is further mounted on the insulating substrate.

As a method of mounting the insulating substrate, a method of directly forming a plated metallized layer on the insulating substrate and joining them by soldering or a method of directly joining metal foils on the upper and lower sides of the insulating substrate and then mounting them on a supporting substrate are carried out. There is a way. In the case of the latter method, a substrate in which a copper foil is directly bonded to an insulating substrate by a metal brazing material (Direct Bond Copper, DBC for short) is used. In this DBC substrate, the copper foil on which the semiconductor element is mounted also serves as wiring for forming an electric circuit, and the withstand voltage between the main terminals of the module is determined by the distance between the copper foils provided with the main terminals. The withstand voltage to the outside of the module is determined by the distance from the end of each copper foil to the end of the insulating substrate and the insulation capacitance of the insulating substrate.

In the conventional DBC substrate, problems such as the warp of the substrate and the peeling of the metal foil are solved by optimizing the thickness of the front and back metal foils of the insulating substrate. However, when the DBC substrate is incorporated in the module, the stress balance changes because the module support substrate and the electrode lead-out terminals to the outside of the module are joined. Therefore, there is a problem that the interface between the metal brazing material and the insulating substrate is peeled off or the insulating substrate is cracked.

As a method for solving these problems, there are techniques described in JP-A-60-32343 and JP-A-5-21641. Japanese Unexamined Patent Publication No. 60-32343 discloses a technique for strengthening bonding by adding an active metal to a brazing filler metal to form an alloy layer of copper and the active metal. On the other hand, JP-A-5-21641 discloses that a gap is provided between the metal foil at the electrode extraction terminal joining position to the outside of the module and the insulating substrate, and a curved portion is provided on the metal foil at the portion where the cap is provided. A technique for absorbing stress is disclosed.

[0006]

SUMMARY OF THE INVENTION In these prior arts, in a portion where a sink or a void of a brazing material for joining a metal foil and an insulating substrate is generated, or in a portion where a gap is provided between the metal foil and the insulating substrate, Insulation capacitance component is generated. This insulating capacitance component is connected in series with the insulating capacitance component due to the insulating substrate. If a high voltage is applied to the module at this time,
Partial discharge (corona discharge) occurs in the space layer where the insulating capacitance component is generated. Partial discharge during use of the module deteriorates the filler inside the module such as silicone gel, and eventually leads to deterioration of insulation. Further, the partial discharge at the time of switching causes noise, and this noise causes malfunction especially in the module of the insulated gate type element such as IGBT.

The present invention has been made in view of the above points, and its main object is to provide a circuit board in which the occurrence of partial discharge is suppressed and a semiconductor device using the same.

[0008]

The circuit board of the present invention has means for short-circuiting the above-mentioned insulating capacitance component.

Specifically, the first conductive layer is provided on one surface of the insulating plate, and the surface of or inside the insulating plate is opposed to the first conductive layer, and is therefore separated from the first conductive layer. To provide a second conductive layer. Further, the first conductive layer and the second conductive layer are electrically connected by a conductor.

Also, in the semiconductor device of the present invention, the semiconductor element is bonded to the first conductive layer of the circuit board as described above, and the other surface of the insulating substrate, that is, the surface opposite to the first conductive layer, is formed. It joins with a conductive substrate.

[0011]

In the circuit board of the present invention, even if an insulating capacitance component is generated due to a sink mark or void of the brazing material or a gap provided between the first conductive layer and the insulating substrate, The insulating capacitance component is short-circuited by the second conductive layer and the conductor. Therefore, since no voltage is applied to the insulating capacitance component, partial discharge can be prevented.

Further, in the semiconductor device of the present invention provided with such a circuit board, deterioration of the filler due to partial discharge and malfunction of the semiconductor element can be prevented. Therefore, the reliability of the semiconductor device is improved.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a part of a semiconductor device according to an embodiment of the present invention, which mounts a circuit board having a conductor layer around a metal foil. (A) is a cross-sectional structure and (b) is an equivalent circuit.

Metal foils 102 and 103 made of copper material are bonded to respective surfaces of an insulating plate 104 made of aluminum nitride by a metal brazing material 105 containing silver as a main component. Here, the metal foil 102 is the first conductive layer and serves as wiring for forming a circuit. Metal foil 102,10
3, the insulating plate 104, and the brazing metal 105 constitute a so-called DBC substrate 117. Furthermore, the insulating plate 1
In a region 111 where 04 and the metal foil 102 are not joined, a conductor layer 109, that is, a second conductive layer is provided on the surface of the insulating plate 104 facing the metal foil 102. Here, the conductor layer 109 is in contact with the metal brazing material.
Therefore, the metal foils 102 and 103 are electrically connected by the metal brazing material 105 which is a conductor.

The metal foil 10 of the circuit board having the above structure
The semiconductor element 107 is bonded onto the top surface 2 by solder 108.
Further, the metal foil 103 and the conductive support substrate 101 made of metal are joined by the solder 106 containing lead and tin as main components. The supporting board on which the circuit board to which such a semiconductor element is bonded is mounted is housed in a sealed case as described later to form a semiconductor module. In this embodiment, the semiconductor element 107 and the support substrate 101 are insulated by the insulating plate 104. In this embodiment, the insulating capacitance component due to the insulating plate 104, that is, the insulating capacitance component 11 in the region 110 to be joined to the metal foil 102 is used.
2 (C _A2 ), in addition to the insulating capacitance component (C _A1 ) in the region 111 which is not joined, the metal foil 102 in the region 111
Insulation capacitance component 113 due to the space between the insulating plate 104 and the insulating plate 104
(Cd) occurs. C _A1 and C _A2 are connected in parallel by the metal foil 103, the conductor layer 109 and the metal brazing material 105, and Cd is connected in series to the parallel circuit by the conductor layer 109 and the metal brazing material 105. When the voltage 116 of V1 is applied to the module, the voltage (Vd) is applied to Cd if the circuit is simply a circuit in which Cd is serially connected to the parallel circuit of C _A1 and C _A2 . At this time, if the space forming Cd is an air layer or a vacuum layer, the dielectric constant is small, so V
d becomes large and partial discharge occurs. However, in this embodiment, Cd is short-circuited by the metal foil 102, the conductor layer 109 and the metal brazing material 105. Therefore,
Since Vd can be reduced, partial discharge can be suppressed.

FIG. 6 shows a cross section of a semiconductor module embodying the present invention.

In this embodiment, the structure of the circuit board shown in FIG. 1 is applied. However, the metal foil 102 is divided into two parts, each of which is bonded onto one insulating plate 104 by a metal brazing material 105. Then, a conductor layer 109 is formed in a region where the metal foil 102 and the insulating plate 104 are not joined. Metal foil 102 in this area
The electrode external lead-out terminals 202 each having a bend portion are joined by solder 201. The semiconductor element 107 is bonded to one (on the right side of the drawing) metal foil 102 by soldering. The semiconductor element 107 and the other (on the left side in the figure) metal foil 102 are wired by a metal wire 601 made of aluminum. The inside of the module is casing with a case 207 and a case lid 602, and the electrode external lead-out terminal 202 is fixed to the case lid with a bolt 603. Further, the electrode external lead terminal 202
The silicone gel 208 is filled up to the bend part to prevent deterioration between semiconductor elements and between wirings due to discharge and vibration of the metal wire 601. In addition, the silicone gel 20
The space 604 between the case 8 and the case lid 602 is filled with an epoxy hard resin for sealing, or the space between the case 207 and the case lid 602 is sealed as an air layer.

In the present embodiment, the case repeatedly expands and contracts due to the heat generated when the module operates and the surrounding environment (temperature change, etc.), and the electrode external lead terminal 202 moves up and down. However, in this embodiment, since the joint between the electrode external lead-out terminal 202 and the DBC substrate 117 is structured so as to be floated from the insulating plate 104, stress is relieved, and cracking of the insulating plate 104 and peeling of the bonding materials 105 and 201 are unlikely to occur. . Further, since the conductor film 109 is provided, even if the silicone gel 208 is not injected into the entire surface of the floating portion where the terminals are joined and the void 503 occurs, the partial discharge does not occur. However, if the silicone gel 208 is injected into the entire floating portion where the terminals are joined like the region 120, the insulating capacitance component of the silicone gel 208 can be made larger than the insulating capacitance component of the insulating plate 104. Therefore, even if there is a defect such as a pinhole in the conductor layer 109, partial discharge does not occur, double discharge prevention measures can be taken, and the defect rate can be greatly reduced.

FIG. 2 shows a sectional structure of a portion of the semiconductor device embodying the present invention to which the electrode external lead terminal is joined. (A) shows the case where the joining point of the electrode external lead terminal is located in the center of the metal foil, and (b) shows the case where it is located in the peripheral portion.

In any case, the metal foil 102 and the insulating plate 10
An insulating capacitance component is generated due to the space between 4 and 4. However, by forming the conductor layer 109 on the surface of the insulating plate 104 facing the metal foil 102, both ends of the insulating capacitance of the space are short-circuited to suppress partial discharge. The inside of the module is sealed with the case 207 and the support substrate 101 and filled with silicone gel 208. At this time, as shown in (b), a void 204 may occur in the space between the metal foil 102 and the insulating plate 104. Even when this void 204 spreads outside the end of the metal foil 102, the insulating capacitance component 20 due to the space layer
5 is generated and is connected in series with the insulating capacitance 206 by the insulating plate 104. In the example shown in (b), the conductor layer 1
09 extends to the outside of the end of the metal foil 102. That is, the position of the end of the conductor layer 109 is located between the end of the metal foil 102 and the end of the insulating plate 104. As a result, the insulating capacitance component 20 due to the void 204
Since 5 can also be short-circuited (115), the occurrence of partial discharge can be suppressed.

FIG. 3 shows an embodiment in which a conductor film layer is provided inside the insulating plate.

(A) shows a cross section of this embodiment. Insulation plate 1
The metal foils 102 and 103 are bonded to the upper and lower surfaces of the bonding material 04.
5, the metal layer 301 (second conductive layer) is formed in the insulating plate 104 so as to face the metal foil 102 (first conductive layer) on the semiconductor element mounting side. Then, the metal foil 102 and the metal layer 301 are disposed inside the insulating plate so that the insulating plate 1
Electrical connection is made by a conductor 302 arranged in a direction perpendicular to the surface of 04. At this time, the insulating capacitance component in the insulating plate 104 is changed by the metal layer 301 to the metal foil 102.
Side insulation capacitance component 303 and supporting substrate side insulation capacitance component 1
14, but the insulating capacitance component 303 is the metal foil 10.
2. Since it is short-circuited by the metal layer 301 and the conductor 302, the substantial insulating capacitance component is only 114.

Cases where the insulating plate 104 is deteriorated in this embodiment are shown in (b) and (c).

(B) is the case where peeling occurs at the interface between the bonding material 105 and the insulating plate 104. At this time, the peeling unit 30
An insulating capacitance component 305 is newly generated in the space portion of No. 4. The insulation capacitance component 305 is connected in series with the insulation capacitance component 303. However, since the insulating capacitance component 303 thus serially connected is short-circuited by the metal foil 102, the metal layer 301, and the conductor 302, partial discharge does not occur even in the peeled portion.

(C) is a case where a crack 308 occurs in the insulating plate 104. Area 307 where crack 308 occurred
Then, the insulation capacitance component 303 between the metal layer 301 and the metal foil 102 on the semiconductor element side is divided into three insulation capacitance components 309, 310, 311 connected in series by cracking. In particular, since the insulating capacitance component 310 is a space layer generated by cracking, there is a high possibility that partial discharge will occur at this location. However, since the insulating capacitance components thus connected in series are short-circuited by the metal foil 102, the metal layer 301 and the conductor 302, partial discharge does not occur.
In addition, in (c), the case where the crack is generated in the direction nearly parallel to the surface of the insulating plate is shown. However, even when the crack is generated in the direction perpendicular to the insulating plate, the partial discharge is similarly prevented.

The defects shown in (b) and (c) are generated near the metal foil 102 on the semiconductor element mounting side. However, in reality, the same deterioration may occur on the module supporting substrate side of the insulating plate 104. In this case, if a metal layer electrically connected to the metal foil 103 on the supporting substrate side is provided in the insulating plate 104, partial discharge can be prevented.

FIG. 4 is a view for explaining the dimensions of each part when the metal layer is formed in the insulating plate.

In order to secure insulation in the module, it is necessary to secure the thickness of the insulating plate 104 in the cross-sectional direction and the creepage distance of the insulating plate 104 in the lateral direction. Therefore, it is necessary to secure the creepage distance Lo according to the capacitance of the insulation from the module supporting board. However, since the dielectric strength in the insulating plate, that is, in the bulk is larger than that on the surface, the distance L1 between the end of the metal layer 301 in the insulating plate 104 and the end of the insulating plate 104 is equal to or larger than the thickness of the insulating plate 104. There are no insulation problems. For example, when the insulation capacitance with the module supporting board is 6 kV, Lo requires 6 mm in terms of the creepage distance of 1 mm / kV. However, L1 of 1 mm is sufficient inside the insulating plate. As a result, it is possible to widen the area where the insulating capacitance component 205 due to the void 204 of the silicone gel 208 filled in the module described in FIG. 2 can be widened, and the occurrence of partial discharge can be suppressed.

FIG. 5 shows an embodiment in which a metal foil is bonded onto a conductor layer provided on the surface of an insulating plate.

A metal brazing material 105 containing silver as a main component is used for joining the insulating plate 104 and the metal foils 102 and 103.
Since this brazing material is a hard brazing material, mechanical fatigue deterioration due to expansion and contraction of each part of the module during thermal cycling is relatively small. However, it is difficult to eliminate the sink mark 501 and the void 503 of the brazing material at the time of joining. When these defects are present in the module, the insulation capacitance components 502, 50
4 is a cause of partial discharge. In this embodiment, the dense conductor layer 10 with few defects is formed on the surface of the insulating plate 104.
By forming 9, the metal foil 102, the conductor layer 1
09 and the bonding material 105 between them can short-circuit the insulating capacitance component due to voids or sink marks of the bonding material. As a result, the occurrence of partial discharge can be suppressed.

FIG. 7 shows a cross section of a terminal connecting portion when the semiconductor module having the structure of FIG. 1 embodying the present invention is incorporated in an inverter device.

Each module is fixed to a cooling fin 709 by a bolt 708. A metal plate 702 fixed with bolts 603 is used for wiring between terminals of each module. A tensile stress 705 is applied to the electrode external lead-out terminal 202 due to the difference in height of the modules and the expansion and contraction of the case 207 and the case lid 602 due to the temperature rise and fall of the modules. On the other hand, generally, a curved portion (bend) is provided in a part of the electrode external lead terminal 202 to relieve the stress. As in the present embodiment, the electrode external lead-out terminal 2 is provided at a portion of the metal foil 102 that is not joined to the insulating plate 104.
If 02 is joined, not only can partial discharge be prevented,
The stress can be relieved by the bending of the metal foil 102. Therefore, the reliability of the joint between the electrode external lead-out terminal 202 and the metal foil 102 is improved, and the height of each module and the dimensional tolerance of the metal plate 702 are increased by adding a new stress relaxation structure. You can

In the above embodiments, in order to suppress the partial discharge more reliably, it is necessary to form the conductor layer so that defects such as pinholes and peeling do not occur. A vapor deposition method or metallization is suitable as a film forming method, but metallization is preferable in order to enhance adhesion between the insulating plate and the conductor layer in order to prevent peeling. But,
If there is no defect and the adhesion is good, the method is not limited to these. The material of the film is Au / Pt /
A laminated film such as Ti / AlN or Pt / Ti / AlN may be used, or a single film such as TiN may be used. Also, considering the adhesion with the insulating plate, W or M
Metallized films such as o-Mn alloys are preferred, but need not be limited to them. Furthermore, N on each metallized film
Defects such as pinholes can be eliminated by performing precise plating such as i.

The materials such as the insulating plate, the metal foil, and the bonding material are not limited to those described in each embodiment, but various insulating materials are used for the insulating plate, and various conductive materials are used for the metal foil and the bonding material. Can be used. Further, the insulating plate and the metal foil may be joined together by firing the metal foil while contacting the metal foil with the insulating plate, without using the metal brazing material. Further, the insulating plate may be directly bonded to the supporting substrate by a bonding material without attaching the metal foil to the surface of the insulating plate on the supporting substrate side.

Next, an embodiment of a power conversion device using the semiconductor device embodying the present invention will be described.

FIG. 8 shows a main circuit of an embodiment of an inverter device using a semiconductor module to which the present invention is applied.
The present embodiment is a series multiple inverter device, which is a so-called neutral point clamp type three-layer inverter device.

In this inverter device, a pair of DC terminals 4
43 and 444, and three AC terminals 457 to 459 equal to the number of phases, a DC power source is connected to the DC terminal,
By switching the IGBTs 470 to 481, DC power is converted into AC power and output to the AC terminal. Filter capacitors 460 and 46 connected in series are connected between the DC terminals.
1 is connected. IGBT pairs 470 and 471,472
, 473, 474, 475, 476 and 477, 478 and 479, 480 and 481 are respectively connected in series,
Each connection point and filter capacitors 460 and 46
Clamp diodes 494 to 49 between the connection point of 1 and
9 is connected. Two sets of IGBTs, for example, a set of IGBTs 470 and 471 and a set of IGBTs 476 and 477 connected in series, are further connected in series, and both ends thereof are connected between DC terminals. Further, the AC terminal is taken out from the connection point of the two IGBT groups. The IGBTs 470 to 481 are respectively connected in reverse parallel with diodes 482 to 493 for circulating a load current.

Here, a set of an IGBT and a diode connected in anti-parallel, for example, an IGBT470 and a diode 482, is housed in one module. Each module has the structure shown in FIG. 6, and one IGBT and one diode are bonded onto the metal foil. The metal foil is patterned so as to form a circuit wiring for connecting the IGBT and the diode in antiparallel.

In this embodiment, the IG by partial discharge is used.
Since the malfunction of the BT can be prevented, the reliability of the inverter device can be improved. In particular, in a module of a voltage control type switching element such as an IGBT, the control signal is small, so that the effect is large. In addition, since noise due to partial discharge occurs in the low frequency region, in addition to the module control signal, transmission of communication systems close to the periphery of the inverter,
There is also an effect that the influence on the receiving system and the like can be suppressed.

FIG. 9 shows a main circuit of another embodiment of an inverter device using a semiconductor module to which the present invention is applied. This inverter device is also provided with a pair of DC terminals 543 and 544 and three AC terminals 557 to 559 having the same number of phases as in the previous embodiment. A DC power supply is connected to the DC terminals to switch the IGBTs 545 to 550. As a result, the DC power is converted into AC power and output to the AC terminal. A series of IGBTs 54 connected in series between the DC terminals.
Both ends of 5 and 546, 547 and 548, 549 and 550 are connected. Two IGBTs in each IGBT set
An AC terminal is taken out from the series connection point of. Also,
A diode for circulating a load current is connected in antiparallel to each IGBT. Also in this embodiment, one set of the IGBT and the diode connected in antiparallel is housed in one module. This embodiment also has the same effects as the inverter device of the previous embodiment.

In the inverter device of the above embodiment,
Although the IGBT is used as the switching element, the IGBT
However, other switching such as GTO, transistor, MOSFET, etc. may be used. Further, the configuration of the module is not limited to that of the above inverter device, and a plurality of switching elements and a plurality of diodes may be accommodated in one module.

[0042]

According to the present invention, it is possible to suppress the occurrence of partial discharge inside the module and prevent defective insulation deterioration of the module. Further, by suppressing the generation of noise due to partial discharge, malfunction of the semiconductor device can be prevented.

[Brief description of drawings]

FIG. 1 shows a part of a semiconductor device according to an embodiment of the present invention, in which a circuit board having a conductor layer provided around a metal foil is mounted.

FIG. 2 shows a cross-sectional structure of a portion of the semiconductor device embodying the present invention to which an electrode external lead terminal is joined.

FIG. 3 shows an embodiment in which a conductor film layer is provided inside an insulating plate.

FIG. 4 is a diagram illustrating the dimensions of each part when a metal layer is formed in an insulating plate.

FIG. 5 is an example in which a metal foil is bonded onto a conductor layer provided on the surface of an insulating plate.

FIG. 6 shows a cross section of a semiconductor module embodying the present invention.

FIG. 7 shows a cross section of a terminal connecting portion when the semiconductor module having the configuration of FIG. 1 according to the present invention is incorporated in an inverter device.

FIG. 8 shows a main circuit of an embodiment of an inverter device using a semiconductor module to which the present invention is applied.

FIG. 9 shows a main circuit of another embodiment of an inverter device using a semiconductor module to which the present invention is applied.

[Explanation of symbols]

101 ... Support substrate, 102, 103 ... Metal foil, 104 ...
Insulating plate, 105 ... Metal brazing material, 106, 108, 201
... solder, 107 ... semiconductor element, 109 ... conductor layer, 1
17 ... DBC substrate, 202 ... Electrode external extraction terminal, 2
07 ... Case, 208 ... Silicone gel, 301 ... Metal layer, 302 ... Conductor, 601 ... Metal wire, 602 ... Case lid, 603, 708 ... Bolt, 702 ... Metal plate,
709 ... Cooling fin.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ryuichi Saito 7-1-1, Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory (72) Inventor, Koji Yamada 7-chome, Omika-cho, Hitachi No. 1-1 Hitachi, Ltd. Hitachi Research Laboratory (72) Inventor Yutaka Higashimura 7-1, 1-1 Omika-cho, Hitachi City, Ibaraki Prefecture Hitachi Ltd. Hitachi Research Laboratory (72) Inventor Yasutoshi Kurihara Hitachi, Ibaraki Prefecture No. 1-1 Omika-cho, Oita-shi, Hitachi Co., Ltd. Hitachi Research Laboratory

Claims (10)

[Claims] 1. An insulating plate, a first conductive layer provided on one surface of the insulating plate, a second conductive layer provided at a position facing the first conductive layer of the insulating plate, and a first conductive layer. And a conductor that electrically connects the second conductive layer. 2. The circuit board according to claim 1, further comprising a dielectric material interposed between the first conductive layer and the second conductive layer. 3. The position of the end of the second conductive layer is the position of the end of the first conductive layer, or the end of the first conductive layer and the end of the insulating plate. A circuit board which is located between the parts. 4. The first conductive layer according to claim 1, wherein
A circuit board comprising a metallized layer of tungsten, a metallized layer containing molybdenum and manganese, a layer plated with a metallized layer of tungsten, or a layer plated with a metallized layer containing molybdenum and manganese. 5. An insulating plate, a first conductive layer provided on one surface of the insulating plate, a second conductive layer provided on the insulating plate away from the first conductive layer, and a first conductive layer. And a conductor electrically connecting the second conductive layer, the circuit board. 6. An insulating plate, a first conductive layer provided on one surface of the insulating plate, a second conductive layer provided at a position facing the first conductive layer of the insulating plate, and a first conductive layer. A circuit board having a conductor electrically connecting the layer and the second conductive layer, a semiconductor element bonded to the first conductive layer of the circuit board, and the other surface of the insulating plate of the circuit board A conductive substrate, and a semiconductor device. 7. The semiconductor device according to claim 6, wherein an electrode terminal is provided on the first conductive layer. 8. An insulating plate, a first conductive layer provided on one surface of the insulating plate, a second conductive layer provided on the insulating plate away from the first conductive layer, and a first conductive layer. A circuit board having a conductor electrically connecting the second conductive layer, a semiconductor element bonded to the first conductive layer of the circuit board, and a conductivity bonded to the other surface of the insulating plate of the circuit board. And a substrate of. 9. A power inverter device using the semiconductor device according to claim 6. 10. A power inverter device using the semiconductor device according to claim 8.