JPH0818409A - Waveform generator with frequency sweep function - Google Patents

Abstract

PURPOSE:To provide a waveform generator capable of performing highly accurate and highly stable frequency conversion and frequency sweep. CONSTITUTION:This generator is provided with a first address generator 10 for generating address signals which change corresponding to frequency data, a waveform memory 6 storing waveform data constituted so as to the contents (waveform data) of a specified address from the first address generator 10 be read out, a DA converter 7 for analog-converting the output data of the waveform memory 6 and a frequency information memory 3 storing optional sweep data constituted so as to the frequency data stored in the specified address be read out when the address from a means for generating the address signals which change by a prescribed ratio or an AD converter 1 for digitalconverting external input signals is specified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform generator with a frequency sweep function capable of generating an arbitrary waveform and performing a high-precision and wide-band frequency sweep.

[0002]

2. Description of the Related Art A function generator for generating a variable frequency signal has been well known. This function generator has a circuit for performing voltage-frequency conversion therein, but most of it is of an analog type.

FIG. 3 shows an example of a voltage-frequency conversion circuit utilizing charge / discharge of a capacitor. When the voltage e ₁ is applied to the input end, the output e ₀ of the amplifier A rises as shown by the ramp circuit composed of the input resistor R, the capacitor C and the amplifier A. When this output exceeds the Zener voltage (reference voltage e _r : +6.3 V here) determined by the Zener diode Z, the output of the comparator B becomes HI.
It becomes the GH level, which causes the output of the flip-flop D to become the HIGH level.

When the output of the flip-flop D becomes HIGH level, the transistor E is turned on and the electric charge charged in the capacitor C is discharged. As a result, the output voltage of the amplifier A drops to 0V, and the output of the comparator B becomes L.
It becomes OW level, and the output of flip-flop D is also LOW.
Become a level. In response to this, the transistor E is turned off.

By repeating the above operation, a signal of frequency F ₀ corresponding to the input voltage e ₁ is obtained from the flip-flop D. The frequency F _{0 at} this time is F ₀ = 1 / {(e ₁ / e _r ) · R · C}. Then, the frequency of the output signal can be swept by sweeping the input voltage e ₁ . In addition,
This voltage-frequency conversion circuit outputs only a pulse train waveform, but by adding a circuit that converts to a triangular wave or sine wave, a triangular wave or sine wave can be obtained at the same time, and a function generator that can also perform frequency sweep can be configured. it can.

[0006]

However, in such a conventional voltage / frequency conversion circuit, there is a problem in that the stability of each element with respect to temperature is poor and the operation speed is very slow. .

In view of the above points, an object of the present invention is to realize a waveform generator capable of highly accurate and highly stable frequency conversion and frequency sweep by using a circuit mainly handling digital data instead of an analog method. It is in.

[0008]

In order to achieve such an object, according to the present invention, a first address generator that generates an address signal that changes in accordance with frequency data, and waveform data are stored. The waveform memory configured to read the content (waveform data) of the specified address from the address generator No. 1, a DA converter for converting the output data of the waveform memory into an analog signal, and arbitrary sweep data are stored. When an address from a means for generating an address signal that changes at a rate of or an AD converter for digitally converting an external input signal is designated,
A frequency information memory configured to read the frequency data stored at the designated address is provided.

[0009]

The waveform data is read from the waveform memory by the address generated from the first address generator, and D
It is output as an analog waveform via the A converter. The frequency of the output analog waveform changes according to the frequency data given to the first address generator. The frequency data is stored in the frequency information memory. The frequency sweep of the analog waveform can be performed by changing the address given to the frequency information memory and changing the read frequency data. The address for the frequency information memory is given by the second address generator or an AD converter for AD converting an external signal input.

[0010]

The present invention will be described in detail below with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of a waveform generator with a frequency sweep function according to the present invention. In the figure, 1 is an analog / digital converter for converting an external input signal (analog signal) into a digital signal (hereinafter, analog / digital conversion is referred to as AD
2 is a switch, 3 is a frequency information memory in which frequency information is stored, 4 is a clock oscillator that generates a reference clock, 5 is a frequency divider that divides the reference clock, and 6
Is a waveform memory in which waveform data is stored, 7 is a digital-analog converter for converting the waveform data read from the waveform memory 6 into analog (hereinafter digital-analog conversion is referred to as DA conversion), 8 is frequency information memory 3 and A control arithmetic circuit for writing data to the waveform memory 6 and the like, 10 is a first address generator for generating an address for the waveform memory 6, and 20 is a second address generator for generating an address for the frequency information memory 3. Is.

The AD converter 1 AD-converts the external input signal in synchronization with the clock given from the frequency divider 5. The frequency divider 5 appropriately divides the clock generated by the clock oscillator 4. The output of the AD converter 1 and the output of the second address generator 20 are selectively selected by the switch 2 and serve as a read address for the frequency information memory 3. Frequency data is stored in the frequency memory 3 in advance.

The first address generator 10 receives the frequency data (M) from the frequency information memory 3 and generates data increasing by M as an address for the waveform memory 6. The waveform memory 6 outputs the content (waveform data) of the designated address. This data is DA converter 7
And is DA converted.

The configuration of the first address generator 10 will be described. The second address generator 2
Since 0 also has the same configuration as the first address generator 10, the configuration of the second address generator 20 will not be described again. First address generator 10
In the figure, 11 is an adder and 12 is a latch. The output of the adder 11 is input to the latch 12, and the output of the latch 12 is returned to the adder 11 again. The adder 11 adds the frequency data M and the output of the latch 12. The latch 12 latches the input signal in synchronization with the clock of the clock oscillator 4. As a result, the latch 12 generates an address that increases by M each time a clock pulse is input.

The operation in such a configuration will be described below. In FIG. 1, a first address generator 10,
A portion including the waveform memory 6 and the DA converter 7 is a waveform generating circuit portion called a direct digital synthesizer (DDS) system. In this portion, the time of one cycle of the output waveform (in other words, the frequency) can be changed by changing the frequency data M. The circuit portion for changing the frequency data is a portion including the AD converter 1, the switch 2, the second address generator 20, and the frequency information memory 3.

(1) First, the case where the output of the second address generator 20 is selected by the switch 2 will be described. While the first address generator 10 and the waveform memory 6 determine the time of one cycle of the output waveform, the second address generator 20 and the frequency information memory 3 are the time of one cycle of the frequency data, that is, the sweep time. Is what determines. Second address generator 20
When the total time N of the second address generator 20 is input, N, 2N, 3N ,. ． ． Is output, and the address of the frequency information memory 3 is sequentially updated. When the linear data is stored in the frequency information memory 3, the output frequency data changes linearly.

For convenience of explanation, it is assumed that the addresses of the frequency information memory 3 are from A to 9A and that the linear data is stored therein. When N = A, the frequency data is repeated every 9 clocks as shown in FIG. When N = 3A, as shown in FIG.
Frequency data is repeated for each clock. Therefore, the sweep time can be changed by changing the total time N. The accuracy of the sweep time depends on the clock, and is not affected by variations in other elements.

(2) Next, the AD converter 1 with the switch 2
The case where the output of is selected will be described. Since the AD-converted value of the external input signal becomes the address value of the frequency information memory 3, the sweep time is determined by the voltage value given as the external input. This AD converter 1 plays the same role as the second address generator 20. Although the input value is an analog amount, it is processed by digital data in the internal circuit of the present invention. The sweep by the external input signal depends on the performance of the AD converter 1.
Many converters operate at speeds of 100 KHz and above, thus allowing wideband frequency sweeps.

The data stored in the frequency information memory 3 is not limited to linear data, and may be logarithmically changing data. In that case, a log sweep output is obtained from the waveform generating circuit of the present invention. Further, desired waveform data can be written in the waveform memory 6 as appropriate, and various waveform data such as a square wave, a triangular wave, and a sine wave can be stored according to the purpose. The control operation circuit 8 writes data in the frequency information memory 3 and the waveform memory 6.

[0019]

As described above, according to the present invention, various frequency sweeps can be easily realized by changing the data stored in the frequency information memory. Further, since it is configured by a digital circuit, the accuracy of the sweep time depends only on the clock used and is not affected by the variation of other elements, and stable frequency sweep can be easily realized. Further, in the sweep by the external input signal, the sweep speed depends on the performance of the AD converter.
There are many ADs that operate at high speeds of KHz or higher, and wideband frequency sweeps can be easily realized.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a waveform generator with a frequency sweep function according to the present invention.

FIG. 2 is an explanatory diagram of frequency data read from a frequency information memory.

FIG. 3 is a configuration diagram showing an example of a conventional voltage-frequency conversion circuit.

[Explanation of symbols]

 1 AD Converter 2 Switch 3 Frequency Information Memory 4 Clock Oscillator 5 Frequency Divider 6 Waveform Memory 7 DA Converter 8 Control Arithmetic Circuit 10 First Address Generator 11 Adder 12 Latch 20 Second Address Generator

Claims (1)

[Claims] 1. A first signal generator for generating an address signal, which changes corresponding to frequency data inputted, in synchronization with a reference clock.
Address generator, waveform data is stored, and when the address is designated from the first address generator, the waveform data stored at the address is read out, and output data of the waveform memory When an address is designated by a DA converter for analog-converting data, a means for generating an address signal that stores arbitrary sweep data and changes at a predetermined ratio, or an AD converter for digitally converting an external input signal, the designation is performed. A frequency information memory configured to read the frequency data stored at the address;
A waveform generator with a frequency sweep function, characterized in that a waveform swept in frequency is obtained from the DA converter.