JPH08181724A - Time-division two-way communication equipment - Google Patents

Abstract

PURPOSE: To obtain a time division 2-way communication equipment in which a deviation of an oscillated frequency of a VCO is minimized independently of an active/inactive state of a preamplifier and a power amplifier. CONSTITUTION: The communication equipment is provided with a digital signal source 4 outputting a digital signal for a transmission time slot period at a low output resistance and indicating a high output resistance higher than the low output resistance for a blind slot period just before the transmission time slot, a bias application means 16 applying a bias voltage to an output terminal of the digital signal source 4, A VCO 1 outputting the oscillation signal with a prescribed transmission frequency for the blind slot period and outputting a modulated signal modulated based on the output of the digital signal source 4 for the transmission time slot period, an IC 2 outputting an error signal representing a phase difference between the oscillated signal and a reference frequency signal for the blind slot period and invalidating the error signal substantially for the transmission time slot period, and a low pass filter 3 smoothing an error signal fed to the VCO 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time division two-way communication device, and more particularly to a reference value of an oscillation frequency of a voltage controlled oscillator (VCO) in a blind slot immediately before a transmission time slot (hereinafter referred to as a transmission slot). And a reference value of the same oscillation frequency in the transmission slot are made substantially equal to each other to suppress the frequency deviation of the transmission frequency.

[0002]

2. Description of the Related Art In a time division two-way (TDD) communication system, a blind slot is provided immediately before a transmission slot. In this blind slot, the signal is neither transmitted nor received, but is prepared for transmission.

Here, FIG. 4 is a block diagram showing a configuration of a transmitting section in a transceiver of a known time division two-way communication device.

As shown in FIG. 4, the transmission section is roughly divided into a phase control section, a modulation signal supply section, a transmission signal output section, and a voltage adjustment section. Among these, the phase control unit includes a voltage controlled oscillator (VCO) 31 and an IC for phase control.
32 and a low pass filter (LPF) 33,
The output terminal O of CO31 is input to IC32, the output of IC32 is input to LPF33, and the output of LPF33 is VCO.
31 error signal input terminals I _E , respectively. Here, the IC 32 is provided with a frequency divider, a phase comparator, a charge pump, etc., and is, for example, UMA1018 manufactured by Philip Company. The modulation signal supply unit includes a digital signal source 34, a waveform shaping circuit 35, and a Gaussian filter (GF) 36.
Output to the input of the waveform shaping circuit 35,
Output is input to GF36 and output of GF36 is VCO3
They are respectively connected to the first modulation signal input terminal I _M.
The transmission signal output section includes a buffer amplifier 37, a preamplifier 38, a power amplifier 39, and a transmission / reception changeover switch 40.
, Bandpass filter (BPF) 41, and antenna 4
2 and the output terminal O of the VCO 31 is input to the buffer amplifier 37, the output of the buffer amplifier 37 is input to the preamplifier 38, and the output of the preamplifier 38 is the power amplifier 3.
9, the output of the power amplifier 39 is connected to one fixed contact of the transmission / reception changeover switch 40, the movable contact of the transmission / reception changeover switch 40 is connected to one terminal of the BPF 41, and the other terminal of the BPF 41 is connected to the antenna 42. There is. The voltage regulator includes a voltage regulator (REG) 43, a first power switch 44, and a second power switch 45,
The input of REG43 is the power supply Vcc, the output of REG43 is VCO31, IC32, waveform shaping circuit 35, GF36,
The movable contact of the first power switch 44 is connected to the power supply Vcc, the fixed contact of the first power switch 44 is connected to the power supply terminal of the preamplifier 38, and the second power switch 45 is moved to each power supply terminal of the buffer amplifier 37. The contact is connected to the power supply Vcc, and the fixed contact of the second power switch 45 is connected to the power supply terminal of the power amplifier 39.

Further, the IC 32 has a reference clock signal (REF CLK) and a PLL clock signal (PLL C
LK), PLL data signal (PLL DATA), PL
An L strobe signal (PLL STB) and a PLL power cutoff signal (PLL PWR DWN) are respectively supplied.
The transmission enable signal (TX ENB) is supplied to the control terminal of the first power switch 44, and the amplifier start-up signal (PA RU) is supplied to the control terminal of the second power switch 45.
MP) is supplied.

Next, FIGS. 5 (a) to 5 (g) are explanatory views showing the temporal displacement state of the signal waveform of each part in the transmission part of the known transceiver having the above-mentioned structure, and FIG. Signal (TX ENB), (b) PLL
A power-off signal (PLL PWRDWN), (c) an amplifier start-up signal (PA RUMP), (d) a digital signal (TX DATA), and (e) a waveform shaping circuit 3.
5 is a signal waveform diagram showing the output signal of FIG. 5, (f) is the output signal (modulation signal) f _T of the Gaussian filter 36, and (g) is an explanatory diagram showing the oscillation frequency deviation of the VCO 31.

In FIG. 5, the vertical axis represents the amplitude or frequency deviation of each signal, and the horizontal axis represents time. in this case,
Times t1 to t4 are periods of blind slots,
Times t4 to t11 are transmission slot periods.

Here, the outline of the operation executed by the transmitting unit of a known transceiver will be described with reference to FIGS. 5 (a) to 5 (g).

First, at time t1, a blind slot period starts. At this time, the transmission enable signal (T
X ENB) is at a high level indicating an inactive state, and the amplifier start-up signal (PA RUMP) is at a low level indicating an inactive state. The contacts of the first power switch 44 and the second power switch 45 are All are open, the PLL power cutoff signal (PLL PWR DWN) is at a low level, the phase control unit including the VCO 31, the IC 32, and the low-pass filter 33 has an open control loop and a digital signal (TX DATA) is in the intermediate level reference voltage state, and no signal is applied to the VCO 31. Although the VCO 31 oscillates a signal, its oscillation frequency does not match the reference oscillation frequency f _T.

Next, at time t2, the PLL power-off signal (PLL PWR DWN) changes to high level, and the control loop of the phase controller is closed. The frequency of the oscillation signal of the VCO 31 is the reference oscillation frequency f at time t2.
_Even if it deviates from _T , the phase is controlled by the phase control unit and converges to the reference oscillation frequency f _T with zero frequency deviation within a short time. The oscillation signal obtained by the VCO 31 is
It is supplied to the preamplifier 38 side via the buffer amplifier 37, but since the contacts of the first power switch 44 and the second power switch 45 are open, the preamplifier 38 and the power amplifier 39 are inactive. In this state, the oscillation signal is blocked by the preamplifier 38 and the power amplifier 39, and is not transmitted from the antenna 42.

Then, at time t3, the PLL power-off signal (PLL PWR DWN) returns to the low level,
In the phase control unit, the control loop is opened again. At this time, the VCO 31 continues to oscillate at the reference oscillation frequency f _T by the control voltage held by the LPF 33. The reason why the control loop is opened at this point is to prevent the modulation operation from being disturbed by the PLL control during the transmission time slot period and to reduce the power consumption.

At time t4, the blind slot period ends and the transmission slot period begins. However, until the time t5, the operation during the period from the time t3 to the time t4 is continued as it is.

Next, at time t5, the transmission enable signal (TX ENB) changes to the low level indicating the active state, the contact of the first power switch 44 is closed, and the preamplifier 38 is activated. At this time, VCO31
The oscillated signal obtained in step (1) is supplied to the power amplifier 39 via the buffer amplifier 37 and the preamplifier 38. However, since the power amplifier 39 is still in the inactive state, the oscillated signal is blocked by the power amplifier 39. It is not transmitted from the antenna 42.

Subsequently, at time t6, the amplifier start-up signal (PA RUMP) changes to the high level indicating the active state, the contact point of the second power switch 45 is closed, and the power amplifier 39 is activated.

At the subsequent time t7, the digital signal source 34 outputs the digital signal (T) as shown in FIG.
X DATA) is generated and its digital signal (TX
DATA) is shaped into a square wave signal as shown in FIG. 5E in the waveform shaping circuit 35, and then GF3
6, it is converted into a sinusoidal modulation signal S _M as shown in FIG. 5 (f) and supplied to the modulation signal input terminal I _M of the VCO 31. The VCO 31 modulates the oscillation signal by frequency shift keying (GFSK) by supplying the modulation signal S _M , and generates the GFSK modulation signal as shown in FIG. 5 (g). This GFSK modulated signal is supplied to the buffer amplifier 3
7, preamplifier 38, power amplifier 39, transmission / reception changeover switch 40 whose movable contact is switched to the transmission side, BPF
The signal is supplied to the antenna 42 via 41 and transmitted from the antenna 42.

Next, at time t8, the digital signal source 34 stops generating the digital signal (TXDATA) and enters the intermediate level reference voltage state. At this time, V
The supply of the modulation signal S _{M to} the CO31 is stopped, and the VCO3
1 stops the generation of the GFSK modulated signal and instead generates an unmodulated oscillating signal.

Then, at time t9, the amplifier start-up signal (PA RUMP) changes to the low level indicating the inactive state, and the contact of the second power switch 45 opens.
The power amplifier 39 switches to the inactive state. At this time, V
The oscillation signal obtained at the CO 31 is blocked by the power amplifier 39 in the inactive state, and the transmission from the antenna 42 is stopped.

Next, at time t10, the transmission enable signal (TX ENB) changes to the low level indicating the inactive state, the contact of the first power switch 44 is opened, and the preamplifier 38 is deactivated. . At this time, V
The oscillation frequency f _T obtained at the CO 31 is blocked by the pre-amplifier 38 and the power amplifier 39 in the inactive state, and is not transmitted from the antenna 42.

Then, at time t11, the period of the transmission slot ends, the period of the subsequent receiving slot and the like elapses, and then the period of the next blind slot is entered again, and the above-described operation is repeatedly executed.

FIG. 6 is a circuit configuration diagram showing an example of the configuration of the VCO 31 in the transmission section of the known transceiver, and FIG. 7 shows the configuration of the waveform shaping circuit 35 in the transmission section of the known transceiver. It is a circuit block diagram which shows an example.

As shown in FIG. 6, the VCO 31 includes a transistor 53 that forms a Colpitts oscillation circuit together with other circuit elements, and a resonance line 54 that sets the oscillation frequency.
And a variable capacitance diode 55 for appropriately shifting the oscillation frequency by supplying the modulation signal S _M and the error voltage V _E. Further, as shown in FIG. 7, the waveform shaping circuit 35 includes an integrated circuit (IC) 47 for inverter, an input resistor 48, a feedback resistor 49, an output resistor 50, and bias resistors 51 and 52. There is.

The VCO 31 and the waveform shaping circuit 35 according to the above-mentioned configuration operate as follows.

First, the operation of the VCO 31 will be described. The digital signal source 34 operates as a digital signal (TX D
ATA) is stopped and the modulation signal input terminal I _M
If the modulation signal S _M is not supplied to the input terminal, the control loop of the phase control unit is open, and the error signal S _E is not supplied to the error signal input terminal I _E , the VCO 31 determines that the LPF 33
Of the reference oscillation frequency f _T set by the control voltage held at the circuit and the circuit constants of the resonance line 54 and other circuit elements in the vicinity thereof.
It oscillates at a frequency close to, and the oscillation signal is supplied to the subsequent buffer amplifier 37. At this time, when the control loop of the phase control unit is closed and the error signal S _E is supplied to the VCO 31, the oscillation frequency of the VCO 31 is controlled by this error signal S _E , and the VCO 31 matches the reference oscillation frequency f _T. It oscillates at the frequency, and the oscillation frequency signal is supplied to the subsequent buffer amplifier 37. In addition, the digital signal source 3
4 becomes to generate a digital signal (TX DATA), and the modulation signal S _M is supplied to the modulation signal input terminal I _M , the reference oscillation frequency f _{T of the} VCO 31 is GFSK-modulated by the modulation signal S _M. Generates a modulated signal and outputs this GF
The SK modulated signal is supplied to the next buffer amplifier 37.

Next, the operation of the waveform shaping circuit 35 will be described. The digital signal (TX DATA) supplied from the digital signal source 34 to the input terminal I is inverted and amplified in the inverter IC 47 in a high gain and supersaturated state, and thus is squared. Wave signal, and this square wave signal is output from output terminal O to the next G
It is supplied to F36.

[0025]

The transmitter of the known transceiver has a preamplifier 3 on the output side of the VCO 31.
8 is connected via the buffer amplifier 37,
V depending on the state of the input impedance of the preamplifier 38
The output load state of the CO 31 changes, and the oscillation frequency of the VCO 31 slightly changes. That is, when the preamplifier 38 is in the inactive state, its output impedance is high and VC
Although the output load of O31 is also in a relatively high impedance state, when the preamplifier 38 changes to the active state at time t5 shown in FIG. The output load is also in a relatively low impedance state, and the oscillation frequency of the VCO 31 shifts from the reference oscillation frequency f _T to the higher side by the _first frequency deviation Δf ₁ as shown in FIG. 5 (g). .

In the transmitter of the known transmitter / receiver, the power consumption of the power amplifier 39 is large, and the power supply voltage Vcc varies depending on whether the power amplifier 39 is in the driving state or in the non-driving state. Have a big impact. That is, when the power amplifier 39 is in the non-driving state, V
Assuming that the power supply voltage Vcc supplied to the CO 31 has a predetermined voltage value, when the power amplifier 39 changes to the active state at the time t6 shown in FIG. 5, the power supply voltage Vcc supplied to the VCO 31 slightly decreases. And along with that, VCO
As shown in FIG. 5 (g), the oscillation frequency of 31 shifts from the reference oscillation frequency f _T to the higher side by the _second frequency deviation Δf ₂ in addition to the _first frequency deviation Δf _1. .

If the preamplifier 38 changes to the inactive state when the oscillation frequency of the VCO 31 is deviated by the first frequency deviation Δf ₁ , the first frequency deviation Δf ₁ is changed. Even when the second frequency deviation Δf ₂ is generated, if the power amplifier 39 changes to the inactive state, the second frequency deviation Δf ₂ disappears and both return to the original oscillation frequency. Is.

As described above, the transmitter of the known transceiver has a change in the input impedance based on the active and inactive states of the preamplifier 38 and a power supply voltage Vcc based on the active and inactive states of the power amplifier 39. The oscillation frequency of the VCO 31 changes due to the change of, and there is a problem that the change width changes about ± 20 kHz at maximum when the reference oscillation frequency f _T is 1.9 GHz.

The present invention eliminates the above problems.
An object of the present invention is to provide a time division two-way communication device in which the deviation of the oscillation frequency of a voltage controlled oscillator (VCO) is minimized regardless of the active / inactive state of the preamplifier and the active / inactive state of the power amplifier. Especially.

[0030]

In order to achieve the above object, the present invention outputs a digital signal in a transmission time slot period and exhibits a low output resistance value, and in the blind slot period immediately before the transmission time slot, A digital signal source exhibiting a high output resistance value higher than a low output resistance value, bias supply means for applying a bias voltage to the output terminal of the digital signal source through a resistor, and an oscillation signal of a predetermined transmission frequency during a blind slot period. And a voltage-controlled oscillator that outputs a modulated signal that is modulated based on the output of the digital signal source during a transmission time slot period, and a phase difference between the oscillation signal and a reference frequency signal during the blind slot period. Output an error signal and substantially disable the error signal during the transmission time slot period. A phase control circuit that includes means and a low pass filter for smoothing the error signal applied to said voltage controlled oscillator.

[0031]

In the above means, the bias supply means for supplying the bias voltage to the output terminal of the digital signal source through the resistor is provided so that a predetermined bias voltage is applied to the output terminal of the digital signal source. In this case, since the digital signal source does not generate a digital signal and the output impedance of the digital signal source is high during the blind slot period, the voltage at the output terminal of the digital signal source is supplied from the bias supply means. It is set by the bias voltage. On the other hand, during the period of the transmission slot, the digital signal source generates a digital signal, and the output impedance of the digital signal source becomes low. Therefore, the bias voltage supplied from the bias supply means is short-circuited and invalidated at this low output impedance, The voltage at the output terminal of the digital signal source is set by the digital signal. That is, the voltage of the output terminal of the digital signal source is set to be slightly different between the blind slot period and the transmission time slot period,
The center voltage of the modulation signal supplied to the voltage controlled oscillator (VCO) has a slightly different value.

As described above, according to the above means, at the time of switching from the blind slot to the transmission time slot,
Since the center voltage is slightly shifted and the modulation signal is supplied to the VCO, the fluctuation of the oscillation frequency of the VCO due to the switching of the preamplifier and the power amplifier from the inactive state to the active state is canceled and the VCO is obtained. The center frequency of the GFSK modulated signal substantially matches the reference oscillation frequency, and the deviation of the oscillation frequency of the VCO can be minimized, and a high-performance time division two-way communication device having a highly accurate transmission frequency can be obtained. be able to.

[0033]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the time division two-way communication device according to the present invention, and shows the constitution of the transmission section in the transceiver of the time division two-way communication device.

Now, comparing the structural differences between the transmitter of this embodiment and the known transmitter shown in FIG. 4,
In the transmitter of this embodiment, the bias supply circuit (bias supply means) 16 is connected to the output terminal of the digital signal source, whereas the known transmitter is only connected to the bias supply circuit. However, in order to clarify the configuration of the transmission unit of the present embodiment, the configuration of the transmission unit of the present embodiment will be described as a whole, including the same portions as the configurations of known transmission units.

As shown in FIG. 1, the transmitting unit is roughly classified into
A phase control unit, a modulation signal supply unit, a transmission signal output unit,
It consists of a voltage regulator. Among them, the phase control unit includes a voltage controlled oscillator (VCO) 1 and a phase control IC 2
And a low-pass filter (LPF) 3, and VCO3
The output terminal O of 1 is the input of IC2, and the output of IC2 is LP
The output of LPF3 is connected to the input of F3, and is connected to the error signal input terminal I _E of VCO1. In addition, IC2
Is the same as the IC 32 used in the known transmitting unit shown in FIG. The modulation signal supply unit includes a digital signal source 4, a bias supply circuit 16, a waveform shaping circuit 5, and a Gaussian filter (GF) 6, and the output of the digital signal source 34 is waveform-shaped via the bias supply circuit 16. The output of the waveform shaping circuit 5 is input to the shaping circuit 5, the output of the GF6 is input to the modulation signal input terminal I _{M of the} VCO 1.
Respectively connected to. The transmission signal output unit includes a buffer amplifier 7, a preamplifier 8, a power amplifier 9, a transmission / reception changeover switch 10, and a bandpass filter (BPF).
11 and an antenna 12, the output terminal O of the VCO 1 is input to the buffer amplifier 7, the output of the buffer amplifier 7 is input to the preamplifier 8, and the output of the preamplifier 8 is input to the power amplifier 9. The output of the power amplifier 9 is connected to one fixed contact of the transmission / reception changeover switch 10 and the transmission / reception changeover switch 1
The moving contact of 0 is connected to one terminal of the BPF11 by the BPF11.
The other terminals of are connected to the antenna 12, respectively. The voltage regulator includes a voltage regulator (REG) 13 and a first regulator.
Power supply switch 14 and second power supply switch 15, and the input of REG 13 is the power supply Vcc, and the output of REG 13 is VCO 1, IC 2, the waveform shaping circuit 5, GF 6, the buffer amplifier 7, and the bias supply circuit 16. The movable contact of the first power switch 14 is connected to the terminal with the power supply Vcc.
The fixed contact of the first power switch 14 is connected to the preamplifier 8
The movable contact of the second power supply switch 15 is connected to the power supply Vcc, the fixed contact of the second power supply switch 15 is connected to the power supply terminal of the power amplifier 9, respectively.

Further, the reference clock signal (R
EF CLK), PLL clock signal (PLL CL
K), PLL data signal (PLL DATA), PLL
A strobe signal (PLL STB) and a PLL power cutoff signal (PLL PWR DWN) are respectively supplied. The transmission enable signal (TX ENB) is supplied to the control terminal of the first power switch 14, and the amplifier start-up signal (PA RUM) is supplied to the control terminal of the second power switch 15.
P) is supplied.

FIG. 2 is a circuit diagram showing an example of the configuration of the bias voltage supply circuit 16 used in this embodiment, and is shown together with the circuit configuration of the waveform shaping circuit 5.

As shown in FIG. 2, the bias voltage supply circuit 16 is connected between the output terminal D of the digital signal source 4 and the input terminal I of the waveform shaping circuit 5, and is connected between the power supply Vcc and the ground. The movable terminal comprises a variable resistor 23 connected to the input terminal I of the waveform shaping circuit 5. In this case, the resistance value of the variable resistor 23 is the digital signal (TX DAT
A) smaller than the high output resistance at the output terminal D of the digital signal source 4 when not generating, and low at the output terminal D of the digital signal source 4 when generating the digital signal (TX DATA). Select a value larger than the output resistance. The waveform shaping circuit 5 includes an integrated circuit (IC) 17 for an inverter and an input terminal I of the IC 17.
A bias voltage is applied to the input resistor 18 connected in series with the feedback resistor 19 connected between the input and output terminals of the IC 17, the output resistor 20 connected in series with the output terminal of the IC 17, and the output terminal of the waveform shaping circuit 5. It is provided with first and second bias resistors 21 and 22 for giving.

Next, FIGS. 3A to 3F show the temporal displacement status of the signal waveform of each part in the transmitting section of this embodiment as the temporal displacement status of the signal waveform of the same part in the known transmitting section. FIG. 3 is an explanatory diagram for comparison, in which (a) is a digital signal (TX) output from a digital signal source 4.
DATA), (b) the output signal of the waveform shaping circuit 5,
(C) shows the output signal (modulation signal) S _M of GF6, and (d)
Is a signal waveform diagram showing an amplifier start-up signal (PA RUMP), (e) is a transmission enable signal (TX ENB), and (f) is an explanatory diagram showing an oscillation frequency deviation of the VCO 1, respectively. The solid line relates to the transmitter of this embodiment, and the dotted line relates to the known transmitter.

In FIGS. 3A to 3F, the vertical axis represents the amplitude or frequency deviation of each signal, and the horizontal axis represents time. In this case, the times t4 to t11 are times in the period of the transmission slot and correspond to the times t4 to t11 shown in FIG.

By the way, the difference between the operation of the transmitting section of the present embodiment having the above-mentioned configuration and the operation of the already-known transmitting section described above is slight in the operation in the process of obtaining the modulated signal S _M in the modulated signal supplying section. 3A, since the operation of the other constituent parts is almost the same except for the difference of
Through (f) together, only the operation of the process of obtaining the modulation signal S _M in the modulation signal supply unit of the transmission unit of the present embodiment will be described, and the description of the other operations will be given with the operation description of the known transmission unit. I will omit it because it overlaps.

First, at time t4, the period of the blind slot so far ends and the period of the transmission slot starts. At this time, the digital signal source 4 does not generate the digital signal (TX DATA), and the output resistance value of its output terminal is larger than the resistance value of the variable resistor 23 of the bias voltage supply circuit 16, so that the digital signal Source 4
To the output terminal of the bias voltage Vb via the variable resistor 23.
Is added. The voltage at the output terminal of the digital signal source 4 is higher than the voltage at the same output terminal in the known transmitter by the voltage Vb, as shown in FIG.
Accordingly, the voltage at the output terminal of the waveform shaping circuit 5 is
As shown in (b), it is lower than the voltage of the same output terminal in the known transmitter by a voltage corresponding to Vb, and G
Output terminal of F6, that is, modulation signal input terminal I of VCO1
The voltage of _M is also slightly lower than the voltage of the same output terminal in the known transmitter, as shown in FIG. However, since the phase was controlled to a predetermined frequency in the blind slot period based on this voltage, the reference oscillation frequency f _T1 of the VCO ₁ is, as shown in FIG. Same as f _T.

Next, at time t5, the transmission enable signal (TX ENB) changes to the low level indicating the active state, the contact of the first power switch 14 is closed, and the preamplifier 8 is activated. At this time, the output terminal of the digital signal source 4, the output terminal of the waveform shaping circuit 5, the GF6
Although the respective voltages at the output terminals of VCO1 are the same as in the previous state, the output load impedance of VCO1 decreases due to the decrease of the output impedance of preamplifier 8, so that the oscillation frequency of VCO1 is the reference oscillation frequency f. It shifts to the first oscillation frequency (f _T1 + Δf ₁ ) which is higher than _T1 by the first frequency deviation Δf ₁ .

Subsequently, at time t6, the amplifier start-up signal (PA RUMP) changes to the high level indicating the active state, the contact of the second power switch 15 is closed, and the power amplifier 9 becomes the active state. Also at this time, the output terminal of the digital signal source 4, the output terminal of the waveform shaping circuit 5, the GF
Although the respective voltages at the output terminals of 6 are the same as in the previous state, the power supply voltage Vcc associated with the power supply of the power amplifier 9 being turned on.
By a reduction in the oscillation frequency of the VCO1 is so far the first oscillation frequency by (f _T1 + Δf ₁₎ frequency deviations Delta] f ₂ further of the second than the higher second oscillation frequency (f _T1 +
Re-shift to Δf ₁ + Δf ₂ ). The deviation of the oscillation frequency up to this point is the same as in known transmitters.

At time t7, the digital signal source 4 starts to generate a digital signal (TX DATA), and the output resistance value of its output terminal is greater than the resistance value of the variable resistor 23 of the bias voltage supply circuit 16. Therefore, the bias voltage Vb applied to the output terminal of the digital signal source 4 through the variable resistor 23 is short-circuited and invalidated by the low output resistance value of the digital signal source 4 to the output terminal of the digital signal source 4. Is a digital signal (TX D
ATA) is supplied. This digital signal has a relationship shifted to the negative voltage side with reference to the bias voltage Vb. And this digital signal (TX DATA)
Is shaped by the waveform shaping circuit 5 into a square wave signal as shown in FIG. 3 (b).
In F6, as shown in FIG. 3 (c), it is converted into a sinusoidal modulation signal S _M that is slightly shifted to the positive voltage side with respect to the bias voltage, and is supplied to the modulation signal input terminal I _M of the VCO 1. At this time, the LPF 33 holds the control voltage when the VCO 1 is oscillating at the reference oscillation frequency f _T by the bias voltage Vb during the blind slot period. With this control voltage applied, VCO
1 is supplied with the modulation signal S _M shifted to the positive voltage side, and frequency shift keying ( ₁ ) is performed with the second oscillation frequency (f _T1 + Δf ₁ + Δf ₂ ) being equivalently shifted to the reference oscillation frequency f _T1. GFSK modulation is performed to obtain a GFSK modulated signal as shown in FIG.

Next, at time t8, the digital signal source 4 stops the generation of the digital signal (TX DATA) and the supply of the modulation signal S _M to the VCO 1 is stopped, so that the GFSK modulation signal of the VCO 1 is changed. The generation is also stopped, and the oscillation frequency of the VCO 1 becomes the non-modulated second oscillation frequency (f _T1 + Δf ₁ + Δf ₂ ).

Then, at time t9, the amplifier start-up signal (PA RUMP) changes to the low level indicating the inactive state, and the contact of the second power switch 15 opens,
The power amplifier 9 switches to the inactive state. Due to the conversion of the power amplifier 9 to the inactive state, the power source voltage VCO of the VCO 1
cc rises, and the oscillation frequency of VCO1 is
Oscillation frequency (f _T1 + Δf ₁ ).

Next, at time t10, the transmission enable signal (TX ENB) changes to the high level indicating the inactive state, the contact of the first power switch 14 is opened, and the preamplifier 8 becomes inactive. . The conversion of the preamplifier 8 to the inactive state increases the output impedance of the preamplifier 8, that is, the output load impedance of the VCO 1, and the oscillation frequency of the VCO ₁ becomes the original reference oscillation frequency f _T1 .

Then, at time t11, the period of the transmission slot ends, the period of the subsequent receiving slot and the like elapses, and then the period of the next blind slot is entered again, and the above-described operation is repeatedly executed.

During such a series of operations, the variable resistor 23 of the bias voltage supply circuit 16 is adjusted so that the center frequency of the GFSK modulated signal is substantially equal to the reference oscillation frequency f _T1 of the VCO 1 during the transmission time slot. In this case, the VCO accompanying the change in the output impedance when the preamplifier 8 is switched to the active state or the inactive state.
VCO1 depending on output load impedance variation
Of the oscillation frequency of the VCO 1 or the oscillation frequency of the VCO 1 depending on the fluctuation of the power supply voltage Vcc when the power amplifier 9 is switched to the active state or the inactive state. The digital signal (TX
The center frequency of the GFSK modulated signal obtained from VCO1 by DATA) is V
It is possible to substantially match the reference oscillation frequency f _T1 obtained from CO1, and the VCO during the transmission slot period
The deviation of the oscillation frequency of 1 can be reduced.

As described above, according to the present embodiment, the bias supply circuit 16 is connected to the output terminal of the digital signal source 4 and the bias voltage is applied to the output terminal of the digital signal source 4, whereby the digital signal (TX DATA ),
Since the center voltage of each of the output square wave signal of the waveform shaping circuit 5 and the output sine wave signal (modulation signal) S _M of GF6 is shifted so that each signal is substantially asymmetric with respect to the center voltage, Even if the oscillation frequency of the VCO 1 slightly changes when the preamplifier 8 and the power amplifier 9 are switched to the active state or the inactive state, the VCO is V during the transmission slot period.
It is possible to make the center frequency of the GFSK modulated signal obtained by CO1 substantially coincide with the reference oscillation frequency f _T1 obtained by VCO1 during the blind slot period, and extremely reduce the deviation of the oscillation frequency of VCO1 during the transmission slot period. be able to.

In the above embodiment, the bias voltage supply circuit 16 is constituted by the variable resistor 23, but the present invention is not limited to this.
The configuration is not limited to the case where 6 is configured by the variable resistor 23, and the bias voltage supply circuit 16 may be configured by a fixed resistor.

[0054]

As described in detail above, according to the present invention, the voltage at the output terminal of the digital signal source is set by the bias voltage supplied from the bias voltage supply means during the blind slot, while , The bias voltage is invalidated during the period of the transmission slot and is set by the digital signal. That is, the voltage of the output terminal of the digital signal source in the period of the blind slot and the voltage of the output terminal of the digital signal source in the period of the transmission slot are set to be different, and the center voltage of the modulation signal supplied to the VCO is substantially the same. It is in a slightly shifted state.

As described above, according to the present invention, even when the oscillation frequency of the voltage controlled oscillator (VCO) slightly changes when the preamplifier or the power amplifier is switched to the active state or the inactive state, By supplying the VCO with a modulation signal whose center voltage is shifted slightly,
The center frequency of the GFSK modulated signal obtained by CO is VC
It is possible to substantially match the reference oscillation frequency of O and minimize the deviation of the oscillation frequency of the VCO during the period of the transmission slot, and to provide a high-performance time division two-way communication device having a highly accurate transmission frequency. It has the effect of being obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a transmission section of a time division two-way communication apparatus according to the present invention.

FIG. 2 is a circuit diagram showing an example of a configuration of a bias voltage supply circuit used in this embodiment shown in FIG.

FIG. 3 is an explanatory diagram showing a temporal displacement state of a signal waveform of each part in the present embodiment illustrated in FIG.

FIG. 4 is a block configuration diagram showing an example of a transmission unit of a known time division two-way communication device.

5 is an explanatory diagram showing a temporal displacement state of a signal waveform of each unit in the known transmission unit shown in FIG.

FIG. 6 is a circuit diagram showing an example of a configuration of a VCO in a transmission unit of a known transceiver.

FIG. 7 is a circuit diagram showing an example of a configuration of a waveform shaping circuit in a transmission unit of a known transceiver.

[Explanation of symbols]

 1 Voltage Controlled Oscillator (VCO) 2 Phase Control IC (PLL) 3 Low Pass Filter (LPF) 4 Digital Signal Source 5 Waveform Shaping Circuit 6 Gaussian Filter (GF) 7 Buffer Amplifier 8 Preamplifier 9 Power Amplifier 10 Transmit / Receive Switch 11 11 Band Pass Filter (BPF) 12 Antenna 13 Voltage Regulator (REG) 14 First Power Switch 15 Second Power Switch 16 Bias Supply Circuit 17 Inverter Integrated Circuit (IC) 18 Input Resistance 19 Feedback Resistance 20 Output Resistance 21 first bias resistor 22 second bias resistor 23 variable resistor

Claims (3)

[Claims] 1. A digital signal source that outputs a digital signal during a transmission time slot period, exhibits a low output resistance value, and exhibits a high output resistance value higher than the low output resistance value during a blind slot period immediately before the transmission time slot. A bias supply means for applying a bias voltage to the output terminal of the digital signal source via a resistor, and an oscillation signal of a predetermined transmission frequency during the blind slot period and an output of the digital signal source during the transmission time slot period. A voltage-controlled oscillator that outputs a modulated signal that is modulated based on the voltage-controlled oscillator, outputs an error signal indicating a phase difference between the oscillation signal and a reference frequency signal in the blind slot period, and substantially in the transmission time slot period. The phase control circuit for invalidating the error signal and the error applied to the voltage controlled oscillator. A time-division two-way communication device, comprising: a low-pass filter that smoothes a difference signal. 2. The bias supply means comprises a resistor having a resistance value higher than a low output resistance value of the digital signal source connected between an output terminal of the digital signal source and a power supply terminal. The time-division two-way communication device according to claim 1, characterized in that 3. The time division two-way communication according to claim 1, wherein the output digital signal of the digital signal source is supplied to the voltage controlled oscillator through at least a waveform shaping circuit and a Gaussian filter. apparatus.