JPH08181626A - Digital matching system for antenna matching circuit - Google Patents

Abstract

PURPOSE: To improve a matching accuracy by using a binary code retrieved by two-branch retrieval as a start point, retrieving preceding and succeeding points of the start point so as to detect an optimum point and setting a variable element onto the data. CONSTITUTION: A variable element of a matching circuit 4 adopts a relay changeover system and relays are controlled by a binary code signal from a CPU 3. Furthermore, an error signal of an error detector 2 is zero in a matching state and in the retrieval of VSWR, a minimum point of a reflection power Pr is obtained in the state of impedance error zero. When the VSWR is discriminated to be OK, preceding and succeeding points of the start point being the retrieved matching point are retrieved. Then an optimum point of the VSWR obtained by a prescribed equation is detected and data of the obtained point are set to the variable element. Moreover, a CPU 3 controls a relay switching signal while discriminating a signal outputted by an error detector 2 to vary the binary code.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital matching system of an antenna matching circuit, and more particularly to a variable system of a variable element of the matching circuit.

[0002]

2. Description of the Related Art FIG. 1 shows an example of a system diagram of a digital matching type antenna matching circuit. In the figure, a transceiver 1 is a device that supplies high frequency power to an antenna.

The error detector 2 detects a signal necessary for the automatic matching operation of the antenna matching device, and detects a resistance R represented by a complex number R ± jφ, a phase difference φ, a traveling wave power Pf and a reflected power Pr. 4 circuits are incorporated, each of R, φ,
Outputs Pf and Pr. The error detection is performed by converting the load impedance R from 50Ω, for example, the load error R in Table 1, and the phase error φ from the pure resistance of the load, for example, into Table 2 and converting the voltage into a voltage.

[0004]

[Table 1]

[0005]

[Table 2]

The matching circuit 4 is a circuit for converting the impedance of the antenna 5 into the impedance of the transceiver 1, and is composed of a variable capacitor V _C and a variable coil V _L. Each variable element changes the constant by switching the relay. Each relay is switched by the binary code from the CPU 3. ko-kn and k'o-k'n represent relay contacts. Co to Cn represent capacitors. Lo to Ln represent coils.

The CPU 3 is a microcomputer, and controls the relay switching signal while judging the signal output from the error detector 2.

The antenna 5 radiates high frequency power.

FIG. 4 shows a variable element V _L of the conventional matching circuit 4.
3 is a flowchart of a method for changing V and V _C. CPU3
The binary code for changing the variable element from is changed according to the following procedure.

First, the L and C initial positions of the variable elements V _L and V _C are set, and the error signal is judged at the lower limit value and the upper limit value of the entire variable range of the binary code, and the error signal falls within this range. Confirm that there is a place where it becomes zero 0 (S
1). Next, the entire variable range (corresponding to the frequency band) of V _L is searched for a range in which the error signal becomes zero 0 at constant step intervals (S2). In the R polarity reversal of the next step (S3), as shown in Table 1, the value of the coil (R) is switched by the relay to change from the plus + numerical value to the minus- numerical value with respect to the reference value 0, and vice versa. -Change from a numerical value to a plus + numerical value, and if there is a change in the error signal, proceed to the next step (S4), the central value of the range where the error signal obtained by searching the binary code in step (S2) becomes zero 0. Then, whether the error signal becomes zero 0 is in the lower half or upper half of the range is determined. The binary code value for relay switching is determined where the error signal becomes zero 0 by this determination (S4).

In the next step (S5), VSWROK is determined. VSWROK is a value of VSWR defined by PfMAX and PrMIN, and VSWR when the error signal is zero is determined in the previous step. This VSWR is given by equation 2.

[0012]

[Equation 2]

If VSWR is not OK in step (S5), then similarly, the entire variable range of V _C is searched for a range in which the error is zero 0 at constant step intervals (S5).
6). Here, in the polarity reversal (S7) that inverts the polarity of the capacitor (φ), as shown in Table 2, the capacitor is switched by the relay and changed from the positive + numerical value to the negative- numerical value,
Conversely, when the error signal is changed from minus to plus and the error signal is changed, the process proceeds to the next step (S8), and the central value of the range where the error signal searched for the binary code in step (S6) becomes zero 0 Then, it is judged whether the error signal becomes zero 0 in the lower half or the upper half of the range, and the binary code value for relay switching is set at the position where the error becomes zero 0 according to the judgment result. Determine (S
8). In step (S9), it is determined whether it is VSWROK. If VSWR is not OK, the repeat counter is incremented by 1 (S10) and the search operation is repeated from step (S2).

Steps 2 (S4) and 2 (S8)
In the branch search, the binary code is set to the center value of the area range obtained in the previous search, and it is determined whether the area where the error signal becomes zero 0 is in the lower half or the upper half of this range, This operation is repeated up to the minimum digit of the binary code while counting up (S10), and the binary code value for relay switching is determined when the error signal becomes zero 0.

[0015]

The above is the conventional search method. However, there are cases where the optimum point of VSWR cannot be obtained for the following reasons. That is, (1) Due to the circuit configuration, the point where the error signal becomes zero 0 and the point where VSWR becomes the optimum value do not necessarily match.

(2) Although related to the problem of the resolution of the binary code, the points finally obtained by the bifurcation search,
When comparing adjacent points across the point where the error signal becomes zero 0, the above method does not necessarily select the one where the error signal is close to zero 0.

An object of the present invention is to solve the problem of the prior art that the matching accuracy of the antenna matching circuit is low, and to provide a high accuracy digital matching method capable of increasing the matching accuracy.

[0018]

The above object is to use the binary code value retrieved by the two-branch search as a starting point,
This is achieved by adding a VSWR search process of searching the points before and after that to detect the optimum point of VSWR and setting the value of the variable element to the data of the obtained point.

[0019]

In the VSWR search of the above-mentioned means, the reflected power Pr is minimized while shifting the variable elements V _L and V _C by 1 point before and after the binary code value searched by the previous two-branch search. Search for
The data of the obtained point, that is, the binary code value is used to switch the relay and set the values of the variable elements V _L and V _C.

By this VSWR search processing, it is possible to always match the optimum VSWR value.

[0021]

EXAMPLES The present invention will be described below with reference to examples. FIG.
In, the variable elements of the matching circuit 4 are of a relay switching system, and these relays are controlled by a binary code signal from the CPU 3. When the error detector 2 is in the matched state, the error signal becomes zero 0. In the search for VSWR, the minimum point of the reflected wave power Pr is obtained when the impedance error is zero.

FIG. 2 shows a flow chart of the matching method according to one embodiment of the present invention.
A process called SWR search 10 is added. VS
The WR search 10 includes steps (S5) and (S5).
When it is determined to be VSWROK in 9), it is a process of searching for the points before and after this matching point as a starting point and detecting the optimum point of VSWR.

FIG. 3 shows a flowchart of the VSWR search 10. First, the flag counter is initialized (S11). Next, the search operation is repeatedly performed, but it is determined whether or not the number of times of repetition has been performed a predetermined number of times (S1).
2). This actual number of times usually ends in three times. Next, with respect to the variable element V _L , a point at which the reflected wave power Pr becomes the smallest is searched by shifting one point before and after the zero 0 point obtained by the two-branch search as a starting point (S13), and the obtained point data is obtained. Switch the relay to (S14),
Similarly, for the variable element V _C , the point where the reflected wave power Pr becomes the smallest is searched while shifting by 1 point before and after the starting point (S15), and the relay is switched to the data of the obtained point (S16). In the next step, the repeat counter is incremented by 1 (S17) and the operations in the above order are repeated. By repeating this, both V _L and V _C converge to the optimum values.

By adding the above VSWR search processing, it is possible to perform matching such that the optimum VSWR value is always obtained.

According to the experiment, the value obtained by the comparative value of VSWR expressed by the equation 2 was about 2.5 in the conventional method, but 1.4 or less was realized in the present invention.

[0026]

As described above, according to the present invention,
The matching accuracy of the antenna matching circuit can be always matched to a high value, and the VSWR value of 1.4 or less was realized.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a process of an embodiment of the present invention.

FIG. 3 is a partial detailed flowchart of FIG.

FIG. 4 is a flowchart illustrating a conventional process.

[Explanation of symbols]

1 ... Transceiver, 2 ... Error detector, 3 ... CPU, 4 ... Matching circuit, 5 ... Antenna.

Claims (2)

[Claims] 1. A phase error and a load error between the impedance of the HF radio transceiver and the impedance of the antenna and the matching circuit, and the traveling wave power and reflected wave power between the HF radio transceiver and the antenna are detected, and the detection signal is detected by a microcomputer. In variably controlling the variable element of the matching circuit with the binary code while making a determination in step 1, the step search for searching the range in which the impedance error signal becomes zero at a constant step interval over the entire variable range of the binary code, and the binary code The binary code value is determined by a two-branch search for determining whether the place where the impedance error signal becomes zero in the central value of the range searched previously is in the lower half or the upper half of the range. In the digital matching method, starting from the binary code value searched by the above-mentioned two-branch search, Number 1 of VSW to explore the point of before and after
A digital matching system for an antenna matching circuit, characterized in that a VSWR search process for detecting the optimum point of R and setting the value of the variable element to the data of the obtained point is performed. 2. The digital matching method for an antenna matching circuit according to claim 1, wherein the VSWR search is a search for a point where the reflected wave power is the minimum. [Equation 1]