JPH08180040A - Digital signal processor - Google Patents

Abstract

PURPOSE: To accelerate digital signal processing and to reduce substrate area and power consumption by providing a first product sum/addition part for executing the product sum processing of digital signals and also executing an addition processing. CONSTITUTION: A partial product reduction array 12 performs the multiplication processing of data (m, n) sent from an overflow detector 11 by the carry look- ahead system of 17 bits × 17 bits, generates plural partial product sums, performs the addition processing of the partial product sums and obtains three partial product sums. A clipper 14 performs the clipping processing of the three partial product sums by exclusive OR based on overflow signals sent from the overflow detector 11 and sends two final partial product sums to a carry save adder 15. The carry save adder 15 sends the result (a+m×n) of the addition processing of the two partial product sums and the data, (a) for instance, sent from a local bus LBO by a carry save method to the two input terminals of a high-speed adder 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing device for processing a digital signal according to a processing procedure according to a program.

[0002]

2. Description of the Related Art Processing a digital signal by operations such as digital calculation and conversion by a table is called digital signal processing, and a circuit for performing digital signal processing is called a digital signal processing circuit. This digital signal processing circuit is a circuit including a digital multiplication circuit section, an addition circuit section, a delay circuit section, and the like.

In recent years, in order to process a predetermined digital signal in real time by laying out an adder, a multiplier and a unit delay element, which are the basic constituent elements of the digital arithmetic processing as described above, along the flow of signal processing. , Dedicated large-scale integrated circuits (LSIs) have been developed. Although the digital arithmetic processing has been speeded up by this dedicated LSI, it is not easy to change the function due to lack of flexibility. Therefore, development of a device for performing general-purpose digital signal processing has been desired. Also,
Development of a general-purpose LSI has also been advanced, but it was expensive.

Therefore, it is possible to perform digital signal processing at high speed and easily change the function of the signal processing, and a device for performing general-purpose digital signal processing for processing a wide range of digital signals with a single chip, that is, digital signal processing. Device (DSP: digital signal process)
sser) is under development. This DSP is basically a single-chip microprocessor that includes a high-speed multiplier and can perform digital signal processing at high speed. Further, the bus structure in the DSP adopts a so-called Harvard architecture in which a program (control) bus and a data bus are separated. Therefore, fetching and execution of instructions are processed in parallel, and a high degree of pipeline processing is possible.

[0005]

In the instruction system for operating the DSP, the word length of the instruction is generally large in order to make the DSP compatible with a wide range of applications. Further, as described above, since the Harvard architecture is adopted, it is necessary to decode the instructions of the program to be handled and to have a complicated configuration when operating the DSP. Therefore, the DSP required for the signal processing is required. Becomes expensive, and not only the IC substrate area and mounting area of such a DSP become large, but also the power consumption becomes large.

Further, further improvement in the processing capability of DSP has been desired. For example, when performing signal encoding / decoding processing in VSELP (vector sum excited linear prediction), which is a standard encoding method for mobile communication, the signal is processed at half the speed of the conventional signal. It has been expected to speed up signal processing so that encoding / decoding processing by a half-rate VSELP method for executing the processing can be executed.

Therefore, the present invention has been made in view of the above-mentioned circumstances, and it is possible to speed up digital signal processing, reduce the substrate area and power consumption, and to program a digital signal processing method. A digital signal processing device is provided.

[0008]

In order to solve the above-mentioned problems, a digital signal processing device according to the present invention is a digital signal processing device for processing a digital signal in accordance with a processing procedure according to a program. The first product-sum / addition unit is configured to perform the product-sum processing and also the addition processing.

Further, according to the present invention, in the digital signal processing device having the first sum of products / addition unit, the shift unit for the digital signal, the barrel shifter logic unit for performing a logical operation, and the digital signal are processed. In this case, a program control unit for controlling the signal processing program and an address generation unit for generating the address of the signal processing program are included.

Further, according to the present invention, in the digital signal processing device comprising the first sum of products / addition unit, the barrel shifter logic unit, the program control unit and the address generation unit, the barrel shifter logic unit is A barrel shifter unit for performing a bit shift operation on the digital signal and a logic unit for performing a logical operation on the digital signal on which the bit shift operation is performed.

Further, according to the present invention, in the digital signal processing device having the first sum of products / addition unit, the barrel shifter logic unit, the program control unit and the address generation unit, the address generation unit is , FIFO (first in, first out: first-in, first-ou
t) Address signal processing is performed using a memory.

Further, the present invention is a digital signal processing device comprising the first sum of products / addition unit, the barrel shifter logic unit, the program control unit and the address generation unit, and a product of the digital signals. A data driven execution unit including a second product-sum / addition unit that executes addition processing and addition processing, and a control unit that controls the product-sum / addition calculation processing. is there.

Also, the present invention provides a digital signal processing device comprising the first sum of products / addition unit, the barrel shifter logic unit, the program control unit and the address generation unit, wherein the sum of products / addition is performed. Section, the barrel shifter logic section, the program control section, and the address generation section, a data memory that stores the processing result obtained by the data processing execution section, the data processing execution section, and the data. It comprises an aligner for connecting / exchanging data with a memory.

[0014]

According to the digital signal processing apparatus of the present invention, by providing the first product sum / addition unit, the first product sum / addition unit can be provided without providing a special addition circuit. The sum of products process and the addition operation process can be executed by one configuration.

When the barrel shifter logic unit, the program control unit and the address generation unit are further provided in the digital signal processing device, the program for performing the digital signal processing is controlled by the program control unit, An address for executing this program is generated in the address generation section, and data driving of signal processing is executed in the data driving execution section according to this address, and further, the data processing execution section is further executed. At, data driven signal processing is executed.

Further, in the digital signal processing device comprising the first sum of products / addition unit, the barrel shifter logic unit, the program control unit and the address generation unit, the barrel shifter logic unit further includes a barrel shifter. And a logic unit, the barrel shifter unit performs a bit shift operation on the digital signal, and the logic unit performs a logical operation process on the digital signal according to the bit shift operation.

Further, in the digital signal processing device comprising the first sum of products / addition unit, the barrel shifter logic unit, the program control unit and the address generation unit, the address generation unit further includes a FIFO. (First-in, first-out)
When address signal processing is performed using a memory, irregular data addressing can be performed by performing address signal processing using the FIFO memory in the address generation unit. Therefore, the digital signal processing device can be used in a wide variety of applications.

Further, in a digital signal processing device comprising the first sum of products / addition unit, the barrel shifter logic unit, the program control unit and the address generation unit, further, a second sum of products / addition In the case where the data drive execution unit including the control unit and the control unit is provided, in the data drive execution unit, before the data processing execution unit performs the digital signal processing, the data drive execution unit is operated according to the operation of the control unit. The data driving operation of the digital signal processing is executed by the product sum / adder unit 2 performing the product sum processing of the data. Therefore,
The speed of digital signal processing is increased.

Further, in the digital signal processing device comprising the first sum of products / addition unit, the barrel shifter logic unit, the program control unit and the address generation unit, the product sum / addition unit is further provided. When the data processing execution unit including the barrel shifter logic unit, the program control unit, and the address generation unit, the data memory, and the aligner are provided, the data obtained by the data processing execution unit is transferred to the data memory, Alternatively, when the data stored in the data memory is transferred to the data processing execution unit, the code of the data transferred by the aligner can be expanded / exchanged.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments to which the digital signal processing apparatus according to the present invention is applied will be described in detail below with reference to the drawings.

FIG. 1 is a block circuit diagram showing a schematic structure of a product sum / addition unit which is a main part of the digital signal processing apparatus of this embodiment.

In FIG. 1, two 16-bit data sent from the local bus LB0 are sent to the overflow detector 11. In addition, the overflow detector 11
The output from is sent to a partial-product reduction array 12 and a clipper 14. Further, two 18-bit most significant bits (MSB) outputs and one 16-bit least significant bit (LSB), which are outputs from the partial-product reduction array 12, are output to the clipper 14 via the logical shifter 13. To be done. The output from the clipper 14 is sent to the carry save adder 15. The output from carry save adder 15 is sent to high speed adder 16. The output from the high speed adder 16 is sent to the maximum / minimum value selector 18 via the clipper 17. The overflow flag O is output from the high-speed adder 16 and the overflow flag O
, And the negative flag N is sent to the maximum / minimum selector. The 40-bit data sent from the local bus LB0 is input to the high speed adder 16 and the maximum / minimum value selector 18, and the 40-bit data sent from the local bus LB1 is the carry save adder 15. , Logical shifter 19 and maximum / minimum value selector 18 described above. Further, the output from the logical shifter 19 is the high-speed adder 1
Sent to 6.

In FIG. 1, an overflow detector 11 detects overflow of the 16-bit data sent from the local bus LB0 based on a clip / shift control signal sent from a control bus (not shown). Further, the data after the overflow is detected, for example, m and n are sent to the partial-product reduction array 12.

The partial-product reduction array 12 is a part having a plurality of carry-save adders for carrying out addition processing by a so-called carry-save method, for example, a method of processing while holding carry data, so-called carry data. . Further, the partial-product reduction array 12 receives the data (m, n) sent from the overflow detector 11 from the carry look ahead of 17 bits × 17 bits.
ahead) to perform a multiplication process to generate a plurality of partial product sums (partial-product terms), and add these partial product sums to obtain three partial product sums. Of these three partial sums of products, two are MSBs and the other one is LSB. This result (mx
n) is sent to the logical shifter 13.

The logical shifter 13, based on a shift control signal sent from a control bus (not shown),
Logical shift processing of the three partial product sums (m × n) from the partial-product reduction array 12;
That is, a so-called left shift operation is performed to move the 0/1 bit to the left. That is, with this logical shift, the same effect as the multiplication processing of each final partial product sum can be obtained.

The clipper 14 is a logical shifter 1.
Based on the overflow signal sent from the overflow detector 11, the three partial product sums subjected to the logical shift processing in 3 are clipped by exclusive OR, and two final partial product sums (final partial-prod
uct) and sends the final partial product sum obtained to the carry save adder 15.

Further, the carry save adder 15 is based on a round processing control signal (round control bit) sent from a control bus (not shown), and the two final partial sums of products (m × n) clipped and the local sum. The data (eg, a) sent from the bus LB0 is added by the carry save method, and the result (a + m × n) obtained by the addition of the final partial product sums is added to the high-speed adder 1
It sends to two input terminals of 6 respectively.

The high-speed adder 16 is a part having a plurality of carry propagation adders (CPA). The first addition result (a + m × n) from the carry save adder 15 and 40-bit data sent from the local bus LB1 via the logical shifter 19, for example, X is input to one input terminal, and the other The second addition result (a + m × n) from the carry save adder 15 and the 4 from the local bus LB0
0 bits and data such as Y are input.

First, it is selected whether the addition processing of the first addition result and the second addition result is performed or the addition processing of the data directly input from the local buses LB0 and LB1 is performed. The result of this addition is 4
0-bit size data (a + m × n or X +
Y), and this data is sent to the clipper 17. Further, the high-speed adder 16 generates an overflow flag O when the number of digits overflows in the process of the addition processing, sends the overflow flag O to the clipper 17, and the addition result becomes negative. If it becomes negative, a negative flag
N is generated, and this negative flag N is sent to the maximum value / minimum value selector 18. Note that the subtraction process is realized by taking the complement of 2 and performing the addition process without separately providing a subtraction circuit system. The clipper 17 is a high-speed adder 1
The data subjected to the CLA addition processing in 6 is clipped based on the presence / absence of the overflag O, and the obtained data is output to the maximum / minimum value selector 18.

Further, the maximum / minimum selector 18 has the data clipped by the clipper 17 based on the presence / absence of the negative flag N sent from the high speed adder 16 and the data from the local bus LB0. The maximum value / minimum value is selected from the data from the local bus LB1 and the selection result is output to the local bus LB0.

It will be understood that by adopting the configuration as shown in FIG. 1, it becomes possible to give the above-mentioned product sum / addition unit the function of executing the product sum process and the addition process.

FIG. 2 is a block diagram showing a schematic structure of a main part of the digital signal processing apparatus of this embodiment.

In FIG. 2, the digital signal processing device is roughly divided into a data driving execution unit 30 and a data processing execution unit 3.
1, a program controller 26, an address generator 27, a data memory 28, and a program memory 29.
Further, the data driving execution unit 30 is composed of a sum of products / addition unit 21 and a control unit 22, and a data processing execution unit 31.
Is composed of a product sum / addition unit 23, a barrel shifter logic unit 24, and a register file 25.

In the digital signal processing device, the product sum / addition unit 23, the barrel shifter logic unit 24 and the register file 25 of the data processing execution unit 31, the program control unit 26, and the address generation unit 27 are the local bus. It is connected to LB0 and LB1. Data memory 2
8, the program memory 29, and the register file 25 are connected to the memory buses MB0 and MB1. Furthermore, the control unit 22 of the data drive execution unit 30 is connected to the memory bus MB0. The product sum / addition unit 21 of the data driving execution unit 30 and the register file 25 of the data processing execution unit 31 are connected to the special buses SB0 and SB1. An isolator 33 is inserted and connected between each component and each bus.

According to the digital signal processing device, the program control section 26 includes the program memory 29.
The digital signal processing program stored in is read out and controlled. Also, based on this program,
The address generator 27 generates an address, the data drive execution unit 30 drives the digital signal processing based on the address, and the data process execution unit 31 executes the digital signal processing in response thereto. . The processing results of the data driving execution unit 30 and the data processing execution unit 31 are accumulated in the register file 25, and the accumulated data processing results are sent to and stored in the data memory.

FIG. 4 is a block circuit diagram showing a main part of the barrel shifter logic section 24 provided in the data processing execution section 31 of the digital signal processing apparatus shown in FIG.

In FIG. 4, the barrel shifter logic unit is roughly divided into a data path unit 51 and a data interpretation / counter unit 52.
Composed of. Further, the data path unit 51 includes a masker 41, a barrel shifter 42, a sign bit detector 43.
The data interpreting / counter unit 52 includes an incrementer 45, a first shift counter 46, a second shift counter 47, and a selector 5.
0, a high speed adder 48 and a complement adder 49.

In the data path unit 51, 40-bit data input from the local bus LB1 is sent to the masker 41. The output from the masker 41 is sent to the logical operation unit 44. The 40-bit data input from the local bus LB0 is sent to the barrel shifter 42 and the sign bit detector 43. The output from the barrel shifter 42 is sent to the logical operation unit 44.
The output from the sign bit detector 43 is sent to the barrel shifter 42 and the data bus DB. The data bus DB is a bus connected to the local bus LB0.

In the data interpretation / counter unit 52, the data bus DB and the first shift counter 4 are also provided.
Sixteen-bit data is bidirectionally sent to and from the sixth and second shift counters 47. In addition, the first shift counter 4
6 and the incrementer 45 output data bidirectionally. Further, the 6-bit (LSB) output from the first shift counter 46 is output to the second shift counter 47,
It is sent to the high speed adder 48 and the selector 50. Also,
6 bits (LSB) from the second shift counter 47
Is sent to the high-speed adder 48 and the selector 50. The output from the high speed adder 48 is the complement adder 49, the selector 50, and the data bus DB.
Sent to. The sign bit from the high speed adder 48 is sent to the complement adder 49 and the selector. The output from the complement adder 49 is sent to the selector 50 and the data bus DB.

In the data path unit 51, the masker 41
Performs mask processing of the data sent from the local bus LB1 and sends the data to the logical operation unit 44.

Further, the barrel shifter 42 performs a bit shift process on the data sent from the local bus LB0 based on a signal indicating a so-called sign bit position, which is a code digit sent from a sign bit detector 43, which will be described later. The data is sent to the logical operation unit 44. Also,
The sign bit detector 43 detects the sign bit from the 40-bit data sent from the local bus LB0, and the sign bit is detected by the barrel shifter 42.
And send to the data bus.

The logical operation unit 44 also performs logical operation processing using the data masked by the masker 41 and the data bit-shifted by the barrel shifter 42, and sends the operation result to the local bus LB0. .

In the data interpretation / counter section 52, the first shift counter 46 fetches 16-bit data from the data bus DB and sends the fetched data to the incrementer 45 and the data bus DB. Further, the data incremented by the incrementer 45 is compared with the already fetched data, and the data satisfying the condition set by the digital signal processing program is sent to the second shift counter 47. The first shift counter 46 outputs 6-bit LSB data of the fetched data.

As described above, the incrementer 45 increments the output from the first shift counter 46 according to the program of the digital signal processing, and outputs the processing result to the first shift. It returns to the counter 46. Further, the second shift counter 47 stores the last transmitted data among the data satisfying the above conditions transmitted from the first shift counter 46. The stored data is sent to the data bus DB. Further, the second shift counter 47 is
The 6-bit data of the LSB of the stored data is output.

The high-speed adder 48 performs addition processing on the 6-bit LSB data sent from the first shift counter 46 and the second shift counter 47, and outputs the addition result and the sign bit generated during the addition processing. . The complement adder 49 performs addition processing on the addition result based on the sign bit and outputs the addition result. Selector 5
0 is the 6-bit LSB data output from the first shift counter 46 and the output from the second shift counter 47 based on the sign bit and a control signal sent from a control bus (not shown). L
The number of bits of data moved / the number of bits of masked data are detected from the 6-bit data of SB, the output from the high-speed adder 48, and the output from the complement adder 49, and the control bus is detected. Output to.

FIG. 5 is a block circuit diagram showing a main part of the address generation unit 27 of the digital signal processing device shown in FIG.

According to FIG. 5, the following 15 registers are present in the address generator. Four address registers (adr0-adr) of the address register unit 64
3), the four offset registers (off0-off3) of the offset register unit 65, the mode register unit 66
4 mode registers (mod0-mod3), two FIFO (first-in-first-out) registers (fl and fd), and one bus address register (bad).
r).

Further, in this embodiment, each address register has a maximum of four addressing modes. For example, in adr0, four programming syntaxes (fixed programming syntax) are given, and each programming syntax is ^* adr0.
++, ^* adr0-, ^* adr + 2, and ^* adr0
It is fixed at%. These ^* adr0 ++, ^* adr
0−−, ^* adr + 2, ^* adr0% are written in the C language, that is, in the C language system. These first three addressing modes ^* adr0 ++, ^* adr0-- and ^* adr + 2 are post-increment increasing by 1 per cycle and post-decrement decreasing by 1 per cycle.
ecrement) and the post-increment that increases by 2 per cycle. Another addressing mode, ad
r0% can be changed to any of eight addressing modes as shown in FIG. 6, for example, by using three MSBs of mod0. The mode register is m
od0h = mod0 [15:13], that is, mod0
3 MSBs and mod0l = mod0 [1
2: 0], that is, 14 bits from the LSB of mod0.

The 4-input adder 67 and the 4-input adder 68 modify the addresses sent from the address register section 64, the offset register section 65 and the mode register section 66. The address is incremented by the address register unit 64 and the 4-input adder 67 or the 4-input adder 68. The address modified by the 4-input adder 67 is sent from the address register unit 64 to the address output terminal DA0, and the address modified by the 4-input adder 68 is sent from the address register unit 64 to the address output terminal DA1. It is output and also sent to the external memory accelerator control unit 61.

Further, for example, when very irregular data addressing is required, the same number of steps as the actual data processing is required only by the address calculation. So FI
FO memory is used to solve this problem. Specifically, in the FIFO memory 63, the fifo data register (f
load any address set via d) and f
The FIFO memory length is set via the ifo length register (fl), and mod0 [15:13] is set to fi
Set to fo index mode (the above operation is called initial setting). With this initialization, the FI is always used whenever adr0% is used.
The data can be automatically read from the FO memory 63 to mod0 [12: 0].

FIG. 7 is a block diagram showing the main part of the program control unit of the digital signal processing apparatus shown in FIG.

In FIG. 7, the program control section is roughly divided into a program decoding section and a program processing section.

The program decoding section is a section comprising an instruction register 71 and an instruction decoder, and decodes program memory data sent from the program memory 29 of FIG. 2 via the program memory data input terminal PD to perform digital signal processing. The decoded program is output to each part of the device as an instruction.

Further, the program processing section, as shown in FIG. 7, has a program counter (P
C) 72, backup circuit 73, PC stack 7
4 and an immediate register 75, and a loop controller 82. Also, the loop control unit 8
2 is a loop counter (lc) 76, an adder 77,
It is a part including a loop end address (lea) register 78, a loop start address (lba) register 80, and a loop stack 81.

Here, the program counter (PC) value is the counter value of the program decoded by the program decoding unit. This PC value is sent to the PC stack 74 and taken in, and is held by the backup circuit 73. In addition to the above PC value, the PC stack 74 also takes in an interrupt control signal from an interrupt controller so that it can handle normal subroutine processing and interrupt instruction processing.

The immediate value register 75 takes in the immediate value of the instruction sent from the instruction register (IR) 71 and sends it to the adder 77 and the data bus. Also, the adder 77 adds the PC value and the immediate value to each other and obtains the addition result, which is the loop end address (l
ea) to the data bus and loop end address register 78. The loop end address register 78 contains
The lea is temporarily stored.

The loop start address register 80 is a loop start address (l
Temporarily store ba). Also, the loop counter 76
The value of the counter (lc) when the above loop processing is performed is temporarily stored.

Then, the loop stack 81 has the above-mentioned lb.
a, the lea, and the lc value are fetched and stored, and the fetched loop start address, loop end address, and lc value are stored in the loop start address register 78 and the loop end address register as necessary in the process of loop processing. 80 and loop counter 76.

Here, as shown in FIG. 7, the program control unit has two types of stacks, such as a PC stack 74 for ordinary subroutines and interrupt instructions, and a loop stack 81 for loop instructions. In the operation of the digital signal processing device, no overhead (no-ove)
rhead do-loop) processing is performed. Further, despite the provision of the above-mentioned two types of stacks, the total stack size is realized in the same size as the stack size provided in the conventional digital signal processing device.

FIG. 8 is a block diagram showing the main part of the data drive execution unit of the digital signal processing device shown in FIG.

In FIG. 8, the data drive execution unit is roughly divided into a product sum / addition unit 21 and a control unit 22.

The product-sum / addition unit 21 has the same structure and function as the product-sum / addition unit 23 in the data processing execution unit 31 of FIG. 2, and via the register file 25 and the special buses SB0 and SB1. Connected.

The control unit 22 uses the trigger register decoder 9
1, instruction register 92 (dc0-dc
3), an instruction decoder 93, a mode register 94 (dm), and a latch circuit 95.

The trigger register decoder 91 includes a comparator, and a write control signal sent from the program control unit 26 via the memory bus MB0 and 4 which will be described later.
Two instruction registers 92 (dc0-dc
3) The trigger register code sent from 3) is compared, and the comparison result is sent to each part in the data driven execution unit 30. The write control signal is a control signal generated when the data stored in the data memory 28 is written in the register of the register file 25. Further, as will be described later, when the register is a trigger register defined by the processing program of the digital signal processing device, the comparison result becomes equal to any of the contents of dc0-dc3 described later, and the result register file 25 The register is started by the above-mentioned bus and is in a so-called triggered state.
In addition, when it is not in the “triggered state”, the data drive execution unit 30 does not operate.

The instruction register 92 has four registers, each of which is dc0 to dc.
Up to 3 is defined. The contents of this dc0-dc3 are
Rewriting is possible in accordance with the digital signal processing program, and the instructions fetched in each register are sent to the trigger register decoder 91 and the instruction decoder 93.

The instruction decoder 93 generates a data driving instruction based on the instruction sent from the instruction register 92 and a mode control signal sent from a mode register 94 (dm) described later, and the data driving instruction is latched by a latch circuit. It sends to the product sum / addition unit 21 via 95. The mode register 94 generates the mode control signal and sends it to the instruction decoder, so that, for example, the bit of the addition / subtraction result of the product sum / addition unit 21 in the data drive execution unit 30 is stored in the data processing execution unit 31. It has a function of controlling the execution mode of the product sum / addition unit 21 in the data drive execution unit 30, such as aligning with the bits of the addition / subtraction result obtained by the product sum / addition unit 23 of FIG.

Here, according to FIG. 8, when the write control signal and the trigger register code are equal, the data driving execution unit 30 operates and the data driving instruction is sent to the product sum / addition unit 21. , Register file 25
Using the operator existing in the register, the operation is started, that is, data driving is executed. The operation of the sum-of-products / addition unit 21 is continued while the data is written in the register, that is, the trigger register, and the data drive execution unit 30 does not operate while the data is not written in the trigger register. It becomes a state, that is, it does not drive. Therefore, it is possible to reduce power consumption. Further, the word length of the instruction can be suppressed as compared with the case where two conventional digital signal processing devices are connected in parallel by a software pipeline to perform data processing in parallel.
Further, the data drive processing can be made more flexible than the case where two conventional digital signal processing devices are connected by wiring in terms of hardware.

FIG. 3 is a diagram schematically showing the data surroundings in the digital signal processing apparatus of this embodiment.

In FIG. 3, the data driving execution unit 30 and the register file 25 are connected via the special buses SB0 and SB1, and the data memory 28 and the register file 25 are connected.
Is connected via the memory buses MB0 and MB1. Further, in the data processing execution unit 31, the register file 25 and the product sum / addition unit and barrel shifter logic unit 32 are connected via local buses LB0 and LB1, respectively.

That is, according to FIG. 3, the data obtained by the data driving execution unit 30 or the data obtained by the product sum / addition unit and barrel shifter logic unit 32 is stored in the data memory 28 via the register file 25. Writable,
Further, the data accumulated in the data memory 28 can be read out to the data driving execution unit 30, or the product sum / addition unit and barrel shifter logic unit 32 via the register file 25. Further, the memory buses MB0 and MB1, the special bus SB0, and the local bus LB0 are configured so that data can be moved bidirectionally with respect to the corresponding configurations, and the special bus SB1 and the local bus LB.
1 is connected so that data can be moved in one direction from the register file 25 to the corresponding components.

The register file 25 has eight registers such as registers a, b, c, d, e, f, m, and n, and each register has a capacity of 40 bits. There is. Also, for example, registers m, n,
d is assigned to store multipliers and multiplicands, for example registers a, b, c and d are assigned to general purpose accumulators, and for example registers b, d and
e and f are assigned to the accumulator of the intermediate data.

Further, as shown in FIG. 3, data is exchanged between the data memory 28 / data driving execution unit 30 / data processing execution unit 31 and each of the above registers of the register file 25, that is, from the data memory 28 to the register. Writing / reading data to / from the file 25, writing / reading data to / from the sum-of-products / addition unit and barrel shifter logic unit 32 of the data processing execution unit 31 to the register file 25 /
For reading and writing / reading of data from the data driving execution unit 30 to the register file 25, an aligner described later is provided in the register file 25, and the aligner described below is used to perform the preprocessing of the data, that is, the bit size handled in each configuration. The data after this pre-processing is performed after performing the processing for aligning the data or the data exchange processing. There are two types of this aligner according to each operation of write operation and read operation via MB0 or MB1. Similarly, from the register file 25 to LB0, LB1,
A read operation via SB0 or SB1 and a write operation to the register file 25 via LB0 or SB0, one type each, that is, a total of four types are required. The operations of these four kinds of aligners A0 to A3 are shown in FIGS. 9, 10, 11 and 12. In addition,
Register file 25 and MAU and BLU / DDU1
The signal handled by 01 is 40 bits, and the signal handled by the data memory 28 is 16 bits.

FIG. 9 is a diagram for explaining the operation of the aligner A0.

According to FIG. 9, the aligner A0 uses the register file 25 to add / add unit (MAU: multiply accumulator / adder unit) and barrel shifter logic unit (BLU: barrel-shifter logic u) in the data processing execution unit 31.
nit) / data-driven uni (DDU)
t) When data is sent to 101, data code expansion / exchange processing is performed. That is, register file 25 to L
MA through B0, LB1, SB0, or SB1
It operates when sending data to U and BLU / DDU 101. For example, as shown in FIG. 9, the signal be from the register b is sent to the aligner A0 and subjected to code extension processing in accordance with, for example, a code extension control signal to become a signal e,
It is sent to the MAU and BLU / DDU 101. Also, the signal bh from the register b or the register a
The signal al from is sent to the aligner A0, and is subjected to mutual data exchange / combination processing to become a signal h or a signal l, which is sent to the MAU and BLU / DDU 101.

FIG. 10 is a diagram for explaining the operation of the aligner A1.

According to FIG. 10, the aligner A1 is MAU.
And BLU / DDU101 to LB0 or SB
When sending data to the register file 25 via 0,
Perform the above pre-processing of the data. For example, as shown in FIG. 10, the signal e obtained by the MAU and BLU / DDU 101 is sent to the aligner A1 and is written in the register b of the register file 25 as the signal be, for example.
Further, the signal h is sent to the aligner A1 and, for example, the signal b
The signal h is written in the register b of the register file 25 as h, and the signal l sent to the aligner A1 is subjected to the coupling process, and is written in the register a of the register file 25 as the signal al.

FIG. 11 is a diagram for explaining the operation of the aligner A2. Here, the data handled by the register file 25 is 40 bits, while the data memory 28
The data handled by is 16 bits.

According to FIG. 11, the aligner A2 has a round / clip circuit 102, and the round / clip circuit 102 performs a round / clip process so as to convert a 40-bit signal into a 16-bit signal. Then, the obtained signal is sent to the data memory 28. That is, as shown in FIG. 11, the signal be, the signal bh, and the signal bl from the register b whose size is 40 bits.
Is sent to the aligner A2, and is sized into 16 bits by round / clip processing by the round / clip circuit, for example, and the 16-bit signal is written in the data memory.

FIG. 12 is a diagram for explaining the operation of the aligner A3.

According to FIG. 12, since the size of the signal stored in the data memory 28 is 16 bits, the aligner A3 stores the stored signal in the register file 2
The size of this signal must be 40 bits to be sent to the predetermined register in 5. Therefore, the above aligner A
3 performs extension processing / zero fill processing of the data code of the accumulated signal. That is, as shown in FIG. 12, the signal sent from the data memory 28 is subjected to a code extension process, a zero fill process, and a data exchange process according to the code extension control signal, and is converted into a signal be, a signal bh, or a signal bl. It is written in the register b in the register file 25.

FIG. 13 shows an FI as an example of pipeline processing using the digital signal processing apparatus of this embodiment.
FIG. 15 is a diagram showing an example applied to calculate the R filter characteristic by a software pipeline (SOFTWARE-pipeline), and FIG. 14 is a diagram showing an example of a program for performing this processing.

Further, the above software pipeline is
This is for performing the expressions (1) and (2) in parallel.

[0083]

[Equation 1]

According to FIG. 13, the address register adr
The data in the data memory 28 pointed to by 0 is taken into the register mh or the register ml in the register file 25 through the memory buses MB0 and MB1 in FIG.
Further, the data in the data memory 28 pointed to by the address register adr2 is taken into the register nh or the register nl in the register file 25 through the memory buses MB0 and MB1. These data are stored in the special buses SB0, SB1 / data buses DB0, DB1.
Through the data driven execution unit 30 / data processing execution unit 31
Sent to

For example, the data driving execution unit 30 multiplies each data of the register ml and the register nl or each data of the register mh and the register nh by the multiplier 111, and the multiplication result is integrated by the adder 112. It is added to the cumulative sum up to the previous multiplication result, that is, the multiplication result is incremented.

Further, the data processing execution unit 31 multiplies each data of the register mh and the register nl or each data of the register ml and the register nh by the multiplier 113, and the multiplication result is integrated by the adder 114. It is added to the cumulative sum up to the previous multiplication result, that is, the multiplication result is incremented.

Here, it is assumed that the data in the register ml is x
(I), the data in the register mh is x (i + 1), the data in the register nl is c (i), and the data in the register nh is c
Assuming that (i + 1), the operation performed by the data drive executing unit 30 is the operation represented by the above equation (1), and
The calculation performed by the data processing execution unit 31 is the calculation shown in the equation (2). The address register a
The data of dr0 and adr2 is the address generator 2 of FIG.
It is incremented by 7.

Further, according to FIG. 14, the instruction I0 represents an instruction for initializing the operation of the data driving execution unit 30 and the data processing execution unit 31. At this time, the instruction register d in the data drive execution unit 30
The operation result of ml × nl is stored in c0, the operation result of mh × nh is stored in the instruction register dc1, and an instruction to send the operation result stored in each instruction register to the register a of the register file 25 is given. . In addition, the instruction I0 is
It is instructed to increment the calculation result stored in the register a. The increment means adding a newly obtained operation result to an operation result stored in advance in a corresponding register. Further, for example, the operation result of mh × nh is fetched in the register mh. The result of multiplication processing of the data and the data stored in the register nh. In addition, a data processing execution unit (EXU) 31, a data memory (memory) 28, and a data drive execution unit (data-dri).
The ven unit (DDU) 30 operates in parallel with each other in one clock time of data processing of the data processing execution unit 31 in accordance with an instruction designated for each instruction.

The instruction I1 also instructs the data processing executing section 31 to initialize the register a in the register file 25 to 0. Further, the instruction I1 instructs the register file 25 to fetch the data designated by the address register adr0 into the register ml and the data designated by the address register adr2 into the register nl.

The instruction I2 instructs the data processing executing section 31 to initialize the register b in the register file 25 to 0. Further, the instruction I2 is the address register ad incremented by 1 with respect to the register file 25.
It is instructed to fetch the data designated by r0 into the register mh and the data designated by the address register adr2 incremented by 1 into the register nh. Further, the instruction I2 instructs the data driving execution unit 30 to store the operation result of ml × nl in the instruction register dc0 and send the operation result to the register a.

The instruction I3 instructs the data processing execution section 31 to repeatedly execute the operation instructions of the instructions I3 to I6 ten times. It also instructs the data drive execution unit 30 to store the calculation result of mh × nh in the instruction register dc1. Further, the data taken in the instruction register dc1 is sent to the register a, and the data in the register a, that is, the ml ×
It is added to the calculation result of nl.

The instruction I4 instructs the data processing executing section 31 to store the calculation result of mh × nl in the register b. Further, the instruction I4 is the address register ad that is incremented by 1 with respect to the register file 25.
The data designated by r0 is stored in the register ml, and
Address register a further incremented by 1
It is instructed to fetch the data designated by dr2 into the register nl.

Further, the instruction I5 instructs the data processing executing section 31 to store the operation result of ml × nh in the register b and add the operation result to the data of the register b. Further, the instruction I5 is the address register adr which is further incremented by 1 with respect to the register file 25.
The data designated by 0 is further added to the register mh by 1
It is instructed to take in the data specified by the address register adr2 incremented only by the register nh. Further, the instruction I5 instructs the data driving execution unit 30 to store the calculation result of ml × nl in the instruction register dc0. Furthermore, this instruction register dc
The data taken in 0 is sent to the register a,
It is added to the data in this register a.

Further, the instruction I6 instructs the data processing execution section 31 to perform the instruction I3.
To the instruction I5 are instructed to be loop-processed.

The instruction I7 instructs the data processing execution unit 31 to send the operation result of mh × nl to the register b and to add the operation result to the data of the register b. Further, the instruction I7 is the address register adr which is further incremented by 1 with respect to the register file 25.
It is instructed to fetch the data designated by 0 into the register ml. In addition, Instruction I7
The data drive execution unit 31 is instructed to store the calculation result of mh × nh in the instruction register dc1 and send the calculation result to the register a. Further, this instruction register dc1
The data taken in is sent to the register a and added to the data in the register a.

The instruction I8 instructs the data processing execution section 31 to send the operation result of ml × nh to the register b and to add the operation result to the data of the register b. Further, the instruction I8 instructs the register file 25 to send the data in the register a to the address register adr3.

The instruction I9 instructs the register file 25 to send the data of the register b to the address register adr3 and add it to the data of the address register adr3.

With the above configuration, in the digital signal processing, the addition part of the function of the conventional addition logic unit is moved to the sum of products unit, and the sum of products / addition unit is combined with the logical operation unit of the above addition logic unit. By using the barrel shifter logic unit including the barrel shifter unit, the IC substrate area is reduced and the speed of the logic operation is increased. Therefore, the data processing speed is increased.

Further, by providing the data driving execution unit and performing the data processing in parallel with the data processing execution unit, not only the operation speed becomes twice as high as that of the conventional digital signal processing device, but also the digital signal processing device is provided. The board area can be reduced and the word length of the instruction can be suppressed as compared with the case of performing data processing by using two. In addition, power consumption can be suppressed by setting the data drive execution unit to a non-operating state except during data drive. further,
The data drive processing can be made more flexible than in the case where two digital signal processing devices are connected by wiring in terms of hardware.

In this embodiment, the data drive execution unit is provided and the data drive execution unit is made to perform the drive operation of the data processing. However, the present invention is not limited to this. It goes without saying that the object of the present invention can be achieved without providing it separately. However, in this case, the data processing speed is lower than that in the case where the data drive execution unit is provided.

[0101]

As described above, according to the digital signal processing apparatus including the first product sum / addition unit according to the present invention, the first product sum / addition unit performs the product sum calculation process. By executing the addition arithmetic processing, it is not necessary to provide a special addition circuit such as the addition portion of the addition logic unit that is conventionally connected to the barrel shifter unit, and this addition unit can be deleted. The board area can be reduced, and the processing speed of logical operations can be increased.

In the digital signal processing device having the first sum of products / addition unit, barrel shifter logic unit, program control unit and address generation unit, the barrel shifter logic unit includes a barrel shifter unit and a logic unit. In the case where it is provided, since only the bit shift operation and the logical operation based on the bit shift operation are executed in the barrel shifter logic unit, the data processing speed is increased and the addition circuit is provided. Since it is not present, the substrate area can be suppressed.

Further, in the digital signal processing device comprising the first sum of products / addition unit, the barrel shifter logic unit, the program control unit and the address generation unit, the address generation unit is a FIFO (first In, first out: first-in, first-out) When address signal processing is performed using a memory, irregular data addressing is possible, so it can be used for various purposes, that is, a general-purpose digital signal. The processing device can be realized.

Further, in the digital signal processing device comprising the first product sum / addition unit, the barrel shifter logic unit, the program control unit and the address generation unit, a second product sum / addition unit is provided. In the case where the data driving execution unit including the control unit is provided, the data driving by the data driving execution unit and the data processing by the data processing execution unit can be performed in parallel. , While enabling high-speed data processing,
Power consumption can be suppressed by setting the data driving execution unit in the non-operating state except during data driving.

Further, in the digital signal processing device comprising the first product sum / addition unit, the barrel shifter logic unit, the program control unit and the address generation unit, the first product sum / addition unit is provided. And a data processing execution unit including the barrel shifter logic unit, the program control unit, and the address generation unit, a data memory, and an aligner, the data obtained by the data drive execution unit, Since the data obtained by the data processing execution unit can be stored in the same data memory, the substrate area can be suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a main part of a product sum / addition unit of the present invention applied to a digital signal processing device.

FIG. 2 is a block diagram showing a schematic configuration of a main part of the digital signal processing device.

FIG. 3 is a diagram schematically showing an area around data in the digital signal processing device.

FIG. 4 is a block circuit diagram showing a main part of a barrel shifter logic unit in a data processing execution unit of the digital signal processing device.

FIG. 5 is a block circuit diagram showing a main part of an address generation unit of the digital signal processing device.

FIG. 6 is a diagram showing an example of an addressing mode of an address register in the digital signal processing device.

FIG. 7 is a block diagram showing a main part of a program control unit of the digital signal processing device.

FIG. 8 is a block diagram showing a main part of a data drive execution unit of the digital signal processing device.

FIG. 9 is a diagram illustrating an operation of an aligner A0 in the digital signal processing device.

FIG. 10 is a diagram illustrating an operation of the aligner A1 in the digital signal processing device.

FIG. 11 is a diagram illustrating an operation of an aligner A2 in the digital signal processing device.

FIG. 12 is a diagram illustrating an operation of an aligner A3 in the digital signal processing device.

FIG. 13 is a diagram for explaining an example of the operation of the digital signal processing device according to the present embodiment.

FIG. 14 is a diagram showing an example of a program for operating the digital signal processing device.

[Explanation of symbols]

 11 Overflow Detector 12 Partial-Product Reduction Array 13 Logical Shifter 14 Clipper 15 Carry Save Adder 16 High-speed Adder 17 Clipper 18 Maximum / Minimum Selector 21 Sum of Products / Adder 22 Control Unit 23 Sum of Products / Adder 24 Barrel Shifter Logic Section 25 Register File 26 Program Control Section 27 Address Generation Section 28 Data Memory 30 Data Drive Execution Section 31 Data Processing Execution Section 42 Barrel Shifter 44 Logical Calculator 63 FIFO Memory 67, 68 4 Input Adder A0, A1, A2 and A3 Aligner

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G10L 9/18 E H03M 7/28 9382-5K

Claims (6)

[Claims] 1. A digital signal processing device for processing a digital signal according to a processing procedure according to a program, comprising a first product sum / addition unit for executing a product sum processing of the digital signals and also an addition processing. A digital signal processing device comprising: 2. A barrel shifter logic unit for performing shift operation and logical operation of the digital signal, a program control unit for controlling a signal processing program when processing the digital signal, and an address for generating an address of the signal processing program. The digital signal processing device according to claim 1, further comprising a generation unit. 3. The barrel shifter logic unit includes a barrel shifter unit for performing a bit shift operation of the digital signal,
3. The digital signal processing apparatus according to claim 2, further comprising a logic unit that performs a logical operation on the digital signal that has been bit-shifted. 4. The digital signal processing apparatus according to claim 2, wherein the address generation unit performs address signal processing using a FIFO (first in, first out) memory. 5. A second sum-of-products / addition unit that performs sum-of-products processing of the digital signals and also performs addition-processing,
3. The digital signal processing device according to claim 2, further comprising a data drive execution unit including a control unit for controlling the sum of products / addition calculation process. 6. A data processing execution unit including the first sum of products / addition unit, the barrel shifter logic unit, the program control unit, and the address generation unit, and a processing result obtained by the data processing execution unit is stored. 3. The digital signal processing apparatus according to claim 2, further comprising: a data memory for executing the data processing, and an aligner for connecting / exchanging data between the data processing execution unit and the data memory.