JPH0817922A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a manufacturing method of a semiconductor device wherein influence of halation and standing wave effect in the patterning of a resist film is little, and a connection hole can be suitably formed, when the connection hole is formed in the self-alignment manner between wiring patterns. CONSTITUTION:A plurality of wiring patterns 3a whose upper surface and side wall surface are covered with insulating antireflection films 4a, 6a composed of SiON are formed on a first interlayer insulating film 2 composed of SiO2. The wiring patterns 3a are covered with a second interlayer insulating film 7 composed of SiO2. On the second interlayer insulating film 7, a photoresist film is patterned, and an aperture part is formed which faces the space between the wiring: of the wiring pattern 3a and has the aperture width larger than or equal to the width of the space between the wirings. The second interlayer insulating film 7 and the first interlayer insulating film 2 are collectively etched via the aperture part, and a connection hole 9 is formed in the space between the wirings, in the self-alignment manner. Thereby the connection hole 9 is formed in a semiconductor device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device such as a highly finely integrated memory device, and more particularly to a method of forming connection holes for wiring connection in a self-aligned manner.

[0002]

2. Description of the Related Art In order to achieve high integration of a semiconductor device, a method of forming connection holes for wiring connection in a self-aligned manner is essential in addition to miniaturization of processing dimensions. As an example of forming the connection hole by this self-alignment, IEDM'92
A case of forming a connection hole between Al wirings processed with the minimum line width as described in (p837-p840) will be described with reference to the drawings.

First, as shown in FIG.
A first interlayer insulating film 22 made of SiO ₂ , a wiring film 23 made of Al, and an insulating film 24 made of Al ₂ O ₃ are laminated in this order on the top, and then a photoresist pattern 25 is formed to form a wiring pattern. To form. Then, the wiring film 23 and the insulating film 24 are subjected to reactive ion etching to form a wiring pattern 23a whose upper surface is covered with the insulating film 24a, as shown in FIG.

Next, as shown in FIG. 12, Al _{2 is formed} on the entire surface.
After the insulating film 26 made of O ₃ is formed, the insulating film 26 is etched back until the first interlayer insulating film 22 is exposed, thereby insulating the side wall surface of the wiring pattern 23a as shown in FIG. The film 26a is formed.

Through the above steps, as shown in FIG.
An insulating film 24a covering the upper surface of the wiring pattern 23a,
The insulating film 26a that covers the side wall surface of the wiring pattern 23a is formed, and the wiring formed in the inter-wiring space of the wiring pattern 23a in a later step is insulated from the wiring pattern 23a.

Next, as shown in FIG. 14, the insulating film 23
After the second interlayer insulating film 27 made of SiO ₂ is formed on the entire surface so as to cover the wiring pattern 23a covered with a and 26a, the second interlayer insulating film 27 is formed on the second interlayer insulating film 27 to form a connection hole. A photoresist pattern 28 is formed. Then, as shown in FIG. 15, until the lower wiring 21 is exposed, the second interlayer insulating film 27 and the first interlayer insulating film 22 are covered with the interlayer insulating films 22 and 27 made of SiO ₂ and Al.
Reactive ion etching is performed under the condition that the selection ratio between the insulating films 23a and 26a made of ₂ O ₃ can be secured. As a result, the connection hole 29 to the lower layer wiring 21 is formed between the wiring patterns 23a covered with the insulating films 23a and 26a.

By forming the contact holes 29 in a self-aligning manner as described above, the reactive ion etching is not restricted by the lithography resolution, so that the opening width of the contact holes 29 can be made equal to or smaller than the minimum line width. The wiring can be made finer.

[0008]

However, in the case of forming the contact hole in a self-aligning manner as described above, when patterning the photoresist film 28 for forming the contact hole, as shown by an arrow A in FIG. The exposure light when exposing the photoresist film 28 is reflected from the wiring pattern 23a, and there is a problem that the photoresist film 28 cannot be patterned well due to the influence of the reflected light.

That is, the light reflected from the wiring pattern 23a concentrates the light on a part of the resist, so that the dimension of the resist pattern varies due to so-called halation, or the light reflected from the wiring pattern 23a causes the resist pattern to be dispersed in the resist. Since light interference occurs in the resist in the height direction of the resist, the opening 28 of the resist pattern obtained after exposure is formed by the so-called standing wave effect.
The cross-sectional shape of a was deteriorated into a wavy shape.

Therefore, as shown in FIG. 15, the cross section 29a of the connection hole 29 has a defective shape.
It has become difficult to achieve high integration of the wiring pattern and causes insulation failure.

Therefore, the present invention has been proposed in view of such a conventional situation, and when the connection holes are formed in a self-aligned manner between the wiring patterns having a high light reflectance, the patterning of the photoresist film is performed. Reduce the standing wave effect in
It is an object of the present invention to provide a method for manufacturing a semiconductor device, which enables favorable formation of connection holes.

[0012]

In order to achieve the above-mentioned object, a method of manufacturing a semiconductor device according to the present invention comprises a first interlayer insulating film, an upper surface of which is an insulating antireflection film having an etching rate smaller than that of the first interlayer insulating film. And a step of forming a plurality of wiring patterns whose side wall surfaces are covered, a step of covering the wiring patterns with a second interlayer insulating film having an etching rate substantially equal to that of the first interlayer insulating film, Patterning a photoresist film on the second interlayer insulating film to form an opening having an opening width at least equal to the width of the inter-wiring space facing the inter-wiring space of the adjacent wiring pattern; A step of collectively etching the second interlayer insulating film and the first interlayer insulating film through an opening and opening a connection hole in the inter-wiring space in a self-aligning manner. That.

In the method of manufacturing a semiconductor device, the wiring pattern is covered with the insulating antireflection film by, for example, a step of laminating the insulating antireflection film on a wiring film forming the wiring pattern, and A step of collectively patterning the wiring film and the insulating antireflection film, a step of forming the insulating antireflection film again by covering the formed wiring pattern, and anisotropically etching the insulating antireflection film. The process of backing is performed.

In the method of manufacturing a semiconductor device described above, the insulating antireflection film needs to have an etching selection ratio with respect to the first interlayer insulating film and the second interlayer insulating film.
Therefore, for example, a SiON-based material film is used for the insulating antireflection film, and a SiO-based material film is used for the first interlayer insulating film and the second interlayer insulating film. Note that normally, SiO is used for the first interlayer insulating film and the second interlayer insulating film.
_{Since 2} is used, the insulating antireflection film only needs to have an etching selection ratio with SiO _2, and may be Si-rich SiO _x , for example, but a SiON-based material film is particularly preferable.

In the method of manufacturing a semiconductor device described above, it is preferable that after forming the connection hole, the insulating antireflection film exposed in the connection hole is oxidized by using plasma.

Then, SiON is formed on the insulating antireflection film.
When a SiO 2 -based material film is used for the first interlayer insulating film and the second interlayer insulating film, the photoresist film is subjected to photolithography using exposure light in the wavelength range of 150 to 450 nm. Then, patterning is performed, and the SiO 2
A composition formula SiO _x N _y H _z (where x is 0.30 to 0.70, y is 0.05 to 0.30, and z is 0
Is 0.50. It is preferable to use a material film represented by (4). The wavelength range of the exposure light of the photoresist film is g line (wavelength 436 nm), i line (wavelength 365 n).
m), a KrF excimer laser (wavelength 248 nm), an ArF excimer laser (wavelength 193 nm), and the like are taken into consideration to set the wavelength to 150 to 450 nm. And x, y,
The range of the numerical value of z was previously found by the applicant of the present application through simulations and experiments.

The composition of the SiON-based material film can be controlled by, for example, setting the kind and flow rate of the film-forming gas and forming the film with a plasma CVD apparatus. For example, the composition of the SiON-based material film to be formed can be controlled by changing the flow rate ratio of these film forming gases using SiH ₄ and N ₂ O as film forming gases. By controlling the composition of the SiON-based material film in this way, S
It is possible to control the optical constants (the real part and the imaginary part coefficient of the complex amplitude refractive index) of the insulating antireflection film made of the iON-based material film,
The antireflection effect can be optimized. That is, the value of the optical constant of the insulating antireflection film when the antireflection effect is optimum varies depending on the type of the underlying material layer, etc. By doing so, it is possible to obtain the optimum antireflection effect depending on the type of the base material layer and the like.

[0018]

Function: The wiring pattern is covered with an insulating antireflection film, and then the connection hole is formed in a self-aligning manner, so that the exposure light is reflected from the wiring pattern when the photoresist film for forming the connection hole is patterned. Is prevented, and the effects of halation and standing wave effects are reduced.

Further, after forming the connection hole, the insulating antireflection film exposed in the connection hole is oxidized by using plasma, so that the withstand voltage of the insulating antireflection film is improved.

The SiON-based material film has a wavelength range from far ultraviolet rays to near ultraviolet rays (a wavelength range of about 150 to 450 nm).
It is suitable as an insulating antireflection film used in the present invention because it has an excellent antireflection effect. Furthermore, the insulating antireflection film is a SiON-based material film, and the first interlayer insulating film and the second interlayer insulating film are a SiO-based material film, whereby the insulating property and the antireflection effect of the insulating antireflection film are improved. In addition to being excellent, the selection ratio of the etching rates of the first and second interlayer insulating films and the insulating antireflection film can be increased, so that the formation of the connection hole by self-alignment can be performed well. it can.

When a SiON-based material film is used for the insulating antireflection film and a SiO-based material film is used for the first interlayer insulating film and the second interlayer insulating film, the composition formula of the SiON-based material film is used. SiO _x N _y H _z (where x is 0.30 to
0.70, y is 0.05 to 0.30, z is 0 to 0.50
Is. By using the material film represented by (4), a particularly excellent antireflection effect is obtained as described in Japanese Patent Application No. 4-359750 by the present applicant.

[0022]

EXAMPLES Specific examples to which the present invention is applied will be described below. Needless to say, the present invention is not limited to the examples below.

Example 1 In this example, a process of forming a connection hole in a self-aligned manner between wiring patterns processed with a minimum line width in manufacturing a semiconductor device will be described.

First, as shown in FIG. 1, a first interlayer insulating film 2 made of SiO _{2 and} a wiring film 3 made of Al are formed on a lower layer wiring 1 made of a metal wiring material or an impurity diffusion region in a Si substrate. And antireflection film 4 made of SiON
Are laminated in this order. The insulating antireflection film 4 made of SiON has a thickness of 23 nm, n = 2.16,
The following conditions are satisfied so that k = 0.875 (n is the real part of the complex amplitude refractive index represented by n + ik, and k is the imaginary part coefficient of the complex amplitude refractive index represented by n + ik). To form a film.

Film forming apparatus: parallel plate type single wafer type plasma CVD apparatus Film forming gas: SiH ₄ = 50 SCCM, N ₂ O = 25 SCCM RF bias power: 190 W (frequency = 13.56 MHz) Pressure: 333 Pa (about 2.5 Torr) ) Substrate temperature: 360 ° C. Distance between electrodes: 1 cm Next, as shown in FIG. 2, the photoresist film 5 is patterned to form an Al wiring pattern. The patterning of the photoresist film 5 is performed, for example, by using a positive chemically amplified resist material (manufactured by Wako Pure Chemical Industries, Ltd., trade name: WKR-PT1) as a resist material and exposing it with a KrF excimer laser stepper. Thereafter, the insulating antireflection film 4 and the wiring film 3 are subjected to reactive ion etching to form a wiring pattern 3a whose upper surface is covered with the insulating antireflection film 4a, as shown in FIG.

Next, as shown in FIG. 4, an insulating antireflection film 6 made of SiON is formed on the entire surface under the same conditions as described above. Then, as shown in FIG. 5, the first interlayer insulating film 2 is formed.
Of the wiring pattern 3a by etching back the insulating antireflection film 6 under normal reactive ion etching conditions for SiO ₂ or reactive ion etching conditions for polysilicon until exposed between the wiring patterns. An insulating antireflection film 6a that covers the side wall surface is formed.

Through the above steps, as shown in FIG. 5, an insulating film 4a covering the upper surface of the wiring pattern 3a and an insulating film 6a covering the side wall surface of the wiring pattern 3a are formed,
The wiring formed in the inter-wiring space of the wiring pattern 3a in a later step is insulated from the wiring pattern 3a.

Next, as shown in FIG. 6, a second interlayer insulating film 7 made of SiO ₂ is formed on the entire surface so as to cover the wiring pattern 3a covered with the insulating antireflection films 3a, 6a. Then, in order to form the connection hole, as shown in FIG. 7, an opening 8 facing the inter-wiring space of the wiring pattern 3a and having an opening width equal to or larger than the width of the inter-wiring space.
The photoresist film 8 having a formed thereon is patterned on the second interlayer insulating film 7. At this time, the wiring pattern is covered with the insulating antireflection films 4a and 6a made of SiON, and the reflection of the exposure light from the wiring pattern 3a when the photoresist film 8 is exposed is suppressed. The resist film 8 can be patterned. In addition,
The opening width of the opening 8a of the photoresist film 8 is set to be equal to or more than the width of the inter-wiring space because the misalignment of the photomask is taken into consideration so that the width of the connection hole formed in a later step has a margin. This is to ensure that the connection hole is formed in the inter-wiring space of the wiring pattern 3a.

Then, as shown in FIG. 8, in order to form the connection hole 9 to the lower layer wiring 1 in the inter-wiring space of the wiring pattern 3a, the second interlayer insulating film 7 and the second interlayer insulating film 7 are formed until the lower layer wiring 1 is exposed. Etching is performed on the first interlayer insulating film 2. At this time, in order to open the connection hole 9 in a self-aligning manner, the etching of the insulating antireflection films 4a and 6a made of SiON does not proceed, and the first interlayer insulating film 2 and the second interlayer insulating film made of SiO ₂ are not formed. For example, the etching is performed under the following conditions so that only the film 7 is selectively etched. The etching conditions are not limited to the following examples, as long as the selection ratio of SiO ₂ and SiON can be obtained, and the etching apparatus, etching gas, etc. may be appropriately selected.

(1) Etching condition example 1 Etching apparatus: magnetron type reactive ion etching apparatus Etching gas: CHF ₃ = 30 SCCM, CO = 170 SCCM RF power: 1400 W (frequency = 13.56 MHz) Pressure: 5.3 Pa (about 40 mTorr) ) Substrate temperature: 20 ° C. Under these conditions, the etching rate of SiO ₂ increases due to the effect of extracting oxygen atoms from SiO ₂ by the etching gas CO. Under these conditions, SiO ₂ / S
The etching selection ratio of iON is about 20: 1.

(2) Etching condition example 2 Etching apparatus: ECR plasma etching apparatus Etching gas: CHF ₃ = 45 SCCM, CH ₂ F ₂ = 5 SCCM Microwave power: 1200 W (frequency = 2.45 GHz) RF bias power: 200 W (frequency) = 1.8 MHz) Pressure: 0.27 Pa (about 2 mTorr) Substrate temperature: 20 ° C. Under these conditions, the etching gas CH ₂ F ₂ is a gas capable of depositing a carbon-based polymer, so that the etching rate of SiON decreases. Under these conditions, SiO
The etching selection ratio of ₂ / SiON is about 20: 1.

(3) Etching condition example 3 Etching apparatus: Inductively coupled plasma etching apparatus Etching gas: C ₂ F ₆ = 50 SCCM Source discharge RF power: 1200 W (frequency = 2 MHz) Substrate RF bias power: 800 W (frequency = 1) .8 MHz) Pressure: 0.27 Pa (about 2 mTorr) Substrate temperature: 20 ° C. Under these conditions, high-order fluorocarbon gas is used as an etching gas, and due to etching by high-density plasma, generation of etching species is promoted and etching is performed. Will be faster. Under these conditions, SiO ₂ / Si
The ON etching selection ratio is 30: 1 to 50: 1.

(4) Example of Etching Conditions 4 Etching device: ECR plasma etching device Etching gas: CHF ₃ = 50 SCCM, S ₂ F ₂ = 10 SCCM Microwave power: 1200 W (frequency = 2.45 GHz) Substrate RF bias power: 200 W Pressure : 0.27 Pa (about 2 mTorr) Substrate temperature: -50 ° C. Under these conditions, the deposition ratio of S on the cooling substrate is expected to improve the selection ratio, so that the bias can be lowered and damage can be reduced. Under these conditions, SiO
The etching selection ratio of ₂ / SiON is 50 or more: 1.

By etching under the above conditions, the connection hole 9 to the lower layer wiring 1 is formed in the inter-wiring space of the wiring pattern 3a. Then, as shown in FIG. 9, the connection wiring portion 10a formed inside the connection hole 9 is formed.
And an upper layer wiring 1 including an upper layer wiring portion 11b connected to the connection wiring portion 10a and formed on the second interlayer insulating film 7.
Form 0. As a result, the lower layer wiring 1 and the upper layer wiring 10 that are electrically connected in the inter-wiring space of the wiring pattern 3a
Then, the wiring pattern 3a insulated from these wirings is formed.

Example 2 In this example, as in Example 1, after forming the contact hole 9 as shown in FIG. 8, the insulating antireflection films 4a and 6a made of SiON exposed in the contact hole 9 were formed. Oxidize. In addition,
In order to avoid the thermal process, the oxidation is performed by low temperature plasma oxidation, for example, under the following conditions.

Plasma device: High-density plasma device such as ECR plasma device Gas: O ₂ = 100 SCCM Pressure: 0.133 Pa (about 1 mTorr) Substrate temperature: Room temperature SiON, which is the insulating antireflection film in Example 1, is
Since it is a Si-rich film as compared with SiO ₂ , there is concern that the withstand voltage will be inferior. On the other hand, as in the present embodiment, by oxidizing the insulating antireflection film after forming the connection hole, the withstand voltage of the insulating antireflection film can be improved.

[0037]

As is apparent from the above description, according to the present invention, when the connection holes are formed between the wiring patterns in a self-aligning manner, the influence of the standing wave effect is reduced and the resist pattern size is reduced. Since it becomes uniform, good connection holes can be formed.

Further, after forming the connection hole, the insulation withstand voltage of the insulation antireflection film can be improved by oxidizing the insulation antireflection film exposed in the connection hole with plasma. .

Therefore, according to the present invention, since a semiconductor device having a finer pattern can be manufactured, high integration of the semiconductor device can be realized.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts showing a step of laminating a first interlayer insulating film, a wiring film, and an insulating antireflection film on a lower layer wiring in an example of a method for manufacturing a semiconductor device to which the present invention is applied. is there.

FIG. 2 is a cross-sectional view of an essential part showing a step of patterning a photoresist film to form a wiring pattern, as a step subsequent to the step shown in FIG.

FIG. 3 is a sectional view of a key portion showing a step of forming a wiring pattern as a step subsequent to the step shown in FIG.

FIG. 4 is a cross-sectional view of essential parts showing a step of forming an insulating antireflection film as a step subsequent to the step shown in FIG.

FIG. 5 is a sectional view of a key portion showing a step of etching back the insulating antireflection film as a step subsequent to the step shown in FIG.

FIG. 6 is a sectional view of a key portion showing a step of forming a second interlayer insulating film as a step subsequent to the step shown in FIG.

7 is a cross-sectional view of a main part showing a step of patterning a photoresist film to form a connection hole, as a step subsequent to the step shown in FIG.

8 is a cross-sectional view of a main part showing a step of forming a connection hole as a step subsequent to the step shown in FIG.

9 is a cross-sectional view of a main part showing a step of forming an upper layer wiring as a step subsequent to the step shown in FIG.

FIG. 10 is a main-portion cross-sectional view showing a step of patterning a photoresist film to form a wiring pattern in an example of a conventional method for manufacturing a semiconductor device.

FIG. 11 is a sectional view of a key portion showing a step of forming a wiring pattern as a step subsequent to the step shown in FIG.

FIG. 12 is a sectional view of a key portion showing a step of forming an insulating film as a step subsequent to the step shown in FIG.

FIG. 13 is a cross-sectional view of an essential part showing a step of etching back the insulating film as a step subsequent to the step shown in FIG.

FIG. 14 is a cross-sectional view of an essential part showing a step of patterning a photoresist film to form a connection hole, as a step subsequent to the step shown in FIG.

FIG. 15 is a sectional view of a key portion showing a step of forming a connection hole as a step subsequent to the step shown in FIG.

[Explanation of symbols]

 1 Lower Layer Wiring 2 First Interlayer Insulation Film 3 Wiring Film 3a Wiring Pattern 4, 4a Insulating Antireflection Film 5 Photoresist Film 6, 6a Insulating Antireflection Film 7 Second Interlayer Insulation Film 8 Photoresist Film 8a Opening 9 connection hole 10 upper layer wiring 10a connection wiring section 10b upper layer wiring section

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/3205 H01L 21/88 B

Claims (5)

[Claims] 1. A step of forming a plurality of wiring patterns on the first interlayer insulating film, the upper surface and side wall surfaces of which are covered with an insulating antireflection film having an etching rate lower than that, and the first interlayer insulating film. A step of covering the wiring pattern with a second interlayer insulating film having an etching rate substantially equal to that of the insulating film; and a step of patterning a photoresist film on the second interlayer insulating film, and between adjacent wirings of the wiring pattern. A step of forming an opening having an opening width equal to or larger than the width of the inter-wiring space facing the space; and forming the second interlayer insulating film and the first interlayer insulating film through the opening. A method of manufacturing a semiconductor device, comprising a step of collectively etching and opening connection holes in the space between the wirings in a self-aligned manner. 2. The coating of the wiring pattern with the insulating antireflection film comprises the steps of laminating the insulating antireflection film on a wiring film forming the wiring pattern, and the wiring film and the insulating antireflection film. It is performed through a step of collectively patterning the film, a step of covering the formed wiring pattern to form an insulating antireflection film again, and a step of anisotropically etching back the insulating antireflection film. The method of manufacturing a semiconductor device according to claim 1, wherein 3. The insulating antireflection film is a SiON based material film, and the first interlayer insulating film and the second interlayer insulating film are SiO based material films. The method for manufacturing a semiconductor device according to claim 2. 4. The method according to claim 1, wherein after forming the connection hole, the insulating antireflection film exposed in the connection hole is oxidized by using plasma. A method of manufacturing a semiconductor device according to item. 5. The photoresist film is 150-450.
patterning is performed through photolithography using exposure light in the wavelength range of nm, and the composition formula SiO _x N _y H _z (where x is 0.30 to 0.70, y
Is 0.05 to 0.30 and z is 0 to 0.50. The method of manufacturing a semiconductor device according to claim 4, wherein a material film represented by (4) is used.