JPH0817822A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To improve the machinability of the upper electrode of an oxide ferroelectric body and at the same time achieve conformity with a contact hole. CONSTITUTION:An upper electrode out of upper and lower electrodes sandwiching a ferroelectric body is in lamination structure of Pt 110 and WSi2 111 and the Pt 110 in contact with a ferroelectric body 109 is thinned. Machinability can be improved by thinning Pt. Also, by using a metal silicide which is not soluble to or is solution-retardant to such fluoric acid solution as WSi2, PdSi2, and PiS for the electrode material of the uppermost layer, W, Ti, TiN, TiW, Al, and Al alloy with improved machinability other than Pt can be utilized for the electrode material under it, thus further improving the machinability of the electrode. Also, the contact hole can be washed by fluoric acid, thus obtaining improved contact characteristics. By using oxide film l 12 with the silicide 111 at the uppermost layer as a machining mask, the residue of a side-wall deposit onto a pattern can be prevented even if Pt is used as an upper lamination electrode material.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor memory device having a ferroelectric element and a manufacturing method thereof.

[0002]

2. Description of the Related Art Currently, nonvolatile memories utilizing the polarization characteristics of ferroelectrics have been proposed. Pb as ferroelectric
FIG. 2 shows an example of a capacitor element structure using (Zr, Ti) ₃ (hereinafter abbreviated as PZT). Semiconductor substrate 201, LO
After forming the underlying transistor layer including the COS oxide film 202, the gate oxide film 205, the poly-Si gate electrode 204, and the source / drain diffusion layer 203, an interlayer film 206 is formed to separate the underlying transistor layer from the capacitive element layer. A Pt lower electrode 207 is formed thereon, a PZT film 208 is formed thereon by sputtering or spin coating and oxygen annealing, and a Pt upper electrode 209 is formed thereon by sputtering, and a resist is formed by milling. Patterning is performed using a mask to form a capacitor. After annealing in oxygen, an oxide film 210 is formed, a contact hole is formed, and a barrier metal and an Al-based wiring 211 are formed.

According to Japanese Patent Application Laid-Open No. Hei 5-90606, a two-layer structure in which MoSi ₂ is disposed as an upper layer and Pt as a lower layer is proposed as an upper electrode in order to prevent a reaction between an Al wiring and Pt. Has a Pt film thickness of 300 nm and MoSi
_Since the thickness of No. ₂ is 50 nm and Pt is quite thick, processing becomes difficult as described below.

[0004]

In the case of a structure in which a ferroelectric material is sandwiched between upper and lower electrodes, the electrode material is Pt, which is a material having high oxidation resistance or a material which does not become an insulator even when oxidized. Is desirable. Pt is not oxidized even in a high-temperature oxygen atmosphere, has a high melting point, and has little adverse effect on the quality of the dielectric film and, consequently, on the performance of the capacitive element. Therefore, Pt is used as an electrode material for a ceramic ferroelectric capacitive film. It is difficult to generate elements and compounds, and it is difficult to process a Pt electrode by ordinary reactive dry etching. Therefore, in the prior art, a method is employed in which Pt is processed by sputtering with primary ions reaching the surface by milling or reactive etching to which a large high-frequency power is applied. However, the sputtered Pt
Has a problem that it is deposited on the mask side wall and remains on the pattern even after the resist mask is removed, which hinders fabrication of a fine and highly integrated circuit.

The present invention utilizes Pt or a metal material having high workability as an electrode of a ferroelectric capacitor, improves the workability of an upper electrode, and matches with the conventional Si integrated circuit manufacturing process. The purpose is to measure.

[0006]

The present invention is characterized in that the upper electrode of the ferroelectric substance is a metallic film having a multi-layered structure and the uppermost layer is a metal silicide insoluble or dissolvable in hydrofluoric acid aqueous solution. To do. WSi ₂ , P
dSi ₂ , PtSi or the like is used.

Further, the present invention is characterized in that the material of a layer below the uppermost layer of the upper electrode having a laminated structure is a metal having high workability.

Further, the present invention is a method for manufacturing a semiconductor device, wherein a processing mask of the uppermost layer material of the above-mentioned upper electrode is formed of two layers of an oxide film or a nitride film and a resist, and the multilayer upper electrode is processed. .

[0009]

The upper electrode has a multi-layer structure and the uppermost silicide layer is thicker than the lower layer, so that even if Pt is used as the lower layer, the thickness of the Pt to be patterned becomes smaller. It will be easier. The connection between the upper electrode and the silicon substrate is made by wiring with an Al-based metal for the convenience of the circuit. However, when the thickness of Pt is reduced and a metal such as Ti or Al is used as the uppermost layer, the interlayer film is formed. Treatment of contact holes
Do not use hydrofluoric acid-based chemicals for cleaning. By using a silicide that is insoluble or exfoliated in the hydrofluoric acid aqueous solution for the uppermost layer, cleaning and surface treatment with the hydrofluoric acid cleaning liquid in the contact hole becomes possible.

Since the upper electrode is processed using the oxide film or the nitride film as a mask, the thickness of the mask is thinner than that of the resist, and the oxide film or the nitride film on the uppermost layer of the mask is hardly etched by a dry etching gas such as chlorine. Sidewall deposits formed by the attachment of the etching species during etching do not remain on the top surface of the pattern.

[0011]

FIG. 1 shows an embodiment in which the structure of claim 1 is formed by the method of claim 3. FIG. First, in the conventional way,
LOCOS oxide film 1 for element isolation on silicon substrate 101
02 and a transistor, and an oxide film 12 as an interlayer film.
Is formed to a thickness of 500 nm by CVD (FIG. 1 (1)). First, Ti107 is 50 nm as a lower electrode of the capacitor, and then Pt108
Is formed to a thickness of 200 nm. Then, P
ZT109 is formed to a thickness of 200 nm. After that, PZT / P
The t / Ti film is patterned by milling ((2)
Figure). On top of that, first, a Pt110 film to be a part of the upper electrode is formed to a thickness of 50 nm, and a tungsten silicide 111 is
Perform nm sputtering film formation. Next, an oxide film 112 having a thickness of 200 nm is formed thereon, and the oxide film is patterned using a resist mask. Subsequently, the tungsten silicide 111 and Pt 110 are etched and patterned using the patterned oxide film as a mask (FIG. 3C). Next, CV
A D oxide film 113 is formed to a thickness of 300 nm to form a contact hole. After cleaning with a hydrofluoric acid-based cleaning liquid, a TiN film / Ti film 114 is formed and sintered as a barrier metal.
The system metal wiring 115 is formed.

[0012]

The effect of the present invention is that the film thickness of Pt is as small as 50 nm.
Due to the presence of 300 nm tungsten silicide,
After the tungsten silicide etching, the side wall of Pt which is sputter-etched adheres to and remains on the side wall portion of the tungsten silicide, and does not remain on the resist mask.

The Pt of the upper electrode is W, Ti, Ti
By replacing with N, TiW, Al, and Al alloy, it was possible to process without forming sidewall deposits.

Even if a contact hole is opened in the interlayer film with the Al wiring and the inside of the contact hole is washed with dilute hydrofluoric acid, the tungsten silicide is not eroded, and the effect of washing the interface between the substrate and the barrier metal is not impaired. And good contact characteristics were obtained. Similar effects were obtained by using PdSi ₂ and PtSi instead of tungsten silicide.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating an embodiment in which the structure of claim 1 of the present invention is formed by the method of claim 3.

FIG. 2 is a cross-sectional view of a semiconductor device illustrating a conventional technique.

[Explanation of symbols]

101, 201 Semiconductor substrate 102, 202 LOCOS oxide film 103, 203 Source / drain diffusion layer 104, 204 Gate polysilicon 105, 205 Gate oxide film 106, 206 Transistor capacitor and interlayer film 107 for isolation thereof Lower electrode 11 108, 207 Lower electrode Pt 109, 208 PZT film 110, 209 Upper electrode Pt 111 Upper electrode tungsten silicide 112 Mask oxide film 113, 210 Wiring / element interlayer film 114 TiN / Ti barrier film 115, 211 Al-based metal wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 27/04 21/822 21/8242 27/108 27/10 451 21/8247 29/788 29 / 792 H01L 27/10 325 J 29/78 371

Claims (3)

[Claims] 1. In a semiconductor device in which a ferroelectric is integrated on a semiconductor substrate, the structure of the upper electrode of the upper and lower electrodes sandwiching the ferroelectric is a laminated structure, and the material of the uppermost layer of the upper electrode is A silicide that is insoluble or exfoliated in hydrofluoric acid,
A semiconductor device, wherein the uppermost silicide layer is thicker than the lower layer. 2. The method according to claim 1, wherein the layers other than the uppermost layer in the upper electrode are W,
2. The semiconductor device according to claim 1, wherein the semiconductor device is formed of a multilayer film made of one or more of Ti, TiN, TiW, Al, and an Al alloy. 3. The method of manufacturing a semiconductor device according to claim 1, wherein a silicon oxide film or a silicon nitride film is formed on a silicide which is an uppermost layer of the upper electrode, and the silicon oxide film or the silicon oxide film is formed by a resist mask. A method of manufacturing a semiconductor device, comprising patterning a silicon nitride film and a silicide, and subsequently patterning the upper electrode using the patterned silicon oxide film or silicon nitride film as a mask.