JPH081742B2 - Recording and playback device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording / reproducing apparatus such as a rotary head type digital tape recorder used for electronic editing or the like.

2. Description of the Related Art Conventionally, a time code is recorded as time information in a device for broadcasting business, and a cue at the time of recording / reproducing or an electronic editing process is performed by this time code. Moreover, in the case of audio editing, the editing accuracy is 1 frame or less, for example, 1/10.
~ 1/100 frame accuracy is often required. Therefore, when the rotary head type digital recording / reproducing apparatus is used for broadcasting, it is necessary to record the time code corresponding to the PCM signal with high accuracy. For example, a so-called PCM that records PCM audio signals on a 3 / 4-inch video tape recorder.
In the processor, the NTSC system records the SMPTE time code in the longitudinal direction of the tape with a fixed head, so that high-precision editing is possible as with a normal video tape recorder. Also, so-called memory rehearsal has been performed in which a PCM signal is stored in a storage device and its address is manipulated to repeatedly reproduce and determine an editing point, thereby efficiently performing rehearsal of electronic editing.
This PCM processor has a cylinder equipped with a rotary head, but its rotation speed is 1800, which is the same as that of a normal video tape recorder, so it was easy to operate the PCM processor and the video tape recorder in synchronization.

On the other hand, in recent years, digital audio tape recorders (DA
T) has been proposed and commercialized for consumer use.

Figure 11 shows an example. In FIG. 11, the PCM audio signal A / D converted by the A / D converter 1 is a signal processing circuit.
Added to 59. In the signal processing circuit 59, parity for error correction is added, and after 8-10 modulation, a signal for tracking is added. After that, the PCM audio signal is supplied to the head 21 of the cylinder 6 via the recording amplifier 5. Further, the signal processing circuit 59 generates a rotation synchronizing signal (100/3 Hz) 32, which is a recording frame of the cylinder 6, and supplies it to the system control circuit 11 and the servo circuit 25. The servo circuit 25 controls the speed and phase of the cylinder 6 and the capstan motor 27, and also controls the reel motors 28 and 29.

The reproduction signal from the head 21 is a reproduction amplifier / equalizer 7
The signal processing circuit 59 demodulates the signal and the signal is subjected to 10-8 demodulation, is error-corrected, and is supplied to the D / A converter 10.

Problems to be Solved by the Invention However, in the case of configuring a business system using DAT, the following problems occur.

(1) The frame frequency of DAT is 100 / 3Hz, while
In a video tape recorder, in the case of NTSC color, the frame frequency is 29.97 Hz, so the frame frequencies do not match and it is difficult to synchronize the two.

(2) Since the frame frequency of the time code is also different, it is difficult to maintain the relative accuracy between the SMPTE time code and the PCM audio signal during recording and reproduction.

(3) When SMPTE time code is recorded directly in the longitudinal direction of the tape, it is necessary to handle two different frame frequencies (100 / 3Hz for DAT, 29.97Hz for NTSC color) in the editing process, so memory rehearsal and editing Processing becomes complicated.

Further, in the configuration of FIG. 11, the following problems occur with respect to memory reproduction and editing.

(4) Since a so-called semiconductor memory or the like for temporarily storing PCM audio signals is not provided, a memory reproduction process such as a memory rehearsal cannot be performed.

(5) The so-called editing process that continuously records the input PCM audio signal from the arbitrary time code point on the tape to the recorded PCM audio signal without any abnormal sound cannot be performed.

(6) At the time of editing, so-called phase adjustment processing in which the playback time code and the playback PCM audio signal are made to follow the time code input from the outside to run is not possible.

In view of the above problems, the present invention, as a time code recording means, converts SMPTE time code to DAT time code,
A method for recording the phase difference between the converted time code frame and the DAT frame at the time of recording, for example, a system for performing high-precision memory reproduction processing, editing processing, and phase adjustment processing using Japanese Patent Application No. 63-24229 is provided. An object is to provide a recording / reproducing device.

Means for Solving the Problems In order to solve the above problems, in the recording / reproducing apparatus of the present invention, a first time code corresponding to input information divided into frames has a frame frequency different from that of the input time information. Conversion means for converting to a second time code, recording / reproducing means having a recording frame of the same frequency as the second time code, phase for detecting a phase difference between the frame of the second time code and the recording frame A detecting means, and the recording / reproducing means includes the input information and the second information.
Recording the time code and the phase difference, reproducing the recorded input information, the second time code and the phase difference,
At least one of the information storage means for storing the input information and the information storage means for storing the reproduction information, and the address reading means for reading the address of the information storage means, the information storage corresponding to the first time code. The address of the means is the address at the rising or falling point of the recording frame, the second time code at the rising or falling point, the second time code corresponding to the first time code, and the second time code. The present invention is characterized in that the recording / reproducing start point is determined by including an address calculating means obtained from the phase difference.

Further, according to the present invention, a converting means for converting a first time code corresponding to the input information divided into frames into a second time code having a frame frequency different from the input time information, and the second time code. Recording / reproducing means having a recording frame of the same frequency, and phase detecting means for detecting a phase difference between the frame of the second time code and the recording frame. Record the second time code and the phase difference,
At least one of the information storage means for reproducing the input information, the second time code, and the phase difference recorded, and storing the input information, and the address of the information storage means. Address reading means, means for performing crossfading of input information, address storage means for storing a memory address for starting the crossfade, addresses read by the address reading means and the address storage means. Comparing means for performing a match comparison of existing addresses,
The address for starting the crossfade is the address at the rising or falling point of the recording frame,
It is characterized in that it is provided with the second time code at the rising or falling point and an address calculating means for obtaining from the reproduced phase difference.

Further, according to the present invention, a converting means for converting a first time code corresponding to the input information divided into frames into a second time code having a frame frequency different from the input time information, and the second time code. Recording / reproducing means having a recording frame of the same frequency, and phase detecting means for detecting a phase difference between the frame of the second time code and the recording frame. Record the second time code and the phase difference,
Information storage means for reproducing the recorded input information, the second time code, and the phase difference and storing the reproduction information, and a relative address setting for relatively changing the address for writing the reproduction information in the information storage means. Means is provided, and the relative address is obtained from the reproduced second time code, the second time code and the phase difference.

Effect The present invention converts the input time code frame into a time code having the same frame frequency as the recording frame even when the frame frequency of the input time code and the frame frequency of the recording means are different due to the above-described structure, thereby converting the time code frame. And the frame of the PCM data stored in the memory can be matched, and when an arbitrary input time code is given, the input time code is converted by the phase difference between the converted time code and the converted time code. Since it can be represented, the correspondence between the input time code and the PCM sample is accurately defined. Therefore, the correspondence between the address of the information storage means for storing the input information or the reproduction information and the input time code is accurately specified.

Further, since the memory address corresponding to the edit point can be defined by the time code of the recording frame and the phase difference, the memory address can be controlled at the edit point in accordance with the time code at the time of recording.

Further, since the relative address of the memory can be obtained from the reproduced time code and the phase difference, the reproduction information and the reproduction time code can be accurately tuned to the time code input from the outside.

First Embodiment FIG. 1 is a block diagram showing a recording / reproducing apparatus according to a first embodiment of the present invention. In FIG. 1, the basic recording / reproducing function is the same as that of the conventional example shown in FIG. Therefore, the A / D converter 1, the recording amplifier 5, the reproduction amplifier equalizer 7, the D / A converter 10, the servo 25, the capstan motor 27, and the reel motors 28 and 29 are the same as those shown in FIG. Is. However, it is possible to perform memory reproduction processing.

First, the outline of the processing will be described. In FIG. 1, the input analog signal is A / D converted by the A / D converter 1, input to the source memory 2, and then supplied to the switch 69. Unlike the conventional example shown in FIG. 11, the cylinder 6 has a pair of preread (hereinafter referred to as head) heads 22 and a pair of follow-up recording (hereinafter referred to as trailing) heads so that editing can be performed. The head 23 is attached. The signal reproduced from the preceding head 22 is amplified and waveform-shaped by the reproduction amplifier equalizer unit 7, 10-8 demodulated by the second signal processing unit 8, error-corrected and added to the tape memory unit 9, and if necessary. Accordingly, data for several seconds is stored.
One of the output signals from the source memory unit 2 and the tape memory unit 9 is selected by the switch 69.

At the edit point, the switch 69 switches from the output signal of the tape memory unit 9 to the output signal of the source memory unit 2. After that, the first signal processing unit 4 adds parity for error correction and after 8-10 modulation, a tracking signal is added and supplied to the trailing head 23 of the cylinder 6 via the recording amplifier 5. It

Further, the output of the switch 69 is added to the D / A conversion unit 10 and the D / A
To be converted.

In FIG. 1, an input time code 30 supplied as a bi-phase signal from a VTR or another DAT is read by a time code input unit 14 including a demodulator for demodulating the bi-phase signal, and the read time code 30 is read.
34 is sent to the time code conversion unit 16. Here, the frame phase of the input time code 30 and the read time code 34
Have the same frame phase. Input time code 34 or composite sync signal as external frame reference signal
Either 59 can be selected with switch 35, and phase detector
Added to 15. The phase detector 15 detects the phase information 60 of the external frame reference signal, that is, the read time code 34 or the composite sync signal 59 and the recording frame, that is, the rotation sync signal 32, and sends it to the time code converter 16.
In the time code conversion unit 16, the read time code 34 and the phase information 60 are converted from the frame period of the input time code 30 into the recording time code 36 having the period of the recording frame having the cylinder rotation period and the phase difference 41. As this conversion method, for example, Japanese Patent Application No. 63-24229 can be used.

FIG. 2 shows the input time code 30, the converted time code 67, the recording time code 36, and the phase difference 41 in the above case.
The timing of is shown. Figure 2 shows that the input time code is SM
It shows the case of PTE (drop frame mode),
Its period is 33.37 ms. Also, the frame numbers of the SMPTE time code are S0, S1, S2, ... And the frame numbers of the converted time code are D0, D1, D2 ,. The phase information 60 shown in FIG. 1 is shown as Ph1, Ph2, etc. in FIG. The converted recording time code 36 and phase difference 41 are added to the system controller 11. The system control unit 11 sends the recording time code 36 and the phase difference 41 as sub data 55 to the first signal processing unit 4. In the first signal processing unit 4,
The sub data 55 and the output PCM signal of the switch 69 are recorded on the tape.

On the other hand, the sub-data 56 reproduced from the tape by the second signal processing unit 8 is sent to the system control unit 11 for decoding, and the time code 38 having the same frequency as the recording frame, that is, the rotation synchronizing signal 32 and the phase difference 42. Are sent to the time code inverse conversion unit 17. The time code inverse conversion unit 17 converts the time code 38 and the phase difference 42 into the time code 40 and the phase information 46 having another frame period. This phase information 46 corresponds to Ph1 'and PH2' in FIG. The time code 40 is sent to the time code output unit 19. Phase generator
18 is a frame synchronization signal 39 that matches the phase of the output frame with the phase at the time of recording based on the phase information 46 and the rotation synchronization signal 32.
Is supplied to the time code output unit 19. As a result, the frame phase of the output time code 31 is determined. The time code output unit 19 outputs an output time code 31 having the same phase as the time code 30.

The source memory unit 2 is controlled by the memory address command calculated by the system control unit 11 based on the time code. The memory address is assumed to circulate from address 0 to a fixed value. The tape memory unit 9 is also controlled by the memory address command calculated based on the time code in the system control unit 11 like the source memory unit 2. In FIG. 1, the address is loaded from the system control unit 11 into the first load register 47 and the initial value of the first counter 46 is given. The first counter 46 provides the source memory unit 2 with an absolute address. On the other hand, the absolute address is read by the first read register 45 and sent to the system controller 11. Further, the first relative address register 48 gives the offset address value of the source memory unit 2. The second load register 50, the second counter 51, the second read register 49, and the second relative address register 52 are respectively the first load register 47, the first counter 46, the first read register 45, The tape memory unit 9 performs the same operation as the first relative address register 48.
Do to.

An address calculation method for memory reproduction of data reproduced from a tape with the configuration shown in FIG. 1 will be described with reference to FIGS. 1, 3 and 4. FIG. 3 shows the system control unit 11 described above.
FIG. 4 shows the processing flow chart of FIG. 4, and FIG. 4 shows the correspondence between time codes and addresses.

(Step 1) Obtain the SMPTE time code when registering the edit point.

(Step 2) The registered edit point given by the SMPTE time code is recorded by the method shown in Japanese Patent Application No. 63-24229, for example, the time code (67 in FIG. 2) having a recording frame, that is, the DAT frame, and the phase difference ( It is converted to 41) in Fig. 2 and the time code 67 and phase difference 41 are combined and re
It is written as ntryir.

(Step 3) Obtain a write end address (write start address) rtapema and a write end DAT time code rtapemt when the PCM data from the tape via the reproduction amplifier equalizer 7 and the second signal processing unit 8 is written in the tape memory 9. . Write end address above rtapema
Is read from the second read register 49 and sent to the system controller 11. On the other hand, the above writing end DAT
The time code rtapemt is sent to the system control unit 11 via the reproduction amplifier equalizer 7 and the second signal processing unit 8.

(Step 4) DAT time code rtape at the writing end point
The time code rtbltc at the memory writing start point is calculated from mt.

(Step 5) The relative address rtirad of the registered edit point is calculated from the time code rtbltc of the memory writing start point and the time code of the registered edit point (including phase information) rentryir. The address of the registration edit point is obtained by the sum of the write start address rtapema and the relative address rtirad.

The registered edit point time code rentrir is converted into the registered edit point memory address by the steps (1) to (5). In the memory reproduction, the address corresponding to the registered edit point is written in the second load register 50.
As a result, the second counter 51 sequentially generates a read address for a predetermined time, for example, 2 seconds, and gives it to the tape memory 9. In this case, for example, the resolution of the phase difference 41
1440th of DAT1 frame period (30ms), that is, 20.83μ
If s is set and the memory address is controlled in units of 20.83 μs, the memory address can be controlled with a resolution of 20.83 μs. The above accuracy can be realized without much difficulty. Therefore, it is possible to obtain the image with a high precision of 1440 of one frame. By the operation described above, the PCM data is sequentially read from the tape memory unit 9 and reproduced. The source memory unit 2 performs the same operation, but in this case, the first read register 45, the first load register 47, and the first counter 46 can be used.

Next, as a second embodiment of the present invention, an operation when the present DAT is used as an editing machine will be described. At a predetermined time code, the editing machine performs the operation of continuously recording the sound reproduced from the tape of the recorder itself, that is, the sound from the outside, for example, the player in this case, by the crossfader section without abnormal noise and recording it on the tape of the recorder. . FIG. 5 shows the configuration of the second embodiment.

In the configuration shown in FIG. 5, a comparator 61 and a comparison value register 6 are used instead of the switch 69 in the configuration shown in FIG.
2. The crossfader 3 is connected, and the output signals from the source memory unit 2 and the tape memory unit 9 are crossfaded by the crossfader 3. The memory address to be cross-fade set in the comparison value register 62 from the system control unit 11 is compared with the memory address 63 of the source memory unit 2 by the comparator 61, and when both match, a flag is generated in the comparator 61. Then
The crossfader 3 is instructed to start the crossfade. FIG. 6 shows an algorithm for calculating the memory address in the editing process, and FIG. 7 shows the timing of the time code. In FIG. 7, the tape reproduction time code 75 corresponds to the SMPTE time code 73 at the time of recording, and the SMP
TE time code 73 is, for example, according to Japanese Patent Application No. Sho 63-24229.
Converted to time code 74 with DAT frames. The edit point is indicated by 70, and the time at which the memory address is set is indicated by 71, that is, the frame (L-2). The outline steps are shown below.

(Step 1) Time code of edit point given by SMPTE time code (K for frame, subframe for
adrsmp) is converted into a recording frame, that is, a DAT frame (L in FIG. 7) and phase information (adra in FIG. 2).

(Step 2) The recording mode, that is, the cross-faded signal is displayed in the following head 59 a few frames before the editing point.
Set to the recording mode.

(Step 3) The memory address at the crossfade point is calculated and set in the comparison value register 62. If the address set in the comparison value register is reditadr, reditadr will subtract the phase information rpia72 recorded on the tape from the difference adrsubs77 between the point 71 for setting the address and the editing point 70 as an offset to the memory address rscwradr. It can be obtained by adding. That is, if the memory address at the address set point read by the first read register 45 is rscwadr, it is expressed as reditadr = rscwradr + adrsubs-rpia (1). In addition, in FIG. 7, the adrsubs77 adds adra76 to the memory address of two frames, and
Since the time code corresponding to the edit point 70 is known (L) for the address of 2 frames at this time because it is obtained by subtracting ia72, the time code (L-2) of the address set point 71 is obtained. For example, it can be easily obtained from the memory address corresponding to one frame. That is, it is obtained from the address of the address set point 71, the time code, and the reproduced phase difference. The address represented by the equation (1) is set in the comparison value register 62. Address of source memory unit 2
63 and the address set in the comparison value register 62 are compared by the comparator 61, and when they match each other, a flag 64 is generated and a crossfade is applied in the crossfade section 3. Now, in this case, the designated resolution of the editing point and the editing accuracy are determined by the accuracy of the adra76 of the time code 74 after conversion into the DAT frame, as is clear in FIG. That is, the editing accuracy is determined by the resolution of the phase difference 41. For example, if the resolution of the phase difference 41 is 1440th of DAT1 frame, that is, 20.83 μs, the editing accuracy is 20.83.
High precision of μs can be obtained.

Next, as a third embodiment of the present invention, a case of a phase adjusting process will be described. The phase adjusting process is a process in which the PCM data and the time code reproduced from the DAT are caused to follow a time code input from the outside by giving a predetermined offset time code. FIG. 8 shows the configuration, FIG. 9 shows the processing flow, and FIG. 10 shows the timing of the time code. The player side phase adjusting process at the time of editing will be described below.

In FIG. 10, consider the case where the PA of the external time code 30 and the PB of the reproduction time code are matched by the phase adjustment. In advance, advance the time code of the player from the time code of the phase adjustment target point input from the outside.

(Step 1) The phasing target point SMPTE time code 30 (frame is n + 1, phase information is Phn) is sent to the time code conversion unit 16 by the method shown in Japanese Patent Application No. 63-24229, for example. To a recording frame, that is, a DAT frame (m in FIG. 10).
+1) and the phase difference SNR (78 in FIG. 10)).
The frame m + 1 and the phase difference SNR are combined and referred to as tcser. These are DAT time code 36 and phase difference 41 after conversion.
Is added to the system control unit 11.

(Step 2) of the time code 80 reproduced from the tape
The DAT frame (P + 1 in FIG. 10) and the phase difference SNR (81 in FIG. 10) are collectively referred to as rpiltc. The time code tcser of the above target point is subtracted from rpiltc, and this is the memory delay amount r
tpdls.

(Step 3) The memory delay amount rtpdl is set in the second relative address register 52. When the memory delay amount rtpdl is set in the second relative address register 52, the second
Address 65 set by counter 51 and adder 54
Is added to become the address 66 and is added to the tape memory unit 9. As a result, the PCM signal applied to the tape memory unit 9 through the reproduction amplifier equalizer 9 and the second signal processing unit 8 is delayed by the memory delay amount represented by the equation (2) and sent to the switch 69. . The output PCM signal from the switch 69 is supplied to the D / A converter 10 and converted into an analog signal. In this case, the memory delay amount rtpdl determines the phase adjustment accuracy. That is, the phase difference SN in FIG. 10 determines the phase adjustment accuracy. For example, if 1/4 1440 of the DAT1 frame is used as the phase difference 41, a 20.83 μs NO phase adjustment accuracy can be obtained.

EFFECTS OF THE INVENTION As described above, the conversion means for converting the first time code corresponding to the input information divided into frames into the second time code having a frame frequency different from the input time information, and the second time code. The recording means has a recording frame having the same frequency as the time code, and a phase detecting means for detecting a phase difference between the frame of the second time code and the recording frame, the recording means comprising the input information and the first information. 2 time code and the phase difference are recorded, the recorded input information, the second time code and the phase difference are reproduced, and information storage means for storing the input information or information storage means for storing the reproduction information. And an address control means for controlling the address of the information storage means by the second time code and the phase information. An address reading means for reading the address of the information storage means is provided, and the address of the information storage means corresponding to the first time code is set to the address at the rising or falling point of the recording frame and the rising or Information storage for storing the input information by providing the second time code at the falling point, the second time code corresponding to the first time code, and the address calculation means obtained from the phase difference A memory is used as a means, and its address can be controlled to an accuracy of one frame or less by the second time code and the phase difference. For example, if 1440th of one frame is used as the resolution of the phase difference, it is possible to control the memory address to the precision of 1440th of one frame. Can be done with precision.

Address reading means for reading the address of the information storage means, means for crossfading the input information, address storage means for storing a memory address for starting the crossfade, and address read by the address reading means. And comparison means for performing a match comparison of the addresses stored in the address storage means,
The address for starting the crossfade is the address at the rising or falling point of the recording frame,
By providing the second time code at the rising or falling point and the address calculating means obtained from the reproduced phase difference, the editing point can be controlled to an accuracy of one frame or less. For example, if 1 / 140th of one frame is used as the resolution of the phase difference, the memory address becomes 1
Since it is possible to control to an accuracy of 1/440 of a frame, editing can be performed with high accuracy.

Further, the information storage means is provided with a relative address setting means for relatively changing an address for writing the input information, and the relative address is reproduced with the reproduced second time code, the second time code and the relative time. By obtaining it from the phase difference, the phase adjustment can be controlled to an accuracy of 1 frame or less. For example, if 1440th of one frame is used as the resolution of the phase information, the memory address of one frame is
Since it is possible to control to an accuracy of 1/440, it is possible to perform phase adjustment with high accuracy.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a recording / reproducing apparatus in a first embodiment of the present invention, FIG. 2 is a timing diagram of time code and phase information of the present invention, and FIG. 3 is a memory reproducing process of the present invention. FIG. 4 is a flowchart showing the memory address calculation algorithm of FIG. 4, FIG. 4 is a relational diagram of the time code and the address of the present invention, FIG. 5 is a block diagram showing the configuration of the second embodiment of the present invention, and FIG. 6 is the present invention. 7 is a flow chart showing a memory address calculation algorithm of the editing process of FIG. 7, FIG. 7 is a timing diagram of the time code of the present invention, FIG. 8 is a block diagram showing the configuration of the third embodiment of the present invention, and FIG. 9 is the present invention. 10 is a flow chart showing a memory address calculation algorithm of the edit phase adjusting process of FIG. 10, FIG. 10 is a timing diagram of the time code of the present invention, and FIG. 11 is a block diagram showing a configuration of a conventional DAT. 2 ... Source memory part, 3 ... Crossfader part, 9 ...
… Tape memory unit, 11 …… System control unit, 15 …… Phase difference detection unit, 16 …… Time code conversion unit, 17 …… Time code inverse conversion unit, 18 …… Phase generation unit, 45 …… First Read register, 46 ... First counter, 47 ... First load register, 48 ... First relative address register, 49 ...
... second read register, 50 ... second load register, 51 ... second counter, 52 ... second relative address register, 61 ... comparator, 62 ... comparison value register.

Claims (3)

[Claims] 1. A conversion means for converting a first time code corresponding to input information divided into frames into a second time code having a frame frequency different from the input time information, and the second time code. The recording / reproducing means has a recording frame having the same frequency and a phase detecting means for detecting a phase difference between the frame of the second time code and the recording frame. 2 time code and the phase difference are recorded, the recorded input information, the second time code and the phase difference are reproduced, and information storage means for storing the input information or information storage means for storing the reproduction information. At least one of the above and an address reading means for reading the address of the information storing means, and the information storing means corresponding to the first time code. The address at the rising or falling point of the recording frame, the second time code at the rising or falling point, the second time code corresponding to the first time code, and the phase difference. A recording / reproducing apparatus, characterized in that the recording / reproducing start point is determined by including an address calculation means obtained from the above. 2. A conversion means for converting a first time code corresponding to input information divided into frames into a second time code having a frame frequency different from the input time information, and the second time code. The recording / reproducing means has a recording frame having the same frequency and a phase detecting means for detecting a phase difference between the frame of the second time code and the recording frame. 2 time code and the phase difference are recorded, the recorded input information, the second time code and the phase difference are reproduced, and information storage means for storing the input information or information storage means for storing the reproduction information. At least one of the above, an address reading means for reading an address of the information storage means, a means for performing a crossfade of the input information, and a crossfade An address storage unit for storing a memory address to start, a comparison unit for comparing and matching the address read by the address reading unit with the address stored in the address storage unit, and an address for starting the crossfade. It is characterized by further comprising an address at a rising or falling point of the recording frame, the second time code at the rising or falling point, and an address calculating means obtained from the reproduced phase difference. Recording / playback device. 3. A conversion means for converting a first time code corresponding to input information divided into frames into a second time code having a frame frequency different from the input time information, and the second time code. The recording / reproducing means has a recording frame having the same frequency and a phase detecting means for detecting a phase difference between the frame of the second time code and the recording frame. 2 time code and the phase difference are recorded, the recorded input information, the second time code and the phase difference are reproduced, and the reproduction information is stored in the information storage means and the information storage means. Is provided with relative address setting means for relatively changing the address to write the relative address to the reproduced second time code and the second time code.
A recording / reproducing apparatus, which is obtained from the time code and the phase difference.