JPH08172174A - Nonvolatile semiconductor storage device and its manufacture - Google Patents

Abstract

PURPOSE: To provide a nonvolatile semiconductor storage device wherein punch through between neighboring memory element parts is restrained, without deteriorating memory cell area reduction. CONSTITUTION: Source lines and bit lines are arranged in parallel on a substratum 1. A plurality of memory element parts are adjacently arranged between the lines. Trenches 20 are formed between the adjacent memory element parts, which are isolated by the trenches 20. A floating gate layer, a second insulating layer and a control gate layer are etched by using a mask, and a floating gate 14, a second insulating film 15 and a control gate 16 are formed by patterning. The trenches 20 are formed between the drain regions and the source regions of the substratum 1 by performing etching in the self-alignment manner using a mask 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device such as an EPROM, and more particularly to a non-volatile semiconductor having a structure in which a source line and a bit line are formed in parallel and a contact hole is not formed in a memory element portion. The present invention relates to a memory device and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, as a non-volatile semiconductor memory device such as an EPROM (hereinafter abbreviated as a memory device), impurities are diffused in a substrate made of, for example, a silicon wafer to form a source line and a bit line in parallel. However, there is known a structure in which a memory element portion is formed between the source line (source region) and the bit line (drain region). (H.Kumee
tal, “A 1.28μm ² ContactlessMemory Cell Technolo
gy for a 3V-only 64Mbit EEPROM ”, 1992 IEDM Tech.Di
g., P.991-993), (YSHisamune et al, “A High Cap
acitive-Coupling Ratio (HiCR) Cell for a 3V-only 6
4Mbit and Future Flash Memories ”, 1993 IEDM TECH.D
ig., P.19 to 22) In the memory device having such a structure, the memory element portion is formed between the source line and the bit line. It is said that the area of the memory cell is smaller than that of a memory device having a normal contact because it does not have a contact in the memory cell, and it is advantageous for high integration of the memory device.

A method of manufacturing such a storage device is shown in FIG.
(A)-(g), FIG. 4 (a)-(e), FIG. 5 (a),
This will be described with reference to (b). Note that FIG. 3 is a cross-sectional view of a main part of the storage device, and is a cross-sectional view taken along the line AA in FIG. 4 (e), and FIGS.
FIG. 5A is a plan view of a main part of the storage device, and FIGS. 5A and 5B are side cross-sectional views of the main part of the storage device. FIG. FIG. First, FIG.
As shown in (a), a LOCOS oxide film 2 is formed on a semiconductor substrate (base) 1 made of a silicon wafer by the LOCOS method, and element isolation is performed.

Next, a thermal oxide film and a silicon nitride film are sequentially formed in the element region surrounded by the LOCOS oxide film 2, and these are patterned by using a photolithography technique and a dry etching technique. A thermal oxide film 3 and a silicon nitride film 4 having a predetermined pattern as shown in FIG. 4A are formed. Here, in order to relax the stress of the silicon nitride film 4, polycrystalline silicon may be formed between the thermal oxide film 3 and the silicon nitride film 4. Subsequently, phosphorus is ion-implanted using the silicon nitride film 4 as a mask, and ion-implanted portions 5 and 5 are formed in the surface layer portion of the substrate 1 so as to be parallel to each other with the silicon nitride film 4 interposed therebetween.

Next, thermal oxidation is performed using the silicon nitride film 4 as a mask to form oxide films 6, 6 as shown in FIGS. 3 (c) and 4 (b). Then, due to such thermal oxidation, the ion-implanted portions 5 and 5 shown in FIG. 3B below the oxide films 6 and 6 become diffusion layers by thermally diffusing the implanted ions. The diffusion layer thus formed serves as a source region and a drain region, and these serve as a source line and a bit line in the obtained memory device. Hereinafter, in the present specification, the diffusion layers are referred to as the source line 7 and the bit line 8, and the reference numerals are shown in the drawings. The source line 7 and the bit line 8 are also formed in parallel because the ion implantation portions 5 and 5 are formed in parallel with each other.

Next, the silicon nitride film 4 and the thermal oxide film 3 are etched and removed as shown in FIGS. 3D and 4C, and further thermal oxidation is performed to remove the thermal oxide film 3. A tunnel oxide film 9 is formed at the mark position as shown in FIG. In the present invention, the tunnel oxide film 9 and the oxide film 6 are collectively referred to as a first insulating film. Then, as shown in FIG. 3F, a low pressure (thermal) CVD is performed on the oxide films 6 and 6 and the tunnel oxide film 9.
Polycrystalline silicon is deposited by the method to form the floating gate layer 10, and then the floating gate layer 10 is patterned by using a lithography technique and an etching technique. The patterning at this time is not performed until the floating gate layer 10 is separated in the direction orthogonal to the length direction of the source line 7 and the bit line 8 as shown in FIG.

Next, the floating gate layer 10
An oxide film made of SiO ₂ is formed on the
Then, a nitride film made of Si ₃ N ₄ is sequentially deposited by a low pressure (thermal) CVD method, and an oxide film made of SiO _{2 is} further sequentially deposited by a thermal oxidation method or the like. As shown in FIG. Form the layer 11. In addition, in the present invention, the ONO layer 11 including the three layers is referred to as a second insulating layer. Then, polycrystalline silicon is deposited on the ONO film 11 by the low pressure CVD method to form the control gate layer 1
Form 2

Next, a resist 13 shown by a chain double-dashed line in FIG. 3 (g) is formed in a predetermined pattern on the control gate layer 13, and the resist 13 is used to perform etching by reactive ion etching or the like. The etching here is performed on the control gate layer 12 and the ONO film 1.
First, the floating gate layer 10 is formed at a time, and by such etching, as shown in FIG. 5A, the floating gate 14, the ONO film 15 serving as the second insulating film, and the control gate 16 are removed. The stacked gate portions 17 are formed, and the gate portions 17 are arranged in parallel in the direction orthogonal to the bit lines 8 as shown in FIG. 4 (e).

In this way, the floating gate 1
4. When the ONO film 15 serving as the second insulating film and the gate portion 17 including the control gate 16 are formed, a region surrounded by the source line 7 and the bit line 8 previously formed in the semiconductor substrate 1. In addition, the memory element portion is formed in each gate portion 17. Therefore, the formed memory element portions are formed adjacent to each other along the length direction of the source line 7 and the bit line 8. After that, as shown in FIG.
Boron is ion-implanted using the resist 13 as a mask during the formation of 7 and the resist 13 is removed, followed by thermal diffusion, and as shown in FIG.
To form a storage device. By forming the channel stops 18 in this manner, the memory element portions are separated from each other in the direction adjacent to each other, that is, in the length direction of the bit line 8.

[0010]

However, the storage device having the above structure has the following disadvantages. That is, when the adjacent memory element portions are separated by the channel stop 18 by ion implantation, punch-through occurs between the adjacent memory element portions, and further, the diffusion layers forming the source line 7 and the bit line 8 are formed. Punch-through also occurs in. Such a phenomenon becomes more remarkable as the memory element portion is miniaturized.

On the other hand, in order to suppress such a phenomenon, instead of the channel stop 18, for example, as shown in FIG.
When the LOCOS oxide film 19 is formed by the OCOS method and the memory element portions are to be separated by the LOCOS oxide film 19, the misalignment is taken into consideration and the gate portion 17 and L
It is necessary to provide a margin I with the OCOS oxide film 19, and as a result, the area of the memory cell including the memory element portion and the region between them becomes large, which impairs high integration of the memory device. It ends up. Therefore, even in the memory cell having no contact, the reduction of the memory cell area can be realized only by using the separation by the impurity diffusion layer, and there is no merit in the memory cell area unless it is used. is there.

The present invention has been made in view of the above circumstances. An object of the present invention is to reduce the area of a memory cell, that is, to increase the degree of integration of a memory device, and between adjacent memory element parts, and To provide a nonvolatile semiconductor memory device in which punch-through between a source region to be a source line and a drain region to be a bit line is suppressed, and a manufacturing method for simplifying the manufacturing process of the memory device. is there.

[0013]

[Means for Solving the Problems] Claim 1 in the present invention
In the described nonvolatile semiconductor memory device, the base has source lines and bit lines arranged in parallel to each other, and the source lines and the bit lines are adjacent to each other along the length direction of the bit lines. In this way, a plurality of memory element parts are arranged, and between the adjacent memory element parts of the memory element parts, a groove for separating these adjacent memory element parts is formed in the base. It was taken as a means for solving the above problems.

In the method of manufacturing a non-volatile semiconductor memory device according to a second aspect of the present invention, a step of diffusing impurities to form a source region serving as a source line and a drain region serving as a bit line in a substrate so as to be parallel to each other. And a step of forming a first insulating film on the source region and the drain region,
Forming a floating gate layer on the first insulating film, forming a second insulating layer on the floating gate layer, and forming a control gate layer on the second insulating layer And a step of etching the floating gate layer, the second insulating layer, and the control gate layer using a mask, and patterning to form the floating gate, the second insulating film, and the control gate, respectively. Further, it is a means for solving the above problems that the method further comprises a step of performing etching in a self-aligning manner using the mask to form a groove between the drain region and the source region of the substrate.

This manufacturing method may include a step of implanting impurities into the inner wall portion of the groove. Also,
The groove may be formed by inclining the inner wall so that the width between the inner walls gradually becomes smaller toward the bottom.

[0016]

According to the non-volatile semiconductor memory device of the present invention, a groove for separating the adjacent memory element portions is formed between the adjacent memory element portions of the memory element portion. By embedding the insulator,
Punch through between the memory element portions and further punch through between the source line and the bit line are suppressed. Further, if the groove is formed to have a necessary minimum width, the space between the memory element parts becomes sufficiently narrow.

According to the method of manufacturing a non-volatile semiconductor memory device according to the second aspect, the trenches are formed in the substrate by using the mask used for etching the floating gate layer, the second insulating layer and the control gate layer as they are. Therefore, the two steps can be successively performed with the same mask, and thus the manufacturing process is simplified. Further, since the groove is formed in a self-aligning manner by reusing the previously used mask, there is no fear of misalignment, and unlike the case of separating by using the LOCOS method, there is no need to provide an alignment margin. As a result, element isolation is possible without increasing the memory cell area more than necessary.

By implanting impurities into the inner wall of the groove, the function of the groove as a channel stop is further enhanced. If the inner wall is formed so that the width between the inner walls becomes gradually smaller toward the bottom side, the angle between the base surface and the inner wall of the groove becomes an obtuse angle. The electric field concentration in the portion is relaxed, and a phenomenon such as so-called side wall inversion is prevented.

[0019]

The present invention will be described below based on the manufacturing method according to claim 2. 1A to 1D are process drawings for explaining a first embodiment of the manufacturing method of the present invention. The manufacturing method of the present invention is different from the conventional manufacturing method in the method of separating the memory element parts after forming the gate part 17. Therefore, the steps up to the formation of the gate portion 17, that is, the steps shown in FIG. 3F are the same as those in the conventional manufacturing method, and therefore the description of the steps is omitted in this embodiment.

1 (a) to 1 (d) are sectional views of the main part of the storage device as in the case of FIG. 5, and B in FIG. 4 (e).
1 is a cross-sectional view taken along the line B in FIG.
FIG. 3A shows the state shown in FIG. From this state, in the present embodiment, the resist 13 used for forming the gate portion 17 is directly used as a mask, the tunnel oxide film 9 is dry-etched, and the substrate at the site where the tunnel oxide film 9 is removed is further removed. 1 is dry-etched to form gate portions 17 and 1 as shown in FIG.
Grooves 20 are formed between the respective seven.

Here, when the substrate 1 is dry-etched under the etching condition that only the silicon is removed without removing the oxide film 6, only the region indicated by the channel stop 18 in FIG. That is, only the region between the source line (source region) 7 and the bit line (drain region) 8 is selectively etched. When the grooves 20 are formed in this way, the mask (resist 13) for forming the gate portions 17 is reused as it is, so that the grooves 20 are formed in a self-aligned manner, and thus misalignment may occur. There is no need to provide the alignment margin I as shown in FIG.

Next, an impurity, that is, an impurity of the opposite type to the impurity injected into the channel region between the source line 7 and the bit line 8 is injected into the formed groove 20. 21 is formed. Here, in the ion implantation, oblique ion implantation is performed so that the ions are implanted not only in the bottom portion of the groove 20 but also in the inner wall portion. Then, by thermal oxidation, an oxide film 22 is formed so as to cover the gate portions 17 ... And at the same time, an oxide film 22 is formed on the inner surfaces of the grooves 20. Then, an insulating film 23 is deposited by the CVD method or the like as shown in FIG.
0 ... An insulating film filling the inside and an interlayer insulating film are simultaneously formed,
A nonvolatile semiconductor memory device according to claim 1 of the present invention is obtained. If necessary, as shown in FIG. 1D, the insulating film 23 may be left only in the grooves 20 of the substrate 1 by etching back, and the others may be removed.

In the thus obtained memory device, the grooves 20 formed in the substrate 1 can ensure the separation between the adjacent memory element parts, and the separation by the conventional diffusion layer can be performed. A much higher punch-through breakdown voltage can be obtained. Further, in such a manufacturing method, L
Using the OCOS separation method and the trench separation method together,
That is, the wide separation area is separated by the LOCOS method,
Since a narrow portion in the memory cell is separated by a trench, a complicated process such as BiasECR CVD method, CMP method (chemical mechanical polishing method), or the like can be selected to fill a portion with a wide separation width. Since it is not necessary to use the epitaxial growth method or the like and the grooves 20 ... Are formed in a self-aligned manner using the mask used for forming the gate portions 17 as they are, the groove 20 ... Formation process can be simplified. .

In addition to embedding the insulating film 23 in the grooves 20 to function as a channel stop, impurities are implanted into the inner wall of the groove 20 to form a channel stop 21. Therefore, the element isolation function of the groove 20 is further enhanced by matching the channel stop 21. Further, as shown in FIG. 1C, if the insulating film 23 is formed not only in the groove 20 (trench) but also on the gate portion 17, the surface of the substrate 1 is the surface of the insulating film in the groove (trench). It is possible to prevent the problem of the general trench isolation method that the gate insulating film becomes higher and the breakdown voltage of the gate insulating film becomes lower due to the electric field concentration at that location.

FIGS. 2A to 2D are process drawings for explaining the second embodiment of the manufacturing method of the present invention. Even in the second embodiment, the difference from the conventional manufacturing method lies in the method of separating the memory element portions after the gate portion 17 is formed in FIG. That is, description up to the step shown in FIG.

2 (a) to 2 (d) are side sectional views of the main part of the storage device, as in the case of FIG. 1, and show B in FIG. 4 (e).
FIG. 2 is a cross-sectional view taken along the line B in FIG.
(A) shows the same state as FIG. 1 (a). From this state, the gate portion 17 is also used in this embodiment.
Using the resist 13 used for forming as it is as a mask, the tunnel oxide film 9 is dry-etched, and the substrate 1 at the site where the tunnel oxide film 9 is removed is dry-etched, as shown in FIG. 2B. At the gate 1
Grooves 24 are formed between 7 and 17, respectively. However, regarding the dry etching for the substrate 1 here, by controlling the gas ratio of the etching gas (for example, Cl ₂ and N ₂ ), the dry etching is performed toward the inner side of the substrate 1, that is, the bottom side of the groove 24 to be formed. The tapered groove 24 is formed by inclining the inner walls so that the width between the inner walls becomes gradually smaller. The inclination angle of the inner wall, that is, the angle θ formed by the surface of the substrate 1 and the inner wall surface is set to, for example, about 100 °.

Next, the groove 2 formed similarly to the first embodiment.
Impurities are implanted into 4 ... to form a channel stop 25 on the inner surface of the groove 24. Here, in ion implantation,
Since the inner wall of the groove 24 is inclined inward, it is not necessary to perform oblique ion implantation, and normal vertical implantation can be performed. Then, thermal oxidation is performed in the same manner as in the first embodiment to cover the inner surfaces of the gate portions 17 ... And the trenches 24.
6 is formed, and the insulating film 27 is further deposited by the CVD method or the like as shown in FIG. 2C to obtain the nonvolatile semiconductor memory device according to claim 1. In addition, if necessary, FIG.
As shown in (d), the insulating film 27 may be left only in the grooves 24 of the substrate 1 by etching back, and the rest may be removed as in the case of the first embodiment.

In the memory device thus obtained, the grooves 24 formed in the substrate 1 can ensure the separation between the adjacent memory element portions, and is shown in FIG. 1 (d). Similar to the memory device described above, a much higher punch-through breakdown voltage can be obtained as compared with the conventional separation by the diffusion layer. Further, even in such a manufacturing method, it is not necessary to use a complicated process for filling a portion having a large separation width as in the previous embodiment, and the groove 24 ... Forming step can be simplified. it can. Further, since the inner wall of the groove 24 is inclined inward, the angle between the corner portion formed by the surface of the substrate 1 and the inner wall of the groove 24 becomes an obtuse angle, which alleviates the electric field concentration at this corner portion, and the general trench ( groove)
It is possible to prevent a phenomenon such as so-called side wall inversion, which is a problem in separation.

Although the source line (source region) 7 and the bit line (drain region) 8 are formed by impurity diffusion into the substrate 1 in the above embodiment, for example, polycrystalline silicon is deposited on the substrate 1, The source line and the bit line may be formed by performing impurity implantation and patterning into a predetermined shape. In the above embodiment, the groove 20 (2
Impurity is injected and diffused into the channel stop 21 (2).
5) is formed, but since the element isolation function is sufficiently obtained by the groove 20 (24), this impurity diffusion layer (channel stop) does not necessarily have to be formed. Also,
Although the three-layer ONO film 15 is used as the second insulating film, for example, an oxide film single layer or a multilayer film having a different structure from the ONO film 15 may be used as the second insulating film.

[0030]

As described above, in the nonvolatile semiconductor memory device according to the first aspect of the present invention, the groove for separating the adjacent memory element portions is formed between the memory element portions adjacent to each other. Since it is formed, it is possible to suppress punch-through between the memory element parts and further punch-through between the source line and the bit line by, for example, embedding an insulator in this groove. The reliability of device characteristics as a memory device can be improved, for example, the through breakdown voltage can be increased. Further, if the groove is formed to have the minimum necessary width, the space between the memory element portions becomes sufficiently narrow, and therefore, the memory cell area can be reduced, that is, the memory device can be highly integrated.

According to a second aspect of the present invention, there is provided a method of manufacturing a non-volatile semiconductor memory device, including a floating gate layer, a second insulating layer,
Since the method is such that the mask used when the control gate layer is etched is used as it is to form the groove in the substrate, the two steps can be successively performed with the same mask, thus simplifying the manufacturing process. be able to. Further, since the groove is formed in a self-aligning manner by reusing the previously used mask, there is no fear of misalignment, and unlike the case of separating by using the LOCOS method, there is no need to provide an alignment margin. As a result, element isolation can be performed without increasing the memory cell area more than necessary.

If impurities are injected into the inner wall of the groove,
The function of the groove as a channel stop can be further enhanced, and if the inner wall is formed so that the width between the inner walls gradually becomes smaller toward the bottom side, the surface of the substrate can be improved. The angle between the corner portion formed by the groove and the inner wall of the groove becomes an obtuse angle, the electric field concentration at the corner portion can be alleviated, and so-called side wall inversion can be prevented.

[Brief description of drawings]

FIG. 1A to FIG. 1D are cross-sectional views of essential parts showing a manufacturing process for explaining a first embodiment of a manufacturing method of the present invention and a nonvolatile semiconductor memory device obtained thereby.

2A to 2D are cross-sectional views of essential parts showing the manufacturing process for explaining the second embodiment of the manufacturing method of the present invention and the nonvolatile semiconductor memory device obtained thereby.

3A to 3G are cross-sectional views of a main part showing a manufacturing process for explaining an example of a conventional manufacturing method.
It is an AA sectional view taken on the line in (e).

4A to 4E are plan views showing manufacturing steps for explaining an example of a conventional manufacturing method and a nonvolatile semiconductor memory device obtained thereby.

5A and 5B are cross-sectional views of a main part showing a manufacturing process for explaining an example of a conventional manufacturing method and a nonvolatile semiconductor memory device obtained by the conventional manufacturing method, and FIG. It is a BB line sectional view taken on the line in FIG.

FIG. 6 is a main-portion plan view of a conventional nonvolatile semiconductor memory device when formed by a LOCOS method.

[Explanation of symbols]

 1 Semiconductor Substrate (Base) 5 Ion Implantation Part 6 Oxide Film 7 Source Line 8 Bit Line 9 Tunnel Oxide Film 10 Floating Gate Layer 11 ONO Layer (Second Insulating Layer) 12 Control Gate Layer 13 Resist (Mask) 14 Floating Gate 15 ONO film (second insulating film) 16 control gate 17 gate portion 20, 24 groove

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 21/8247 29/788 29/792 8418-4M H01L 21/94 A 29/78 371

Claims (4)

[Claims] 1. A memory having a source line and a bit line arranged in parallel to each other on a base, and being adjacent to each other along the length direction of the bit line between the source line and the bit line. In a nonvolatile semiconductor memory device in which a plurality of element units are arranged, between the memory element units adjacent to each other in the memory element unit,
A non-volatile semiconductor memory device characterized in that a groove for separating these adjacent memory element portions is formed in the base body. 2. A step of forming a source region to be a source line and a drain region to be a bit line in a substrate so as to be parallel to each other by diffusing impurities, and forming a first region on the source region and the drain region. Forming an insulating film, forming a floating gate layer on the first insulating film, forming a second insulating layer on the floating gate layer, the second insulating film Forming a control gate layer on the layer, etching the floating gate layer, the second insulating layer, and the control gate layer using a mask, and patterning the floating gate, the second insulating film, and the control gate. A method of manufacturing a non-volatile semiconductor memory device, comprising: And a step of forming a groove between the drain region and the source region of the base body. 3. The method for manufacturing a nonvolatile semiconductor memory device according to claim 2, further comprising a step of implanting impurities into the inner wall portion of the groove. 4. The non-volatile semiconductor memory device according to claim 2, wherein the groove is formed by sloping the inner wall so that a width between the inner walls becomes gradually smaller toward the bottom side. Method.