JPH08171371A - Non-linear characteristic correction circuit - Google Patents

Non-linear characteristic correction circuit

Info

Publication number
JPH08171371A
JPH08171371A JP6316798A JP31679894A JPH08171371A JP H08171371 A JPH08171371 A JP H08171371A JP 6316798 A JP6316798 A JP 6316798A JP 31679894 A JP31679894 A JP 31679894A JP H08171371 A JPH08171371 A JP H08171371A
Authority
JP
Japan
Prior art keywords
correction data
data
memory
circuit
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6316798A
Other languages
Japanese (ja)
Inventor
Akihiro Maenaka
章弘 前中
Yukio Mori
幸夫 森
Takeshi Yatani
武始 八谷
Haruhiko Murata
治彦 村田
Yasuo Funatsukuri
康夫 船造
Toshiya Iinuma
俊哉 飯沼
Toshiyuki Okino
俊行 沖野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP6316798A priority Critical patent/JPH08171371A/en
Publication of JPH08171371A publication Critical patent/JPH08171371A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To realize a high definition liquid crystal projector capable of precisely. correcting a voltage-transmissivity characteristic over the whole screen. CONSTITUTION: One representative point is set at every area of a liquid crystal panel divided to plural parts, and the correction data correcting the voltage- transmissivity characteristic in the representative point in linear are stored in look-up table RAMs 1-4. The correction data in four representative points close to the input data are read out from the look-up table RAMs 1-4. The correction data from the look-up table RAMs 1-4 are linearly interpolated in the horizontal and vertical directions by an interpolation circuit 6.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、液晶プロジェクタ等に
使用される液晶パネルにおける非線形な電圧−透過率特
性を線形な特性に補正する非線形特性補正回路に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-linear characteristic correction circuit for correcting a non-linear voltage-transmittance characteristic in a liquid crystal panel used in a liquid crystal projector or the like into a linear characteristic.

【0002】[0002]

【従来の技術】液晶プロジェクタ等に使用される液晶パ
ネルは、通常、図5Aに示すように電圧−透過率特性が
非線形である。このため、従来は同図Bのような入出力
特性を有する特性補正回路を設け、この特性補正回路を
通した後の電圧を液晶パネルに印加することにより電圧
−透過率特性を同図Cのように補正していた。この電圧
−透過率特性の補正は、例えば、1992年テレビジョ
ン学会年次大会予稿集P345〜P346「ハイビジョ
ン用背面投射型液晶ディスプレイの信号処理装置」に記
載のように測定した電圧−透過率特性の逆特性を補正デ
ータとして書き込んだRAMテーブルを使用して行って
いた。
2. Description of the Related Art A liquid crystal panel used in a liquid crystal projector or the like usually has a non-linear voltage-transmittance characteristic as shown in FIG. 5A. Therefore, conventionally, a characteristic correction circuit having an input / output characteristic as shown in FIG. 9B is provided, and a voltage after passing through the characteristic correction circuit is applied to the liquid crystal panel to show the voltage-transmittance characteristic as shown in FIG. Was corrected. This voltage-transmittance characteristic is corrected by, for example, the voltage-transmittance characteristic measured as described in 1992 Television Society Annual Conference Proceedings P345-P346 "Signal processing device for rear projection type liquid crystal display for high vision". This is done by using the RAM table in which the reverse characteristic of is written as the correction data.

【0003】ところで、液晶パネルはその製造上のバラ
ツキにより厳密には画素毎に電圧−透過率特性が異なっ
ている。このため、ハイビジョン用等の高精細な液晶プ
ロジェクタに使用する場合、従来のように、液晶パネル
一枚に対して、1つの補正データで補正する方法であれ
ば画面全体にわたって正確な電圧−透過率特性の補正を
行うことができず、色むら等の原因となっていた。
By the way, strictly speaking, the liquid crystal panel has different voltage-transmittance characteristics for each pixel due to manufacturing variations. For this reason, when used in a high-definition liquid crystal projector for high-definition television or the like, if the method of correcting with one correction data for one liquid crystal panel as in the conventional case, accurate voltage-transmittance over the entire screen is obtained. The characteristics could not be corrected, which caused color unevenness.

【0004】[0004]

【発明が解決しようとする課題】本発明は、画面全体に
わたって正確に電圧−透過率特性の補正を行うことがで
きより高精細な液晶プロジェクタを実現できる非線形特
性補正回路を提供するものである。
SUMMARY OF THE INVENTION The present invention provides a non-linear characteristic correction circuit capable of accurately correcting the voltage-transmittance characteristic over the entire screen and realizing a higher definition liquid crystal projector.

【0005】[0005]

【課題を解決するための手段】本発明は、複数に分割さ
れた液晶パネルの各領域毎に1個の代表点を設定し、こ
の代表点における電圧−透過率特性を線形に補正する補
正データを記憶するメモリと、入力データに対して前記
メモリの所定アドレスにおける前記補正データを読み出
すメモリ制御回路と、前記入力データに対して複数の前
記代表点における補正データにより補間する補間回路と
を備える非線形特性補正回路である。
According to the present invention, one representative point is set for each area of a liquid crystal panel divided into a plurality of areas, and correction data for linearly correcting the voltage-transmittance characteristic at the representative point is set. A non-linear circuit including a memory for storing the data It is a characteristic correction circuit.

【0006】また、本発明は、複数に分割された液晶パ
ネルの各領域毎に1個の代表点を設定し、この代表点に
おける電圧−透過率特性を線形に補正する補正データと
基準補正データとの差分である差分補正データを記憶す
る第1メモリと、前記基準補正データを記憶する第2メ
モリと、入力データに対して前記第1メモリの所定アド
レスにおける前記差分データを読み出すメモリ制御回路
と、前記入力データに対して複数の前記代表点における
差分補正データにより補間する補間回路と、前記第1メ
モリ出力と前記補間回路出力を加算する加算回路とを備
える非線形特性補正回路である。
Further, according to the present invention, one representative point is set for each area of the liquid crystal panel divided into a plurality of areas, and the correction data and the reference correction data for linearly correcting the voltage-transmittance characteristic at the representative point are set. A first memory that stores difference correction data that is a difference between the first and second memory, a second memory that stores the reference correction data, and a memory control circuit that reads the difference data at a predetermined address of the first memory with respect to input data. A nonlinear characteristic correction circuit including an interpolation circuit that interpolates the input data with difference correction data at a plurality of the representative points, and an adder circuit that adds the first memory output and the interpolation circuit output.

【0007】[0007]

【作用】本発明においては、液晶パネルは複数の領域に
分割され各領域毎に代表点が設定される。各代表点にお
ける電圧−透過率特性を線形に補正する補正データがメ
モリに記憶されている。入力データに対して、複数の代
表点における補正データが前記メモリから読み出された
後、補間回路は前記補正データに基づき入力データに対
する補間データを水平及び垂直方向に線形補間して出力
する。
In the present invention, the liquid crystal panel is divided into a plurality of areas, and a representative point is set for each area. Correction data for linearly correcting the voltage-transmittance characteristic at each representative point is stored in the memory. After the correction data at a plurality of representative points is read from the memory for the input data, the interpolation circuit linearly interpolates the interpolation data for the input data in the horizontal and vertical directions based on the correction data and outputs the interpolation data.

【0008】[0008]

【実施例】以下、図面に従って本発明の第1の実施例を
説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings.

【0009】まず、本発明の原理について説明する。図
1のように液晶パネルを複数画素で形成されるサブブロ
ックSBに分割し、各サブブロックSBに一個の代表点
bを設定する。そして、この代表点毎に電圧−透過率特
性を測定し、これと逆特性の補正データを後述するルッ
クアップテーブルRAMに書き込んでおく。前記サブブ
ロックは4個単位で1個のブロックを形成しており、各
ブロックには水平アドレス0〜n及び垂直アドレス0〜
mが付されている。
First, the principle of the present invention will be described. As shown in FIG. 1, the liquid crystal panel is divided into sub blocks SB formed of a plurality of pixels, and one representative point b is set in each sub block SB. Then, the voltage-transmittance characteristic is measured for each of the representative points, and the correction data having the opposite characteristic is written in the look-up table RAM described later. The sub blocks form one block in units of four, and each block has horizontal addresses 0 to n and vertical addresses 0 to.
m is attached.

【0010】次に、図2は本発明の第1実施例を示すブ
ロック図であり、1〜4は液晶パネルの電圧−透過率特
性を線形に補正するために入力データを補正する補正デ
ータが記憶されているルックアップテーブルRAMであ
り、各RAMには前記代表点における補正データが記憶
されている。5は水平画素アドレス及び垂直画素アドレ
スに基づいて、前記RAMに対する水平ブロックアドレ
ス及び垂直ブロックアドレスを作成して出力するブロッ
クアドレス作成回路である。
Next, FIG. 2 is a block diagram showing a first embodiment of the present invention. Reference numerals 1 to 4 show correction data for correcting input data in order to linearly correct the voltage-transmittance characteristic of a liquid crystal panel. It is a stored look-up table RAM, and each RAM stores the correction data at the representative point. Reference numeral 5 is a block address creating circuit for creating and outputting a horizontal block address and a vertical block address for the RAM based on the horizontal pixel address and the vertical pixel address.

【0011】6は各RAMの出力に基づいて入力データ
に対する補正後データを補間する補間回路であり、乗算
器61〜66及び加算器67〜69で構成される。ま
た、7は水平画素アドレス及び垂直画素アドレスに基づ
いて前記補間回路6の補間係数を作成する係数作成回路
である。
Reference numeral 6 is an interpolation circuit for interpolating the corrected data for the input data based on the output of each RAM, and is composed of multipliers 61 to 66 and adders 67 to 69. Reference numeral 7 is a coefficient creating circuit for creating the interpolation coefficient of the interpolation circuit 6 based on the horizontal pixel address and the vertical pixel address.

【0012】次に、本実施例の動作について説明する。Next, the operation of this embodiment will be described.

【0013】まず、入力データはRAM1〜4に入力さ
れる。ブロックアドレス作成回路5は入力データの画素
アドレスに応じてブロックアドレスを算出する。即ち、
図3に示すような入力データがa1の位置の画素のもの
である場合は近接する4個の代表点b1〜b4を用いて
補間を行うため、この各代表点の補正データが記憶され
ている各RAMのブロックアドレスが指定される。つま
り、この場合、RAM1〜RAM4のブロックアドレス
は水平がNで垂直がMである。
First, the input data is input to the RAMs 1 to 4. The block address creating circuit 5 calculates the block address according to the pixel address of the input data. That is,
When the input data as shown in FIG. 3 is for the pixel at the position a1, interpolation is performed using four adjacent representative points b1 to b4, so the correction data for each representative point is stored. The block address of each RAM is designated. That is, in this case, the block addresses of RAM1 to RAM4 are N in the horizontal direction and M in the vertical direction.

【0014】また、入力データがa2の場合は代表点は
b3〜b6が選ばれるため、RAM3及びRAM4のブ
ロックアドレスは前述の場合と同じであるが、RAM1
及びRAM2のブロックアドレスは水平がNであるが、
垂直はM+1となる。
When the input data is a2, b3 to b6 are selected as the representative points, so the block addresses of RAM3 and RAM4 are the same as in the above case, but RAM1
And the block address of RAM2 is N horizontally,
Vertical is M + 1.

【0015】次に、ブロックアドレスが指定された前記
RAM1〜4の出力は補間回路6の乗算器61〜64に
供給され、まず、水平方向の線形補間が行われる。即
ち、代表点b1とb2を結んだ線上に、入力画素データ
a1を投影した点における補正データを代表点b1及び
b2の補正データにより補間するとともに、同様に代表
点b3とb4を結んだ線上に入力画素データa1を投影
した点における補正データを代表点b3及び代表点b4
の補正データにより補間する。そして、前記両投影点の
補正データにより垂直方向の線形補間を行うことによ
り、入力画素データa1の補正データの補間を行う。
Next, the outputs of the RAMs 1 to 4 designated by the block addresses are supplied to the multipliers 61 to 64 of the interpolation circuit 6, and first, the linear interpolation in the horizontal direction is performed. That is, on the line connecting the representative points b1 and b2, the correction data at the point where the input pixel data a1 is projected is interpolated by the correction data of the representative points b1 and b2, and similarly, on the line connecting the representative points b3 and b4. The correction data at the point where the input pixel data a1 is projected is represented by the representative points b3 and b4.
Interpolation is performed using the correction data of. Then, the correction data of the input pixel data a1 is interpolated by performing the linear interpolation in the vertical direction with the correction data of the both projection points.

【0016】具体的には、乗算器61及び63には補間
係数作成回路7で作成された補間係数1−KHが供給さ
れ、乗算器62及び64には補間係数KHが供給され
る。そして、乗算器61出力及び62出力は加算器67
で加算され、乗算器63出力及び64の出力は加算器6
8で加算されることにより水平方向に線形補間が行われ
る。更に、前記加算器67及び68出力はそれぞれ乗算
器65及び66に供給される。前記乗算器65には補間
係数1−KVが供給され、乗算器66には補間係数KV
が供給される。そして、前記乗算器65及び66出力は
加算器69で加算されることにより垂直方向に線形補間
される。
Specifically, the multipliers 61 and 63 are supplied with the interpolation coefficient 1-KH created by the interpolation coefficient creating circuit 7, and the multipliers 62 and 64 are supplied with the interpolation coefficient KH. The outputs of the multiplier 61 and 62 are added by the adder 67.
And the outputs of the multipliers 63 and 64 are added by the adder 6
8 is added to perform linear interpolation in the horizontal direction. Further, the outputs of the adders 67 and 68 are supplied to multipliers 65 and 66, respectively. The multiplier 65 is supplied with the interpolation coefficient 1-KV, and the multiplier 66 is supplied with the interpolation coefficient KV.
Is supplied. Then, the outputs of the multipliers 65 and 66 are added by an adder 69 to be linearly interpolated in the vertical direction.

【0017】このようにすることによって、液晶パネル
の各画素毎に電圧−透過率特性が異なっていても、各画
素単位に電圧−透過率特性を近似的に補正することがで
きる。次に本発明の他の実施例について図4に従って説
明する。
By doing so, even if the voltage-transmittance characteristic differs for each pixel of the liquid crystal panel, the voltage-transmittance characteristic can be approximately corrected for each pixel. Next, another embodiment of the present invention will be described with reference to FIG.

【0018】本実施例では、ルックアップテーブルRA
M1〜4の他にルックアップテーブルRAM7を設け、
このRAMに各代表点の補正データを平均した平均補正
データを記憶させておくと共に、RAM1〜4には各代
表点の補正データと前記平均補正データとの差分をとっ
た差分補正データを記憶させておく。そして、前記差分
補正データに対して補間回路6で補間を行い、その出力
を前記RAM7出力に加算器8で加算することにより、
第1の実施例と同様の出力を得ることができる。尚、R
AM7に記憶するデータは平均補正データ以外でも、任
意の1個の代表点における補正データとしてもよく、要
は基準となる補正データであればよい。
In this embodiment, the lookup table RA is used.
A look-up table RAM 7 is provided in addition to M1 to 4,
Average correction data obtained by averaging the correction data of each representative point is stored in this RAM, and difference correction data obtained by taking the difference between the correction data of each representative point and the average correction data is stored in RAM1-4. Keep it. The interpolation circuit 6 interpolates the difference correction data, and the output is added to the output of the RAM 7 by the adder 8,
An output similar to that of the first embodiment can be obtained. Incidentally, R
The data stored in the AM 7 may be correction data at any one representative point other than the average correction data, and the point is that the correction data is a reference.

【0019】この実施例によれば、平均補正データを記
憶するRAMを余分に設ける代わりにRAM1〜4に記
憶する各代表点に対する補正データはデータ量の少ない
差分補正データで済むため全体のRAMの容量を大幅に
削減することができる。
According to this embodiment, instead of providing an extra RAM for storing average correction data, the correction data for each representative point stored in RAMs 1 to 4 need only be difference correction data with a small amount of data, so that the entire RAM is stored. The capacity can be significantly reduced.

【0020】[0020]

【発明の効果】上述の如く本発明によれば、画面全体に
わたって正確に電圧−透過率特性の補正を行うことがで
きるためより高精細な液晶プロジェクタを実現すること
ができる。
As described above, according to the present invention, since the voltage-transmittance characteristic can be accurately corrected over the entire screen, a higher definition liquid crystal projector can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の原理を説明する図である。FIG. 1 is a diagram illustrating the principle of the present invention.

【図2】本発明の一実施例における非線形特性補正回路
の回路図である。
FIG. 2 is a circuit diagram of a nonlinear characteristic correction circuit according to an embodiment of the present invention.

【図3】図2の動作を説明する図である。FIG. 3 is a diagram illustrating the operation of FIG.

【図4】本発明の他の実施例における非線形特性補正回
路の回路図である。
FIG. 4 is a circuit diagram of a non-linear characteristic correction circuit according to another embodiment of the present invention.

【図5】電圧−透過率特性の補正を説明する説明図であ
る。
FIG. 5 is an explanatory diagram illustrating correction of voltage-transmittance characteristics.

【符号の説明】[Explanation of symbols]

1〜4、8 ルックアップテーブルRAM 5 ブロックアドレス作成回路 6 補間回路 7 係数作成回路 1-4, 8 Look-up table RAM 5 Block address creation circuit 6 Interpolation circuit 7 Coefficient creation circuit

───────────────────────────────────────────────────── フロントページの続き (72)発明者 村田 治彦 大阪府守口市京阪本通2丁目5番5号 三 洋電機株式会社内 (72)発明者 船造 康夫 大阪府守口市京阪本通2丁目5番5号 三 洋電機株式会社内 (72)発明者 飯沼 俊哉 大阪府守口市京阪本通2丁目5番5号 三 洋電機株式会社内 (72)発明者 沖野 俊行 大阪府守口市京阪本通2丁目5番5号 三 洋電機株式会社内 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Haruhiko Murata 2-5-5 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd. 5-5 Sanyo Electric Co., Ltd. (72) Inventor Toshiya Iinuma 2-5-5 Keihan Hondori, Moriguchi City, Osaka Prefecture Sanyo Electric Co., Ltd. (72) Inventor Toshiyuki Okino Keihan Hondori, Moriguchi City, Osaka Prefecture 2-5-5 Sanyo Electric Co., Ltd.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 複数に分割された液晶パネルの各領域毎
に1個の代表点を設定し、この代表点における電圧−透
過率特性を線形に補正する補正データを記憶するメモリ
と、入力データに対して前記メモリの所定アドレスにお
ける前記補正データを読み出すメモリ制御回路と、前記
入力データに対して複数の前記代表点における補正デー
タにより補間する補間回路とを備える非線形特性補正回
路。
1. A memory for storing correction data for setting one representative point for each area of a liquid crystal panel divided into a plurality of areas, and linearly correcting the voltage-transmittance characteristic at the representative point, and input data. A non-linear characteristic correction circuit including a memory control circuit that reads out the correction data at a predetermined address of the memory and an interpolation circuit that interpolates the input data with the correction data at the plurality of representative points.
【請求項2】 複数に分割された液晶パネルの各領域毎
に1個の代表点を設定し、この代表点における電圧−透
過率特性を線形に補正する補正データと基準補正データ
との差分である差分補正データを記憶する第1メモリ
と、前記基準補正データを記憶する第2メモリと、入力
データに対して前記第1メモリの所定アドレスにおける
前記差分データを読み出すメモリ制御回路と、前記入力
データに対して複数の前記代表点における差分補正デー
タにより補間する補間回路と、前記第1メモリ出力と前
記補間回路出力を加算する加算回路とをを備える非線形
特性補正回路。
2. One representative point is set for each area of the liquid crystal panel divided into a plurality of areas, and the difference between the correction data for linearly correcting the voltage-transmittance characteristic at this representative point and the reference correction data is set. A first memory for storing certain difference correction data; a second memory for storing the reference correction data; a memory control circuit for reading the difference data at a predetermined address of the first memory with respect to input data; On the other hand, a non-linear characteristic correction circuit including an interpolation circuit that interpolates with difference correction data at a plurality of the representative points, and an addition circuit that adds the first memory output and the interpolation circuit output.
JP6316798A 1994-12-20 1994-12-20 Non-linear characteristic correction circuit Pending JPH08171371A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6316798A JPH08171371A (en) 1994-12-20 1994-12-20 Non-linear characteristic correction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6316798A JPH08171371A (en) 1994-12-20 1994-12-20 Non-linear characteristic correction circuit

Publications (1)

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JPH08171371A true JPH08171371A (en) 1996-07-02

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JP6316798A Pending JPH08171371A (en) 1994-12-20 1994-12-20 Non-linear characteristic correction circuit

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JP2002287716A (en) * 2001-03-28 2002-10-04 Seiko Epson Corp Electrooptical device, electronic equipment, and projection type display device
WO2002104014A1 (en) * 2001-06-14 2002-12-27 Koninklijke Philips Electronics N.V. Lcd projection device
WO2004002170A1 (en) * 2002-06-24 2003-12-31 Koninklijke Philips Electronics N.V. Color non-uniformity correction method and apparatus
KR20040038312A (en) * 2002-10-31 2004-05-08 엘지전자 주식회사 Apparatus and method for driving plasma display panel
JP2007122013A (en) * 2005-09-29 2007-05-17 Sony Corp Display image correcting device, image display device, and display image correction method
JP2009300709A (en) * 2008-06-13 2009-12-24 Sony Corp Image display device and method for adjusting the same
JP2011039477A (en) * 2009-08-13 2011-02-24 Renei Kagi Kofun Yugenkoshi Method for control of improving luminance uniformity, luminance calibrating controller, and display device
JP4711825B2 (en) * 2003-03-27 2011-06-29 三洋電機株式会社 Display unevenness correction method

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11113019A (en) * 1997-09-30 1999-04-23 Sony Corp Image display device
JP4665328B2 (en) * 2001-03-28 2011-04-06 セイコーエプソン株式会社 Electro-optical device, electronic apparatus, and projection display device
JP2002287716A (en) * 2001-03-28 2002-10-04 Seiko Epson Corp Electrooptical device, electronic equipment, and projection type display device
WO2002104014A1 (en) * 2001-06-14 2002-12-27 Koninklijke Philips Electronics N.V. Lcd projection device
WO2004002170A1 (en) * 2002-06-24 2003-12-31 Koninklijke Philips Electronics N.V. Color non-uniformity correction method and apparatus
US6844883B2 (en) * 2002-06-24 2005-01-18 Koninklijke Philips Electronics N.V. Color non-uniformity correction method and apparatus
KR20040038312A (en) * 2002-10-31 2004-05-08 엘지전자 주식회사 Apparatus and method for driving plasma display panel
JP4711825B2 (en) * 2003-03-27 2011-06-29 三洋電機株式会社 Display unevenness correction method
JP2007122013A (en) * 2005-09-29 2007-05-17 Sony Corp Display image correcting device, image display device, and display image correction method
US7839457B2 (en) 2005-09-29 2010-11-23 Sony Corporation Display image correcting device, image display device, and display image correcting method
EP1770986A3 (en) * 2005-09-29 2010-11-17 Sony Corporation Display image correcting device, image display device, and display image correcting method
JP2009300709A (en) * 2008-06-13 2009-12-24 Sony Corp Image display device and method for adjusting the same
JP2011039477A (en) * 2009-08-13 2011-02-24 Renei Kagi Kofun Yugenkoshi Method for control of improving luminance uniformity, luminance calibrating controller, and display device

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