JPH08167639A - Contamination evaluation method in ion implantation and manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To enable detection of a fine amount of contamination by comparing a sheet resistance of a semiconductor region to a reference value after annealing by performing ion implantation for an upper surface of an evaluation substrate wherein a depth and a thickness of a semiconductor region are specified. CONSTITUTION: A polysilicon film 2 is deposited on a substrate 1 with an insulation surface as an evaluation substrate. Ion containing ion to be injected is injected to an upper surface of the substrate 1, annealed for activating ion, a sheet resistance measurement value of a semiconductor region is compared to a reference sheet resistance value and other ion excepting ion to be injected which is contained in ion beam is detected. Here, a depth and a thickness of a semiconductor region are decided so that an absolute value of a difference between a sheet resistance of a semiconductor region in ion implantation of only ion to be injected and a sheet resistance of a semiconductor region in ion implantation containing other ion is larger than a reference value of predetermined standard deviation of in-plane distribution of a sheet resistance of a semiconductor region after annealed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contamination evaluation method in ion implantation. The doping of impurities by ion implantation is widely used in the manufacture of VLSI because it can control the implantation amount and the concentration distribution in the depth direction with high accuracy. In recent years, as the miniaturization of VLSI progresses,
Higher precision has been demanded for the amount of implanted impurities and the concentration distribution in the depth direction. Therefore, a technique for easily and highly sensitively detecting the deviation of the implantation amount or the concentration distribution in the depth direction from the design value and the contamination by metal or the like has become important.

[0002]

2. Description of the Related Art A deviation of an implantation amount or a concentration distribution in a depth direction from a designed value is caused by an ion beam having the same element as the ion to be implanted but different ion valence or an ion different from the element to be implanted. The cause is that it is contained in.
Hereinafter, an ion having the same element as the ion to be implanted but a different ion valence, or an ion different from the element to be implanted is referred to as “contamination”.

Conventionally, a method of measuring the sheet resistance of the ion-implanted semiconductor substrate for evaluation has been adopted for detecting contamination in the ion-implantation process. If there is contamination, the sheet resistance of the semiconductor substrate will deviate from the designed value. By detecting this deviation, the content of contamination can be evaluated.

[0004]

The sheet resistance can be obtained from the reciprocal of the product of the carrier mobility and the concentration at each depth of the semiconductor substrate integrated from the front surface to the back surface in the depth direction. The sheet resistance is determined by the carriers distributed within the entire thickness of the semiconductor substrate, even if the contamination is concentrated at a certain depth. Therefore, the rate of change in sheet resistance due to contamination is extremely small. That is, the method of detecting contamination from the rate of change of sheet resistance has low detection sensitivity.

In recent years, the amount of contamination, which is a problem in the semiconductor manufacturing process, is 1% or less of the total injection amount, and the contamination cannot be detected by the conventional method.

For example, if contamination exists in the channel region of the MOSFET, the threshold voltage deviates from the designed value. An object of the present invention is to provide a contamination evaluation method for detecting a trace amount of contamination with high sensitivity.

[0007]

A method for evaluating contamination in ion implantation according to the present invention comprises a step of preparing an evaluation substrate in which a semiconductor region and an insulator region are distributed in the depth direction, and implantation on the upper surface of the evaluation substrate. A step of irradiating an ion beam containing ions to be ion-implanted, an annealing step of annealing the evaluation substrate to activate the ion-implanted ions, and measuring and measuring the sheet resistance of the semiconductor region. Comparing the value with a reference value of the sheet resistance obtained in advance, and detecting other ions other than the ions to be implanted contained in the ion beam, the evaluation substrate, In the preparing step, σ is a reference value of a predetermined standard deviation of the in-plane distribution of the sheet resistance of the semiconductor region after the annealing step, and an ion beam containing only the ions to be implanted. By irradiating-ion implanted Rs ₀ the sheet resistance of the semiconductor region when, when the sheet resistance of the semiconductor region by irradiating the other ion beams including ion when the ion implantation was set to Rs, | An evaluation substrate is prepared in which the depth and thickness of the semiconductor region are determined so as to satisfy the relationship of Rs ₀ −Rs |> σ.

The depth and thickness of the semiconductor region may be determined so as to satisfy the relationship of | Rs ₀ −Rs |> 2σ.

[0009]

When ions are implanted into the evaluation substrate in which the semiconductor layer and the insulator layer are laminated, the implanted ions are distributed in the semiconductor layer and the insulator layer. If an insulator layer is formed near the depth where a large amount of ions to be injected are injected, the large amount of injected ions does not contribute to the sheet resistance. If the semiconductor layer is near the depth where a large amount of contamination is injected,
The sheet resistance of this semiconductor layer changes relatively greatly depending on the presence or absence of contamination. By detecting the variation of the sheet resistance of the semiconductor layer, the contamination can be detected with high sensitivity.

If the depth and thickness of the semiconductor layer are selected so that the variation of the sheet resistance due to the presence or absence of contamination is larger than the variation of the sheet resistance in the plane, the contamination can be detected more reliably. You can

[0011]

EXAMPLE A contamination evaluation method according to an example of the present invention will be described below by taking an example of implanting trivalent P ions into a silicon substrate.

Ion implantation using polyvalent ions can obtain high-energy ions even under the same acceleration voltage as compared with ion implantation using monovalent ions. Therefore, it has been put to practical use in high energy ion implantation of 200 keV or more.

When performing ion implantation using trivalent P ions, only the trivalent P ions are taken out by the mass spectrometer. Even if only the trivalent P ions are taken out from the mass spectrometer, a part of the trivalent P ions becomes divalent or monovalent ions due to the action with the residual gas in the path of the ion beam. The divalent and monovalent ions become contamination. Incidentally, it may become a neutral P atom.

Therefore, the ion beam contains trivalent to monovalent P ions. When the ions are accelerated by the post-stage acceleration voltage, the kinetic energy obtained by each ion varies depending on the ion valence. For example, 40k from the ion source
Ions are taken out at a voltage of V and the post-stage acceleration voltage is set to 210 k
Assuming V, the kinetic energies of trivalent, divalent, and monovalent P ions are 750 keV, 540 keV, and 330 keV, respectively.

The depth at which P ions are implanted into the semiconductor substrate depends on its kinetic energy. For example, the above 3
The projected ranges of the valent, divalent, and monovalent P ions are 1040 nm, 790 nm, and 490 nm, respectively. In this way, more P ions than the designed value are implanted near the depths of 790 nm and 490 nm.

FIG. 1 shows the P concentration distribution in the depth direction when the ion implantation is carried out under the above conditions and the contamination is 1%. The dose is 3 × 10 ¹³ cm ^-2
Is. The horizontal axis is the depth from the silicon substrate surface in nm
And the vertical axis represents the P concentration in the unit of cm ⁻³ . The curve p in the figure shows the P concentration when 1% of contamination is included, and the curve q shows the P concentration when no contamination is included.

The P concentration increases with increasing depth from the substrate surface regardless of the presence or absence of contamination, and the P concentration increases to 104
A maximum value of about 7.6 × 10 ¹⁷ cm ⁻³ is taken at a point of 0 nm. At a deeper depth, the P concentration sharply decreases. It can be seen that the P concentration is higher in the case of containing the contamination than in the case of not containing the contamination, particularly in the range of 700 nm from the surface. This is because divalent and monovalent P ions are heavily implanted in this range.

The sheet resistance of a silicon substrate having the concentration distribution shown in FIG. 1 is greatly influenced by the P concentration near a depth of 1000 nm. Therefore, the depth from the surface is 700 nm
The difference in sheet resistance due to the difference in P concentration in the range is small.

FIG. 2A is a sectional view of the evaluation substrate used in this example. A polysilicon film 2 is formed on a substrate 1 having an insulating surface. Polysilicon film 2
Is deposited by, for example, CVD.

FIG. 2B shows another example of the structure of the evaluation board. An insulating film 1b such as SiO ₂ is formed on the silicon substrate 1a.
Are formed. The insulating film 1b is formed by, for example, thermally oxidizing the surface of the silicon substrate. Figure 1 on the insulating film 1b
A polysilicon film 2 is formed as in (A).

FIG. 3 shows the sheet resistance of the polysilicon film 2 when P ions are implanted into the evaluation substrate shown in FIG. 2A or 2B under the same conditions as in FIG. The horizontal axis represents the thickness of the polysilicon film 2 in the unit of nm, and the vertical axis represents the sheet resistance in the unit of Ω / □. The curve r in the figure shows the sheet resistance when 1% of contamination is included, and the curve s shows the sheet resistance when no contamination is included.

When the thickness of the semiconductor layer is in the range of 0 to 700 nm, the sheet resistance sharply decreases as the thickness of the semiconductor layer increases. When the thickness of the semiconductor layer is further increased, the decrease in sheet resistance gradually becomes gentle and approaches 500Ω / □.

When the thickness of the semiconductor layer is about 700 nm or less, the difference between the sheet resistances with and without contamination is relatively large, and the sheet resistance with the contamination is smaller. The thickness of the semiconductor layer is 7
When it is more than 00 nm, the difference in sheet resistance becomes small, and 1
When the thickness is 000 nm or more, there is almost no difference.

The relationship between the thickness of the semiconductor layer and the difference in sheet resistance corresponds to the P concentration distribution in FIG. That is, FIG.
As shown in, a large amount of trivalent P ions are implanted near the depth of 1000 nm. The thickness of the semiconductor layer is 1000
When the thickness is greater than or equal to nm, a large amount of P injected to this depth greatly contributes to the sheet resistance, so that the difference in P concentration due to contamination does not become apparent as the difference in sheet resistance. Therefore, there is almost no difference in sheet resistance.

FIG. 4 shows the variation rate of the sheet resistance with respect to the thickness of the semiconductor layer. The horizontal axis represents the thickness of the semiconductor layer in the unit of nm, and the vertical axis represents the variation rate of the sheet resistance in the unit of%. Here, the variation rate of the sheet resistance is Rs (Ω / Ω) for the sheet resistance with and without contamination, respectively.
□) and Rs ₀ (Ω / □), it was defined as | Rs−Rs ₀ | / Rs ₀ × 100 (%).

When the thickness of the semiconductor layer increases from 0 nm, the variation rate of the sheet resistance also increases, and the maximum value is about 12% when the thickness is about 450 nm. When the thickness of the semiconductor layer is further increased, the variation rate of the sheet resistance is reduced, and approaches 1%.
In order to detect the presence or absence of contamination, the thickness of the semiconductor layer may be selected so that the variation rate of the sheet resistance is larger than the measurement error or the in-plane variation rate of the sheet resistance.

Specifically, if the standard deviation of the in-plane distribution of the sheet resistance is σ, then | Rs−Rs ₀ | / Rs ₀ ≧ σ / Rs ₀ . In order to further increase the detection sensitivity, it is preferable that | Rs−Rs ₀ | / Rs ₀ ≧ 2σ / Rs ₀ .

The standard deviation σ may be obtained by ion implantation into another semiconductor substrate and measuring the in-plane distribution of the sheet resistance. For example, when σ / Rs ₀ is 2%, it can be seen from FIG. 4 that the thickness of the semiconductor layer should be about 1000 nm or less in order to increase the variation rate of the sheet resistance to 2% or more. To further increase the detection sensitivity, the thickness of the semiconductor layer should be about 1% in order to make the variation rate of the sheet resistance 4% or more.
It is understood that the thickness may be set to 00 to 800 nm. Note that since the normal σ / Rs ₀ is about 0.5%, | Rs−R
It is preferable that s ₀ | / Rs ₀ be 0.005% or more.

However, when the thickness of the semiconductor layer is reduced, the sheet resistance sharply increases as shown in FIG. If the sheet resistance increases, the measurement becomes difficult. For example, a sheet resistance measuring device OmniMA manufactured by Prometrics (USA)
When using PRS50 / e, the sheet resistance is 1
It is necessary to set it to 0000Ω / □ or less. That is, it can be seen from FIG. 3 that the thickness of the semiconductor layer needs to be 480 nm or more.

Therefore, when σ / Rs ₀ is 2%, the thickness of the semiconductor layer is preferably 480 to 1000 nm, and 480 to 800 nm is preferable in order to further improve the detection sensitivity.
The sheet resistance may be reduced by increasing the dose amount.

Although the case where the contamination is 1% has been described with reference to FIGS. 3 and 4, when the contamination ratio to be detected is changed, the preferable thickness of the semiconductor layer is also changed. For example, if the contamination ratio decreases, the variation rate of the sheet resistance shown in FIG. 4 also decreases.
Therefore, the preferable thickness of the semiconductor layer is more limited.

Next, the sheet resistance and the variation rate of the sheet resistance when the contamination ratio is changed will be described with reference to FIG. FIG. 5A shows a case where the evaluation method according to the conventional example is used, that is, when the thickness of the semiconductor layer is made sufficiently larger than the projected range of the ions.
Shows the sheet resistance and its variation rate when evaluated by the evaluation method according to the example. Note that FIG. 5B shows the case where the thickness of the semiconductor layer is selected so that the variation rate of the sheet resistance is maximized. In both figures, the horizontal axis represents the contamination ratio in unit%, the left vertical axis represents the sheet resistance in the unit Ω / □, and the right vertical axis represents the variation rate of the sheet resistance in the unit%. The solid line and the dotted line in the figure show the sheet resistance and the variation rate of the sheet resistance, respectively.

When the evaluation method according to the conventional example is used, the sheet resistance increases from 500 Ω / □ to about 480 Ω / □ when the contamination ratio increases from 0% to 4%.
The sheet resistance fluctuation rate increases from 0% to about 4%.

When the evaluation method according to the embodiment is used, the sheet resistance increases from about 12000 Ω / □ to about 800 when the contamination ratio increases from 0% to 4%.
It decreases to 0Ω / □, and the variation rate of the sheet resistance increases from 0% to about 33%.

When the contamination ratio is 1.5% or less, the sheet resistance becomes 10,000 Ω / □ or more, which makes the measurement difficult. Therefore, it is not preferable to select the thickness of the semiconductor layer so as to maximize the variation rate of the sheet resistance. In this case, the sheet resistance is 10000Ω / □
Within the range below, the fluctuation rate is σ / Rs _{0 and} further 2
It is preferable to select the thickness of the semiconductor layer so that σ / Rs ₀ or more.

As described above, in the evaluation method according to the embodiment, a larger variation rate of the sheet resistance can be obtained as compared with the conventional example even if the contamination ratio is the same. Therefore,
It is possible to detect a small amount of contamination with high sensitivity.

Next, the procedure of the evaluation method according to the embodiment will be described. First, the ion implantation conditions to be investigated and the contamination ratio to be detected are determined. The contamination energy under these conditions is calculated. Find the implantation depth of ions to be implanted and contamination,
A concentration distribution in the depth direction shown in FIG. 1 is created.

The relationship between the thickness of the semiconductor layer and the sheet resistance shown in FIG. 3 is obtained from the concentration distribution shown in FIG. From the relationship between the thickness of the semiconductor layer and the sheet resistance, the relationship between the thickness of the semiconductor layer and the variation rate of the sheet resistance shown in FIG. 4 is obtained. The thickness of the semiconductor layer is determined so that the sheet resistance and its variation rate fall within a desired range.

A semiconductor layer having a predetermined thickness is deposited on a substrate having an insulating surface to prepare an evaluation substrate. For example, a polysilicon film is deposited by CVD. Ion implantation is performed on the evaluation substrate under predetermined conditions. Annealing is performed after the ion implantation to activate the implanted ions. After annealing, the sheet resistance of the semiconductor layer of the evaluation substrate is measured. For example, the sheet resistance is measured at a plurality of points on the surface and the average thereof is taken. From the difference between the sheet resistance Rs _{0 in the} absence of contamination and the measured sheet resistance, the contamination ratio can be inferred.

More simply, referring to the graph of the concentration distribution in the depth direction of FIG. 1, an insulating layer is formed in the vicinity of the depth where the target ions are most injected, and the most contamination is injected. You may produce the evaluation board | substrate which becomes a semiconductor layer in the vicinity of the depth. As described above, even when the evaluation substrate is manufactured by a simple method, an effect close to the effect when the evaluation substrate is manufactured can be expected from the detailed calculation results described above.

In the above embodiment, the case where the contamination is implanted at a position shallower than the target ion has been described, but the invention can be applied to the case where the contamination is implanted at a position deeper than the target ion. In a deceleration ion implantation method in which ions are once accelerated with a high voltage and then decelerated with a reverse voltage to perform ion implantation, for example, compared with the target trivalent P ion, the contamination is divalent or monovalent.
Valence P ions or neutralized P atoms have a smaller deceleration amount. Therefore, the contamination is implanted at a deeper position than the target ion.

In such a case, an insulating layer is formed on the surface of the evaluation substrate, and a semiconductor layer is formed in the vicinity of the depth at which contamination is injected. Obtainable. For example, FIG. 2 (A)
An insulating layer 3 is formed to a desired thickness on the semiconductor layer 2 as shown by a broken line. Alternatively, an insulator layer may be formed on the surface of the silicon substrate. In this case, the insulator layer 3 on the surface is removed by etching before measuring the sheet resistance of the semiconductor layer.

In a method of manufacturing a semiconductor device having a step of implanting ions into a semiconductor substrate, the degree of contamination of the ion beam obtained by such a contamination evaluation method is confirmed, and the result is fed back. Desired ion implantation can be performed by controlling the degree of vacuum in the path of the ion beam of the ion implantation apparatus.

That is, in the case of implanting polyvalent ions, the polyvalent ions become ions of lower valence due to the residual gas in the path of the ion beam, and the ions of low valence are contaminated. It becomes a nation. Therefore, when the degree of contamination of the ion beam is high, if the residual gas in the path of the ion beam is removed, that is, if the degree of vacuum is controlled to perform the ion implantation, the desired multivalent charge can be obtained. Ion implantation can be performed.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0046]

As described above, according to the present invention,
Contamination during ion implantation can be easily detected with high sensitivity.

[Brief description of drawings]

FIG. 1 is a graph showing a P concentration distribution in a depth direction when P ions are implanted into a silicon substrate.

FIG. 2 is a cross-sectional view of an evaluation substrate used in a contamination evaluation method during ion implantation according to an example of the present invention.

FIG. 3 is a graph showing the relationship between the sheet resistance of the semiconductor layer and the thickness of the semiconductor layer when P ions are ion-implanted into the evaluation substrate shown in FIG.

4 is a graph showing the relationship between the variation rate of the sheet resistance of the semiconductor layer and the thickness of the semiconductor layer when P ions are ion-implanted into the evaluation substrate shown in FIG.

5 is a graph showing the relationship between the sheet resistance of the semiconductor layer and its variation rate and the contamination ratio when P ions are implanted into the evaluation substrate shown in FIG.

[Explanation of symbols]

 1 Substrate having insulating surface 1a Silicon substrate 1b Insulating film 2 Polysilicon film

Claims (4)

[Claims] 1. A step of preparing an evaluation substrate in which a semiconductor region and an insulator region are distributed in a depth direction, and ion implantation is performed by irradiating an upper surface of the evaluation substrate with an ion beam containing ions to be implanted. A step, an annealing step of annealing the evaluation substrate to activate the ion-implanted ions, a sheet resistance of the semiconductor region is measured, and the measured value is compared with a predetermined reference value of the sheet resistance. Then, including the step of detecting ions other than the ions to be implanted contained in the ion beam, in the step of preparing the evaluation substrate, a sheet of the semiconductor region after the annealing step The standard value of the standard deviation of the in-plane distribution of the resistance is σ,
The sheet resistance of the semiconductor region when ion-implanted by irradiating the ion beam containing only the ions to be implanted is Rs ₀ , and the sheet resistance of the semiconductor region when ion-implanted by irradiating the ion beam also containing the other ions. Sheet resistance is R
A contamination evaluation method in ion implantation for preparing an evaluation substrate in which the depth and thickness of the semiconductor region are determined so as to satisfy the relationship of | Rs ₀ −Rs |> σ, where s. 2. The contamination evaluation method in ion implantation according to claim 1, wherein the depth and thickness of the semiconductor region are determined so as to satisfy the relationship of | Rs ₀ −Rs |> 2σ. 3. The contamination evaluation method in ion implantation according to claim 1, wherein the reference value σ is 0.005 × Rs ₀ . 4. The semiconductor region and the insulator region are divided in the depth direction.
Prepare the coated evaluation board, and set the vacuum degree in the ion beam path to the first vacuum degree.
An ion beam containing ions to be implanted on the upper surface of the evaluation substrate.
Ion implantation by irradiating the ion beam, annealing the evaluation substrate, and implanting ions
Is activated, the sheet resistance of the semiconductor region is measured, and the measured value is obtained in advance.
Compare the sheet resistance reference value
Other than the ions to be implanted contained in the on-beam
Is an evaluation step for detecting other ions of the evaluation substrate, wherein the evaluation substrate is the semiconductor region after annealing.
Based on a predetermined standard deviation of the in-plane distribution of sheet resistance of
Ion beam containing quasi value σ and only the ions to be injected
Of the semiconductor region when ion irradiation is performed by irradiating a semiconductor
Resistance to Rs ₀, An ion beam containing the other ions
Of the semiconductor region when irradiated with ions for ion implantation
When the resistance is Rs, | Rs₀-Rs |> σ so that the depth and thickness of the semiconductor region are satisfied.
And the predetermined sheet resistance error tolerance is ΔRs.
, | Rs₀In the case of −Rs |> ΔRs, the first vacuum degree is increased and the evaluation step is repeated.
Carry out | Rs₀When −Rs | ≦ ΔRs, the step of setting the first degree of vacuum to a proper degree of vacuum, the step of preparing a semiconductor substrate to be ion-implanted, and the condition that the degree of vacuum in the ion beam path is the proper degree of vacuum.
The semiconductor substrate containing the ions to be implanted.
A step of irradiating with an on-beam and performing ion implantation
A method for manufacturing a conductor device.