JPH0816696B2 - Azimuth reference pulse correction voltage generator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to TACAN (tactica).
l air navigation) The present invention relates to an azimuth reference pulse correction voltage generator that generates a correction voltage for a transmission modulation waveform that controls the transmission output of the device.

[0002]

2. Description of the Related Art The takan system is a system in which a radio wave is reciprocated from a mobile device to obtain a distance, and a radio wave from a takan device of a ground station is received to obtain a direction. Azimuth measurement in the takan system is described in, for example, Japanese Patent Laid-Open No. 64-1982.

First, the pulse configuration of the transmission output of the takan device will be described with reference to FIG. As shown in the 1st to 3rd lines, the pulse configuration of the transmission output of the takan device is such that a high duty (about 30%) called a burst and a short north and 40 degree azimuth reference pulse and a low duty called a squitter. It is composed of (about 1.9%) pulses. As shown in the first and second lines, each pulse of the transmission output of the takan consists of a pair of pulses called a Gaussian waveform. The fourth line shows the north azimuth reference pulse of the third line, the squitter pulse that follows it, and the 40-degree azimuth reference pulse that follows them. The fifth line shows the azimuth reference pulse gate signal indicating the positions of the north azimuth reference pulse and the 40 ° azimuth reference pulse. 6th and 7th
As shown in the line, the north azimuth reference pulse consists of 12 pulse pairs and the 40 degree azimuth reference pulse consists of 6 pulse pairs. As shown in the eighth line, the squitter pulse also consists of a pulse pair. A transmission detection waveform (waveform of e of FIG. 5 described later) is shown in the ninth line.

As is apparent from the above, the azimuth reference pulse gate signal of the fifth line is the first to nth (n is an integer of 2 or more) sequentially generated, as is apparent from the sixth and seventh lines. When indicating the position of the north reference pulse train, n is 24 (that is, 12 pulse pairs), and when indicating the position of the 40-degree reference pulse train, n is 12 ( That is, 6 pulse pairs). The present invention receives an azimuth reference pulse gate signal indicating the position of an azimuth reference pulse train consisting of sequentially generated first to nth pulses, and sets a correction voltage for a modulation waveform for transmission to the first to nth pulses. Corresponding to
The present invention relates to an azimuth reference pulse correction voltage generator that generates an nth correction voltage.

As described above, every pulse of the transmission output of the takan device is a pair of pulses called a Gaussian waveform, and is controlled so that the transmission level (5 kW) and the pulse width (3.5 μs) are constant. Assuming that the power amplification transistor voltage is 45 V, the efficiency is 50%, and the circuit loss is 10% at the transmission level of 5 kW, the current is 5000 (W) ÷ 45 (V) ÷
0.5 / 0.9 = 247 (A).

Since this current flows at pulse intervals of 12 μs, a large-capacity power supply is required to keep the voltage constant. Due to downsizing of equipment and efficiency of power supply capacity, the power supply capacity is
5 seconds) is expected. In this case, the north and 40 degree azimuth reference pulses are 16
Since it is twice as high, the voltage behind the constituent pulses gradually drops. As a result, when amplitude modulation is performed with pulses of the same amplitude, the output drop behind the constituent pulses is significant. Further, due to the thermal effect of the power amplification transistor, the transmission output has a level difference of about 2 dB even though there is an ALC (automatic level control) circuit (which has a large time constant and therefore does not respond in a short time). . Since this value is too large for the standard of 1 dB or less, the modulation voltage correcting means has been conventionally provided for the north and 40-degree azimuth reference pulses.

FIG. 5 shows a block diagram of a conventional transmitter, and FIG. 6 shows a block diagram of an azimuth reference pulse correction voltage generator. In FIG. 5, the continuous wave (CW wave) of the 1 GHz signal generator 1 is amplified by the amplifier 2, and the pulse modulator 3
Then, the RF (radio frequency) synchronized with the TX (transmission) trigger a
ency) The pulse is modulated by the modulation waveform b of the gate generator 9. The output of the pulse modulator 3 is amplitude-modulated by the class C pulse modulator 4 in the next stage by the composite waveform j of the gate waveform i and the Gaussian waveform g. For class C amplification, the gate waveform i portion is used as a bias, and the bias component of the amplifier 5 at the next stage is taken into consideration. As a result, the output waveform d of the amplifier 5 becomes a Gaussian waveform without a gate waveform.

A part of the transmission output d passes through the directional coupler 6, the detector 7, and the amplifier 8 for feedback, and then the level system ALC circuit 15, the pulse width system ALC circuit 18, and the azimuth reference pulse correction voltage generator. Added to 30.
The level system ALC circuit 15 is a circuit that amplifies and outputs the difference between the peak hold voltage of the detected waveform e and the reference value voltage.
The pulse width system ALC circuit 18 detects the detected waveform e with an amplitude of about 2
It is a circuit that integrates the pulse width when compared with the reference voltage at the 0% point and amplifies and outputs the difference between the peak hold voltage of the integrated waveform and the reference value voltage. The azimuth reference pulse correction voltage generation device 30 is a device that performs a calculation process on the level and pulse width of the detection waveform e for each constituent pulse of the north and 40 ° azimuth reference pulses and generates a correction voltage. 6 shows. The detailed description of FIG. 6 will be described later.

The level system output signals of the level system ALC circuit 15 and the azimuth reference pulse correction voltage generator 30 are added by the analog adder 14 to form a DC voltage waveform f. The DC voltage waveform f becomes a Gaussian waveform g proportional to the DC voltage waveform f in the voltage-pulse level conversion circuit 12. The Gaussian waveform is generated by reading the waveform of the ROM in the voltage-pulse level conversion circuit 12 at the timing of the TX trigger a. Next, the pulse width system output signals of the pulse width system ALC circuit 18 and the azimuth reference pulse correction voltage generator 30 are added by the analog adder 17 to form a DC voltage waveform h. The DC voltage waveform h is pulse-modulated in the gate circuit 13 by the output signal c of the gate generator 10 which produces a pulse width of 10 μs from the TX trigger a and becomes a waveform i. The pulse waveform i is used as a bias of the class C pulse modulator 4. The Gaussian waveform g and the gate waveform i are added by the analog adder 11 to form a modulation signal waveform j. The feedback circuit is constructed in this way.

Next, the azimuth reference pulse correction voltage generator 30 shown in FIG. 6 will be described.

In FIG. 6, north and 40 degree azimuth reference pulse addressing is generated by the north and 40 degree azimuth reference pulse gate and the TX trigger a. The address is given by the TX trigger (T for north and 40 degree azimuth reference pulse).
The address is generated by the address circuit 48. TX
The trigger a is added to the timing generation circuit 49, and each timing signal (correction RAM read,
D / A writing, data RAM reading, data latching and correction data addition) are generated. This calculation is performed for both the level system and the pulse width system for each transmission pulse (11.6 μs).

The feedback detection waveform e is applied to the pulse width / voltage conversion circuit 31 of the pulse width system and the peak hold circuit 34 of the level system. First, the pulse width / voltage conversion circuit 31 integrates the pulse width compared with the voltage at the 40% point of the amplitude of the detected waveform e to convert it into a voltage. The integrated voltage is peak-held by the next peak-hold circuit 32 and is A
The analog voltage is converted into a digital signal by the / D converter 33. For the level system, the peak level of the detected waveform e is set in the peak hold circuit 34 in exactly the same manner, and the value is set to A
The / D converter 35 converts the analog voltage into a digital signal.

The two signals which have become digital signals are averaged by the average value calculating circuit 36, and the pulse width system calculates the average of 64 times (the added value of 64 times is divided by 64) and the level system calculates 8 times. The average (the added value of 8 times is divided by 8) is taken and output to the next subtractor 37. First north and 40 degree azimuth reference pulse
Since the reference value storage circuit 38 operates only when the pulse is applied, the reference value of the pulse width system is set every 64 times.
The standard value of the level system is rewritten every 8 times. North and four
The first pulse of the 0 ° azimuth reference pulse becomes the reference value, and the second pulse and the subsequent pulses passing through the data buffer circuit 39 are controlled by being subtracted by the subtractor 40. Outputs one small level (1/2 ⁸ level). As for the output of the subtractor 37, the data output circuit 41 performs addition / subtraction of the data up to the previous time stored in the data storage circuit 42 and the large or small one level (1/2 ⁸ level) acquired this time. The output result of the data output circuit 41 is stored in the data storage circuit 42 and
It is output to the pulse width D / A converter 43 or the level D / A converter 44 and converted from a digital value to an analog value. The converted analog voltages are output circuits 45 and 46 having gain setting and impedance conversion functions.
Is output as a correction voltage. As described above, a series of these arithmetic processings are performed for each transmission pulse (11.6 μs) for both the level system and the pulse width system.

[0014]

In this conventional azimuth reference pulse correction voltage generator, two feedback circuits for the ALC circuit and the azimuth reference pulse (the pulse width system and the level system are divided into four feedback systems). Since the control system is provided, the control system easily becomes unstable. Therefore, as described above, the azimuth reference pulse system has the drawbacks that no feedback gain is obtained, the response to the disturbance is slow, and the amplitude variation due to the minimum bit error due to digital is always about ± 0.3 dB. The control of the azimuth reference pulse is
Although it is performed for each constituent pulse, since the pulse interval is specified as 12 μs, data control (A / D conversion, data collection, comparison with reference value, average value processing, data output and D / A conversion) is performed during this period. Therefore, a high speed device is required. A high-speed element has a drawback in that a timing error occurs due to element variations and the like, which is apt to malfunction and becomes unstable.

Further, since the control of the azimuth reference pulse is a feedback system, as described above, there is a drawback that the circuit configuration for data control is complicated and maintenance is difficult.

An object of the present invention is to eliminate the above-mentioned drawbacks, to generate an azimuth reference pulse correction voltage capable of reducing the amplitude fluctuation of the transmission output due to a stable control system, quick response, and minimum bit error such as digital control. To provide a device.

Another object of the present invention is to provide an azimuth reference pulse correction voltage generator which has a simple circuit configuration, is easy to maintain, does not require a high speed element, and does not malfunction due to a timing error. It is in.

[0018]

The azimuth reference pulse correction voltage generator of the present invention uses a conventional ALC circuit to deal with the overall level fluctuation of the transmission output, and with respect to the azimuth reference pulse, An open-loop correction means is used that creates a correction voltage for each constituent pulse and adds it to the ALD circuit.

That is, according to the present invention, the first
To an n-th (n is an integer of 2 or more) pulse, the azimuth reference pulse gate signal indicating the position of the azimuth reference pulse train is received, and the correction voltage of the modulation waveform for transmission is changed to the first to the n-th pulses. In the azimuth reference pulse correction voltage generator that generates the corresponding first to nth correction voltages, the first to nth correction voltage generators generate the first to nth correction voltages.
A correction voltage generating circuit having a resistance dividing circuit; receiving the azimuth reference pulse gate signal and sequentially generating first to nth address signals indicating positions of the first to nth pulses of the azimuth reference pulse train, An address generator for controlling the azimuth reference pulse train, which is connected to the address generator and the first to nth resistance division circuits and is indicated by the first to nth address signals. To a selection circuit for sequentially outputting the first to nth correction voltages corresponding to the nth pulse, the azimuth reference pulse correction voltage generating device is obtained.

According to the present invention, the address generator receives the azimuth reference pulse gate signal, detects a rising portion of the azimuth reference pulse gate signal, and generates a rising detection pulse; and a differentiating circuit; A delay circuit connected to the circuit for delaying the rising edge detection pulse as a delayed rising edge detection pulse until the generation of the first pulse of the azimuth reference pulse train; and a delay circuit connected to the delay circuit and operated by the delayed rising edge detection pulse. And an oscillation circuit that sequentially generates first to nth clock pulses corresponding to the first to nth pulses of the azimuth reference pulse train; and the oscillation circuit connected to the oscillation circuit and the first to nth pulses. Clock pulses are counted as first to nth count values, and the first to nth count values are counted as the first to nth azimuth reference pulse trains. A counting circuit for sequentially outputted as the first to address signal of said first n indicates the position of the pulse; heading reference pulse correction voltage generating device which comprises a can be obtained.

Further, according to the present invention, the selection circuit is connected to the address generator and the first to nth resistance division circuits, and is indicated by the first to nth address signals. A multiplexer circuit that sequentially selects and outputs the first to nth correction voltages corresponding to the first to nth pulses of the azimuth reference pulse train; and an output of the multiplexer circuit connected to the multiplexer circuit. There is provided an azimuth reference pulse correction voltage generating device characterized by including an output circuit for setting gain and converting impedance with respect to voltage.

[0022]

The present invention will be described below with reference to the drawings. 1 is a block diagram of a transmitter in which the present invention is used, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a timing diagram. In FIG. 1, except for the azimuth reference pulse correction voltage generator 16 of the present invention, those described in the prior art. As shown in FIG. 1, the inputs of the azimuth reference pulse correction voltage generator are the north and 40 degree azimuth reference pulses. It is a gate signal only.

The azimuth reference pulse correction voltage generator according to the embodiment of the present invention shown in FIG. 2 includes an azimuth reference pulse train (first to n-th (n is an integer of 2 or more)) sequentially generated. 3) (first line), the azimuth reference pulse gate signal (the second and third lines in FIG. 3) indicating the position is received, and the correction voltage of the modulation waveform for transmission is changed to the first to nth pulses. It is generated as the 1st to nth correction voltages.
As is clear from the first line in FIG. 3, n is 24 in the case of the north azimuth reference pulse train and n is 12 in the case of the 40 ° azimuth reference pulse train.

The azimuth reference pulse correction voltage generating device shown in FIG. 2 has a correction voltage generating circuit 26 having first to n-th resistance division circuits for generating first to n-th correction voltages.
The address generator 20 receives the azimuth reference pulse gate signal and sequentially generates the first to nth address signals indicating the positions of the first to nth pulses of the azimuth reference pulse train.

Multiplexer circuit 25 and output circuit 27
Is connected to the address generator 20 and the first to nth resistance divider circuits, and selects the first to nth pulses of the azimuth reference pulse train indicated by the first to nth address signals. Corresponding first to nth correction voltages are sequentially selected and output.

More specifically, the address generator 20 receives the azimuth reference pulse gate signal, detects the rising portion of the azimuth reference pulse gate signal, and detects the rising detection pulse p.
It has a differentiating circuit 21 for generating (the fourth line in FIG. 3). The delay circuit 22 is connected to the differentiating circuit 21 and delays the rising edge detection pulse as a delayed rising edge detection pulse q (fifth line in FIG. 3) until the first pulse of the azimuth reference pulse train is generated. The oscillating circuit 23 is connected to the delay circuit 22 and operates with the delayed rising edge detection pulse q, and the first to nth clock pulses r (corresponding to the first to nth clock pulses r in FIG. 3) corresponding to the first to nth pulses of the azimuth reference pulse train. 6 lines) are sequentially generated. The counting circuit 24 is connected to the oscillator circuit 23, counts the first to nth clock pulses r as first to nth count values, and outputs the first to nth count values to the first azimuth reference pulse train. 1st to nth indicating the position of the nth pulse to the nth pulse
The address signals are sequentially output.

The multiplexer circuit 25 is a first circuit of the counting circuit 24 of the address generator 20 and the correction voltage generating circuit 26.
To the nth resistance division circuit, and corresponding to the 1st to nth pulses of the azimuth reference pulse train indicated by the 1st to nth address signals, the 1st to nth correction voltages t (FIG. The seventh line 3) is sequentially selected and output. Output circuit 27
Is connected to the multiplexer circuit 25 and performs gain setting and impedance conversion for the output voltage t of the multiplexer circuit 25.

In FIGS. 2 and 3, the north and 40 degree azimuth reference pulse gate inputs have a waveform p in which the rising portion of the gate is detected by the differentiating circuit 21 of the address generator 20, and the delay circuit 22 outputs north and 40 degrees. It is delayed to the position of the first pulse of the direction reference pulse. The oscillator circuit 23 operates according to the delay waveform q, and stops when the counting circuit 24 calculates a predetermined number. With respect to the output of the oscillation circuit 23, a trigger is output with a repetition of 12 μs and 30 μs in the north reference pulse system, and a trigger is output with a repetition of 12 μs (or 15 μs) in the 40 ° reference pulse system. Therefore, the address output of the counter circuit 24 coincides with the position of the north and 40 degree azimuth reference pulses. The correction voltage generation circuit 26 is + V
A plurality of parallel circuit for generating a correction voltage by setting in advance a variable resistor in _REF and -V _REF resistance division technique from represented by that positive and negative reference voltage (6.2 V) in, the number , 24 circuits each for pulse width system and level system in north direction reference pulse system, 12 circuits each for pulse width system and level system in 40 degree direction reference pulse system (Y mode 1
3 circuits) are prepared. The multiplexer circuit 25 is a multiplexer which is switched by the address signal (5 bits for the north azimuth reference pulse system and 4 bits for the 40 ° azimuth reference pulse system) from the above-mentioned counting circuit 24.
6 parallel signals are converted to serial. The output waveform t of the multiplexer circuit 25 is applied to the output circuit 27 that performs gain setting and impedance conversion, and is output as a correction voltage.

Immediately after the north and 40 degree azimuth reference pulse (2
Since the squitter (about ms) is affected by the azimuth reference pulse, a signal for correcting this is added to the multiplexer circuit 25.

[0030]

As described above, according to the present invention, the control system is stabilized by using the correction means of the open loop system, and the correction voltage is given as the optimum constant value from the beginning, so that the response is quick. Also, since there is no minimum bit error as in digital control, there is an effect of reducing the amplitude fluctuation of the transmission output.

Further, an address generator, a correction voltage generating circuit,
Also, since the multiplexer circuit has a simple circuit structure and is easy to understand, maintenance is easy, and since the circuit does not require a high-speed element, there is an effect of eliminating malfunction due to a timing error.

The inputs are north and 40, which are conventionally used.
Since it has only the azimuth reference pulse gate, it can be compatible with any circuits of conventional equipment.

[Brief description of drawings]

FIG. 1 is a block diagram of a transmitter having an azimuth reference pulse correction voltage generator according to an embodiment of the present invention.

FIG. 2 is a block diagram of an azimuth reference pulse correction voltage generator of the transmitter of FIG.

FIG. 3 is a signal waveform diagram of each part of the azimuth reference pulse correction voltage generator of FIG.

FIG. 4 is a pulse configuration diagram of a transmission output of the takan device.

FIG. 5 is a block diagram of a transmitter having a conventional azimuth reference pulse correction voltage generator.

6 is a block diagram of an azimuth reference pulse correction voltage generator of the transmitter of FIG.

[Explanation of symbols]

 16 Direction Reference Pulse Correction Voltage Generator 20 Address Generator 21 Differentiation Circuit 22 Delay Circuit 23 Oscillation Circuit 24 Counting Circuit 25 Multiplexer Circuit 26 Correction Voltage Generation Circuit 27 Output Circuit

Claims (3)

[Claims] 1. A correction reference voltage of a modulation waveform for transmission is received by receiving an azimuth reference pulse gate signal indicating a position of a position azimuth reference pulse train consisting of sequentially generated first to n-th (n is an integer of 2 or more) pulses. In the azimuth reference pulse correction voltage generator that generates the first to nth correction voltages corresponding to the first to nth pulses, the first to nth correction voltage generating devices generate the first to nth correction voltages. a correction voltage generation circuit having n resistance division circuits; receiving the azimuth reference pulse gate signal, sequentially outputting first to nth address signals indicating positions of the first to nth pulses of the azimuth reference pulse train, Generate address generator;
The first to nth pulses of the azimuth reference pulse train, which are connected to the address generator and the first to nth resistance division circuits, and are indicated by the first to nth address signals. And a selection circuit for sequentially outputting the first to nth correction voltages corresponding to the azimuth reference pulse correction voltage generator. 2. An address generator, which receives the azimuth reference pulse gate signal, detects a rising portion of the azimuth reference pulse gate signal, and generates a rising detection pulse; and a differentiating circuit; connected to the differentiating circuit, The rising detection pulse is the first pulse of the azimuth reference pulse train.
A delay circuit that delays as a delayed rising edge detection pulse until the point in time when the pulse is generated; is connected to this delay circuit, operates with the delayed rising edge detection pulse, and corresponds to the first to nth pulses of the azimuth reference pulse train. First to nth
An oscillator circuit that sequentially generates the clock pulses; and that is connected to the oscillator circuit and counts the first to nth clock pulses as first to nth count values, and the first to nth counters. The numerical value is the first of the azimuth reference pulse trains.
2. The azimuth reference pulse correction voltage generator according to claim 1, further comprising: a counting circuit that sequentially outputs the first to nth address signals indicating the position of the nth pulse. 3. The azimuth reference pulse train, wherein the selection circuit is connected to the address generator and the first to nth resistance division circuits, and is indicated by the first to nth address signals. A multiplexer circuit for sequentially selecting and outputting the first to nth correction voltages corresponding to the first to nth pulses of; and a gain for an output voltage of the multiplexer circuit, which is connected to the multiplexer circuit. 3. An azimuth reference pulse correction voltage generator according to claim 1, further comprising: