JPH0816650A - Logic synthesization and layout arrangement wiring device - Google Patents

Abstract

PURPOSE:To provide a logic synthesization and layout arrangement wiring device for shortening the length of connecting wiring from a power source/ ground cell to a logic cell. CONSTITUTION:This device is provided with a net list input part 5, layout cell arrangement condition setting part 3, connection existence probability extracting part 6 for calculating probability for the logic cell connected to the power source/ground cell to exist in an area to arrange an unadjacent logic cell, addition probability judging part 7 for judging the addition of the power source/-ground cell when the calculated probability is higher than a specified value, and adding part 8 for adding the power source/ground cell. Thus, degradation in the characteristics of a semiconductor can be minimized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for performing logic synthesis and layout placement / wiring in logic / circuit design of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 12 is a block diagram of a conventional logic synthesizing and layout placement and routing apparatus. 1 is a logic synthesizing section for performing logic synthesis based on function description data, and 2 is a netlist from the logic synthesized data. A netlist creation section that creates
Reference numeral 3 is a layout cell placement condition setting unit that sets cell placement conditions on the layout, and 4 is a layout placement and wiring unit that performs cell placement and routing on the layout based on the netlist and the set layout cell placement conditions.

In the conventional device configured as described above, first, if there is a node N01 whose logic value is fixed to 1 from the function description data, one power supply cell is mapped on the logic circuit and connected to the node. A logic circuit diagram (netlist) is created so as to be connected to each logic cell via. FIG. 13 is an example of a netlist created by logical synthesis. If the node N01 is a node whose logic value is fixed at 1, the power supply cell I01 is mapped and connected to the node N.
The logic cells I02, I03, I04, and I06 are connected via 01. Next, as conditions for arranging the logic cells on the layout, the number of logic cell arrangement stages and the length per logic cell arrangement region are set. Layout placement and routing is performed based on the set conditions and the netlist created above. In this case, as many logic cells (for example, I011 power supply cells) as many as exist in the logic circuit diagram are placed on the layout. Then, wiring between the logic cells is performed. FIG. 14 is a layout diagram created by arranging and wiring logic cells based on the netlist shown in FIG. In this case, one power supply cell I01 is connected to the logic cells I02, I03, I04, I06, and each connection is by one node N01.

[0004]

In the conventional logic synthesis and layout placement and routing apparatus as described above, the number of logic cells existing in the netlist created by the logic synthesis is placed on the layout. When the number of logic cells connected to one power supply cell increases, the wiring length of the node connecting them increases, and the characteristics of the semiconductor deteriorate.

The present invention has been made in order to solve the above-mentioned problems, and its object is to perform logic synthesis and to suppress the connection wiring length from a power / ground cell to a logic cell to a specified value or less. A layout layout wiring device is obtained.

[0006]

In the logic synthesis and layout placement and routing apparatus according to the present invention, means for inputting a netlist, means for setting the number of logic cell placement area stages as layout cell placement conditions, the netlist and the above Based on the set layout cell placement conditions, means for determining whether to add a power / ground cell, means for adding a power / ground cell as a result of this determination, and added power / ground cell In consideration of the above, logic synthesis is performed to modify the netlist.

Further, the logic cell connected to the power supply / ground cell is provided with a means for calculating the probability that the logic cell exists in the non-adjacent logic cell arrangement areas, and a means for comparing the calculated probability with a specified value. is there.

Further, it is provided with means for extracting the number of logic cells connected to the power supply / ground cell, and means for comparing the extracted number of logic cells with a prescribed value.

Further, there is provided means for extracting the wiring length of the node connected to the power supply / ground cell from the back annotation data, and means for comparing the extracted wiring length with a specified value.

Further, a means for setting a priority order in the connection relation between the logic cells arranged in one logic cell arrangement area, and a node having a high priority order for the prioritized nodes It is provided with a cell layout structure creating means for layering logic so as to fit in one logic cell layout area.

Further, the prioritization of the connection relation is made by the power source /
The highest node is connected to the ground cell.

[0012]

In the logic synthesis and layout placement and routing apparatus configured as described above, it is determined whether or not the power supply / ground cell is added based on the input netlist and layout cell placement conditions, and the addition is made. In that case, logic synthesis is performed in consideration of the power supply / ground cell.

Further, the probability that the logic cells connected to the power / ground cells exist in the non-adjacent logic cell arrangement areas is calculated.
A ground cell is added.

Further, when the number of logic cells connected to the power / ground cell is a specified value or more, the power / ground cell is added.

Further, the wiring length of the node connected to the power / ground cell is extracted from the back annotation data, and the power / ground cell is added when the wiring length is equal to or more than the specified value.

Further, priority is given to the connection relationship between the logic cells arranged in one logic cell arrangement area, and the logic is hierarchized so that the connections having the highest priority are contained in one logic cell arrangement area in order. To be done.

If there is a node connected to the power / ground cell, the power / ground cell is added to the logic cell arrangement area.

[0018]

【Example】

Example 1. FIG. 1 is a functional block diagram showing a logic synthesis and layout placement and routing apparatus according to an embodiment of the present invention.
4 to 4 are the same as or equivalent to those of the conventional one shown in FIG. 12, but the logic synthesizing unit 1 includes the power supply / ground cell adding unit 8
If the power / ground cell is added in step 2, logic synthesis is performed without deleting it. Further, in that case, the netlist creating unit 2 becomes a netlist to which power / ground cells are added. Reference numeral 5 is a netlist input section for inputting a logic circuit at the netlist level, and 6 is a probability that logic cells having power / ground cells as inputs are present in non-adjacent logic cell placement regions based on the input netlist and layout placement conditions. A power source / grand cell connection existence probability extracting unit for calculating, and a power source / ground cell for determining whether or not the probability calculated by the power source / ground cell connection existing probability extracting unit 6 is equal to or more than a predetermined specified value. Additional probability judgment unit,
Reference numeral 8 denotes a power supply / ground cell addition unit that adds a power supply / ground cell when the probability calculated by the power supply / ground cell addition probability determination unit 7 is a specified value or more.

The operation of the logic synthesis and layout placement / routing apparatus having the above-described configuration will be described with reference to the flow chart of FIG. First, the netlist input unit 5 reads the netlist of the logic circuit (S
1). Further, the layout cell arrangement condition setting unit 3 sets the number M of logic cell arrangement stages (S2). Next, in the power supply / ground cell connection existence probability extraction unit 6, when there are a plurality of logic cells connected to the power supply / ground cells, the above logic cells are placed in the non-adjacent logic cell placement regions according to the following expression (A). The probability P that will be arranged is calculated (S3). However, P1 in the formula (A) is the probability that the power supply / ground cell and the logic cell connected thereto are arranged in the same logic cell arrangement region, and P2 is the power supply / ground cell and the logic cell connected thereto are adjacent to each other. It is the probability of being placed in a matching logic cell placement area. P = 1- (P1 + P2) ... (A) P1 = M (VG / (M.BC)) (bc / (M.BC)) P2 = _M C _N (VG / (M · BC)) (1- (BC-bc) / (M · BC)) where BC is the cell area of the entire logic cell in the netlist bc is the entire logic cell connected to the power / ground cell Cell area VG: Total area of power supply / ground cell M: Number of logic cell arrangement area stages N: Number of power supply / ground cells (initial value = 1)

Next, the power / ground cell addition probability judgment unit 7 compares the calculated probability P with a prescribed value γ (S
4) If the probability P is greater than or equal to the specified value γ, the power supply / ground cell adding unit 8 adds one power supply / ground cell (S5). When the power supply / ground cell is added, the process returns to S3, and the probability P is recalculated with one power supply / ground cell added. If the probability P becomes less than the specified value γ, the logic synthesis unit 1 performs logic re-synthesis while holding the number of power supply / ground cells added in the processing up to that point (S6). After that, the netlist creation unit 2 outputs the netlist (S7), and the layout placement / wiring unit 4 places and routes the layout based on the netlist and the layout placement conditions set previously (S8). .

For example, if the above-mentioned probability is calculated by inputting the netlist shown in FIG. 13 and the number of power supply / ground cells is added so that the value is less than a specified value, logic recomposition is performed. For example, the power supply I01B is added at the position shown in FIG. 3, and the logic cells I04 and I06 are connected at the node N01B. Further, FIG. 4 is a layout diagram in which layout placement and wiring are performed based on the netlist shown in FIG.
A power source I01B is added to the cell placement area 3. As a result, as compared with the conventional layout diagram (FIG. 14) in which the layout is arranged and routed based on the netlist shown in FIG. 13, the connection wiring length from one power supply cell to the logic cell is significantly shortened. I understand. As described above, by adding the power / ground cells until the probability that the logic cells having the power / ground cell as an input exist in the logic cell placement area that is not adjacent to each other becomes less than the specified value,
The wiring length from the ground cell can be shortened.

Example 2. In the first embodiment, when there are a plurality of logic cells connected to the power supply / ground cell, the probability that the logic cells will be arranged in the non-adjacent logic cell arrangement regions is calculated, and the probability is calculated. Although the addition of the power supply / ground cell is determined by comparing with the specified value, the same effect can be obtained even if the number of logic cells connected to the power supply / ground cell is compared with the specified value.

Example 3. FIG. 5 is a configuration diagram showing a logic synthesis and layout placement and routing apparatus according to the third embodiment,
In the figure, the same or corresponding parts as those of the conventional device or the device according to the first embodiment are designated by the same reference numerals. Reference numeral 9 is a power / ground connection wiring length extraction unit that extracts the wiring length of the node connected to the power / ground from the data (wiring length, capacitance, resistance, etc.) extracted by the layout back annotation data extraction unit 10. , 11 are power supply / ground cell addition determination units that make a power supply / ground cell addition determination based on the wiring lengths extracted by the power supply / ground connection wiring length extraction unit 9.

Next, the operation will be described with reference to the flowchart of FIG. First, the layout back annotation data extraction unit 10 extracts back annotation data (T1). The back annotation data is data for adding physical data on the actual layout to the netlist.
Next, as in the first embodiment, the logic circuit is read at the netlist level (T2) and the layout arrangement condition is set (T3). Next, the node wiring length is extracted from the data extracted in T1 (T4). FIG. 7 is a diagram showing an example of the wiring length of each node in the back annotation data of the layout diagram (FIG. 14) corresponding to the netlist shown in FIG. 13, in which the node N01 is connected to the power supply / ground. It is a node. Subsequently, the wiring length of the node N01 connected to the power supply / ground is compared with a specified value γ (T5),
If it is equal to or more than the specified value, a power supply / ground cell is added (T6). As a result, also in this case, as in the first embodiment, the netlist as shown in FIG. 3 is created, and the layout diagram (FIG. 4) is created based on the netlist. In FIG. 8, the above process is performed when the wiring length 130.5 μm of the node N01 is equal to or greater than the specified value γ, and the layout diagram (FIG. 4) created as a result is predicted based on the data of FIG. 7. It is a diagram showing the wiring length of each node, the wiring length of the node N01 is, for example,
It is as short as 40.5 μm. After that, the above process is repeated until the length of the power supply connection wiring becomes less than the specified value. If the power supply connection wiring length is less than the specified value, as in the first embodiment, the power supply / ground cell added in the processing up to that time is held,
Logic re-synthesis, netlist output, and layout wiring are performed (T7 to T9). As described above, since the power supply / ground cell is added until the wiring length of the node connected to the power supply / ground becomes less than the specified value, the wiring length from the power supply / ground cell can be shortened.

Example 4. FIG. 9 is a block diagram showing a logic synthesis and layout placement / wiring device according to the fourth embodiment. In the figure, 1 to 5 are the same as or equivalent to those of the conventional or the above-mentioned first to fourth embodiments. Reference numeral 12 is an inter-logical cell connection relationship ranking unit that sets the connection relationship between the logic cells based on the netlist input by the netlist input unit 5, and 13 is an inter-logical cell connection relationship ranking unit 12 Ranking and layout cell placement condition setting unit 3 set in
The logical cell placement structure creating unit sets the logical cells that fit within the same logical cell placement area as one layer based on the logical cell placement conditions set in step 1.

Next, the operation will be described with reference to the flowchart of FIG. First, read the netlist (U1) and set the layout placement conditions (U
2). Next, the logic cells arranged in the same logic cell arrangement area are extracted from the netlist and the layout arrangement condition, and the nodes connected to the power supply / ground cells are ranked as the highest in the connection relation between the logic cells. Attach (U
3). Then, the arrangement structure of the logic cells is changed so that the highest priority order and the predetermined priority order are included in one logic cell placement area (U4). In other words, power supply /
Since the node connected to the ground cell has the highest priority, in the placement area where there is a logic cell connected to the power supply / ground cell, first, the power supply / ground cell is added to fit within the placement area. Become. Similarly, the logic cells connected to the nodes up to the predetermined rank are also added to the placement area. Further, after that, when the layout is arranged and wired, the logic circuits in the respective arrangement areas are hierarchized as one block so that the blocks are laid out as one block (hierarchy).

Thereafter, logic re-synthesis is performed, netlist output and layout placement / wiring are performed (U5 to U7) in the same manner as in the first embodiment, with the power supply / ground cell added and the hierarchical state maintained. ). In FIG. 11, based on the netlist shown in FIG. 13, only the nodes connected to the power / ground cells (only those with the highest priority) are set to 1
It is a figure which shows the netlist which changed the arrangement structure so that it may be accommodated in one logic cell arrangement | positioning area | region, and is a power supply / ground inside each logic cell arrangement | positioning area I101, I102, I103, I104, and I105. A power supply / ground cell I01 is added in a region (I101, I102, I103, I104) where a logic cell connected to the cell exists. In the logic cell arrangement region I105, since no logic cell connected to the power / ground cell exists, no power / ground cell is added. As described above, when there is a logic cell connected to the power supply / ground cell, the power supply / ground cell is added so that the power supply / ground cell fits within the logic cell arrangement area. The wiring length can be shortened. In the above description, the node connected to the power / ground cell is ranked highest, but when the node connected to another specific logic cell is ranked highest, the logic cell is first placed in one placement area. It becomes possible to shorten the wiring length from the logic cell.

Example 5. In any of the above-mentioned first to fourth embodiments, the addition / decision of the power supply / ground cell is made by each method based on the initially created netlist, and in the case of addition, the netlist is corrected, From the result, layout placement and routing was performed, but based on the layout diagram created by layout placement and routing from the netlist created in the initial stage, the addition / decision of the power supply / ground cell is made in the same way and added. In that case, the same effect can be obtained even if the layout diagram is modified.

[0029]

Since the present invention is constructed as described above, it has the following effects.

Based on the input netlist and layout cell placement conditions, it is determined whether or not to add a power / ground cell. When adding, logic synthesis is performed in consideration of the power / ground cell. Since this is done, the wiring length from the power supply / ground cell can be shortened and the deterioration of the semiconductor characteristics can be made minute.

Further, the probability that a logic cell having a power / ground cell as an input is present in a logic cell arrangement region which is not adjacent is calculated, and if the probability is equal to or more than a specified value, the power / ground cell is added. Therefore, the additional judgment of the power supply / ground cell can be accurately made.

Further, since the power supply / ground cell is added when the number of logic cells connected to the power supply / ground cell is equal to or more than the specified value, it is possible to quickly determine whether the power supply / ground cell is added.

Further, since the power supply / ground cell is added when the wiring length of the node connected to the power supply / ground is equal to or more than the specified value, it is possible to surely make the addition judgment of the power supply / ground cell.

Further, since the connection relations within one logic cell arrangement area are prioritized and the arrangement structure is changed so that the connection relationships are arranged within the arrangement area in descending order of priority, the wiring length can be shortened. it can.

Since the node connected to the power supply / ground cell has the highest priority, the power supply / ground cell is added to fit in one arrangement area, and the wiring length from the power supply / ground cell is shortened. be able to.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a logic synthesis and layout placement / routing apparatus according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a processing flow of the logic synthesis and layout placement and routing apparatus according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a netlist when a power supply / ground cell is added by the logic synthesis and layout placement and routing apparatus according to the first exemplary embodiment of the present invention.

FIG. 4 is a layout diagram in which layout placement and wiring are performed based on the netlist of FIG.

FIG. 5 is a configuration diagram showing a logic synthesis and layout placement / wiring device according to a third embodiment of the present invention.

FIG. 6 is a flowchart showing a processing flow of a logic synthesis and layout placement / wiring apparatus according to a third embodiment of the present invention.

FIG. 7 is a diagram showing the node wiring length in the back annotation data for the layout corresponding to the netlist input in the logic synthesis and layout layout wiring apparatus according to the third embodiment of the present invention.

FIG. 8 is a diagram showing predicted node wiring lengths for a layout corresponding to a netlist after power is added by a logic synthesis and layout placement and routing apparatus according to a third exemplary embodiment of the present invention.

FIG. 9 is a configuration diagram showing a logic synthesis and layout placement / routing apparatus according to a fourth embodiment of the present invention.

FIG. 10 is a flowchart showing a processing flow of a logic synthesis and layout placement / wiring device according to a fourth embodiment of the present invention.

FIG. 11 is a diagram showing a netlist when a power supply / ground cell is added by the logic synthesis and layout placement / routing apparatus according to the fourth embodiment of the present invention.

FIG. 12 is a configuration diagram showing a conventional logic synthesis and layout placement and routing apparatus.

FIG. 13 is a diagram showing an example of a netlist input in the conventional device and the device according to each embodiment of the present invention.

14 is a layout diagram in which layout layout and wiring are performed based on the net list of FIG. 12 in the conventional apparatus.

[Explanation of symbols]

1 logic synthesis unit, 2 netlist creation unit, 3 layout cell placement condition setting unit, 4 layout placement and routing unit,
5 netlist input section, 6 power supply / ground cell connection existence probability extraction section, 7 power supply / ground cell addition probability determination section, 8 power supply / ground cell addition section, 9 power supply / ground connection wiring length extraction section, 10 layout back annotation data Extraction unit, 11 power supply / ground cell addition determination unit, 12 logic cell connection relation ranking unit, 13 logic cell placement structure creation unit in the same cell placement region.

Claims (6)

[Claims] 1. A means for inputting a netlist of a logic circuit, a means for setting the number of logic cell layout regions as a condition for arranging logic cells on a layout (hereinafter referred to as a layout cell layout condition), the netlist and the setting. Based on the layout cell placement conditions that have been determined, a method for determining whether to add a power / ground cell, a method for adding a power / ground cell as a result of the above determination, and a power / ground cell added A logic synthesis and layout placement and routing apparatus comprising means for performing logic synthesis to correct the netlist, and performing layout placement and routing based on the revised netlist. 2. A logic cell connected to a power supply / ground cell, comprising means for calculating a probability that the logic cell exists in a non-adjacent logic cell placement area, and means for comparing the calculated probability with a prescribed value, 2. The logic synthesis and layout arrangement / wiring device according to claim 1, wherein it is determined that the power supply / ground cell is added when is greater than or equal to the specified value. 3. A means for extracting the number of logic cells connected to a power supply / ground cell, and means for comparing the extracted number with a specified value, wherein the number of the logic cells is equal to or more than the specified value. The logic synthesis and layout placement and routing apparatus according to claim 1, wherein it is determined that a power supply / ground cell is added. 4. A means for extracting the wiring length of a node connected to a power supply / ground cell from back annotation data (data for adding physical data on an actual layout to a netlist), and the extracted wiring length. 2. The logic synthesis and layout arrangement / wiring device according to claim 1, further comprising means for comparing with a specified value, wherein when the wiring length is equal to or larger than the specified value, it is determined to add a power supply / ground cell. 5. A means for setting prioritization to a connection relationship between logic cells arranged in one logic cell arrangement area,
3. The cell placement structure creating means for hierarchically arranging logic so that nodes having higher priorities are sequentially placed in one logic cell placement area with respect to the prioritized nodes. The described logic synthesis and layout placement and routing device. 6. The logic synthesis and layout placement and routing apparatus according to claim 5, wherein the connection connection is prioritized so that the node connected to the power supply / ground cell is the highest.