JPH08163138A - Atm header check circuit - Google Patents

Abstract

PURPOSE: To increase the working speed and to reduce the constitution scale of an ATM header check circuit by deciding a valid or invalid atate of a received ATM cell based on the result of comparison performed between the header value of the received ATM cell and the ATM header value which is read out of a storage part. CONSTITUTION: The ATM header value up to the largest number (n) of pieces used in an network(NW) is set at a connection information storage pert 1 based on the connection information requested by an network(NW) management part 4 for communication. An ATM cell reception part 2 receives an ATM cell and reads one or every (m) pieces of ATM header value stored in the part 1 to give these header value to an ATM header check part 3. The part 3 successively compares the header value of the ATM cells received at the part 2 with the ATM header set value read out of the part 1 and outputs the valid/invalid decision result to the part 4. Thus it is possible to prevent the increase of scale of a comparator that is caused by the increase of connections and also to increase the working speed and to reduce the scale of an ATM header check circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM header check circuit, and more particularly to an ATM header check circuit for determining validity / invalidity of an ATM cell received in an ATM layer of B-ISDN.

The header of the ATM cell used in the ATM layer of B-ISDN is, as shown in FIG. 15, in the ATM switching network EX or in the ATM switching network EX or ATM.
ATM at the end of ATM layer such as terminal T
Information that indicates whether or not the cell is passing through the network correctly is stored.

FIG. 16 shows the structure of an ATM cell and its ATM header. The NNI shown in FIG. 16A is a display at a network interface reference point, and the NNI shown in FIG.
The UNI shown in is displayed at the user network interface reference point.

Further, V included in an ATM header composed of 5 bytes, which is commonly shown in (1) and (2) of FIG.
PI / VCI is a routing bit in an ATM connection and represents a virtual path / channel of ATM. The PTI is a payload type indication indicating whether the information field of the ATM cell is user information or network information. Further, CLP represents the priority of the cell, HEC is a header error control byte, and AT
The calculated value of CRC-8 of M header 5 bits is stored and also used for cell synchronization detection.

Further, GFC shown in FIG.
It is a byte for generative flow control of I only and is used by multiple users.

At the end of the ATM layer, VPI / VCI, which is a virtual path and / channel, is fixedly provided or flexibly provided by call control or the like to transmit and receive ATM cells.

Therefore, it is necessary to compare the VPI / VCI provided in the receiving section of the ATM layer terminating section with the VPI / VCI of the received ATM cell to determine whether or not the cell should be terminated.

FIG. 17 is a diagram showing the state of fetching such an ATM cell, in which VPI / V is provided at the ATM termination section a.
The CI value a is assigned, and VPI /
VCI value b is assigned and V of ATM header
ATM cells with PI / VCI values of a, b, c, etc. are flowing.

In this case, the ATM terminal parts a and b take in the ATM cells a and b having the same VPI / VCI value.

For this reason, when receiving an ATM cell at the end of the ATM layer, it is necessary to check the ATM header pattern to determine whether or not the ATM cell should be fetched.

[0011]

2. Description of the Related Art In order to determine whether an ATM cell is valid or invalid in the ATM layer of B-ISDN, conventionally,
The header pattern is checked by providing a circuit for individually comparing the maximum number of ATM header values used in the network with the ATM header value of the received ATM cell.

[0012]

As described above, since a circuit for comparing header values is provided in the conventional art,
As the number of network connections increases, it becomes necessary to increase the number of such comparison circuits, which has a drawback of increasing the hardware scale.

Therefore, the present invention realizes an ATM header check circuit capable of preventing an increase in hardware scale due to an increase in connections and configuring more connections at a higher speed and with a reduced hardware size. With the goal.

[0014]

In order to achieve the above object, an ATM header check circuit according to the present invention is shown in FIG.
As shown in principle, the connection information storage unit that can set up to n ATM header values, which is the maximum number used in the network according to the connection information requested by the network management unit, and the connection when the ATM cell is received. The ATM cell receiving unit that controls the reading of the ATM header value from the information storage unit matches the header value of the ATM cell received from the ATM cell receiving unit with the ATM header value read from the connection information storage unit. And an ATM header check unit that outputs the determination result to the network management unit.

In the above ATM header check circuit, the connection information storage unit can set up to n × m (m> 1) ATM header values, and the AT
The M cell receiving unit controls the reading of the ATM header value from the connection information storing unit by m times for n times, and
The TM header check unit can perform the comparison of the ATM headers up to m matches.

Furthermore, in the above ATM header check circuit, the connection information may further include a bit indicating whether the ATM header value is valid or invalid for the network.

Further, according to the present invention, a connection in which valid / invalid information can be set at a corresponding location using up to n ATM header values, which is the maximum number used in the network, as an input address according to the connection information requested by the network management unit for communication. An information storage unit, and an ATM cell reception unit which, when an ATM cell is received, uses the header value of the ATM cell as the input address to control the reading of the valid / invalid information from the connection information storage unit and gives it to the network management unit. , Can be provided.

Further, according to the present invention, if a fixed value is included in the maximum number n of ATM header values used in the network according to the connection information requested by the network management unit, an AT other than the fixed value is included.
M header value as an input address, valid / invalid information is set in the corresponding portion, and the fixed value can be set in the connection information storage section, and the fixed value of the header value of the ATM cell when the ATM cell is received. ATMs other than
An ATM cell receiving unit that controls reading of the valid / invalid information and the fixed value from the connection information storage unit using the header value as the input address, and a fixed value in the header value of the ATM cell received from the ATM cell receiving unit. An ATM header check unit that compares the valid fixed value of the valid / invalid information read from the connection information storage unit until it matches and outputs a determination result to the network management unit. Can also be provided.

In the above ATM header check circuit, a channel number required by the network management unit may be added to the valid / invalid information.

[0020]

In the present invention shown in FIG. 1, the ATM header value requested for communication by the network management unit is set as connection information in the connection information storage unit. This connection information contains up to n ATM header values, which is the maximum number used in the network.

When the ATM cell receiving unit receives the ATM cell, the AT stored in the connection information storage unit
The M header values are read one by one or m by one.

The ATM header check unit sequentially compares the header value of the ATM cell received by the ATM cell receiving unit with the ATM header set value read from the connection information storage unit, and outputs the determination result.

As a result, one or an arbitrary number of comparison circuits can be used to eliminate the need for a connection comparison circuit.
TM header check can be realized.

Further, by addressing the ATM header value, the ATM cell receiving section provides the connection information storing section with the information having the ATM header value as an address. Since the valid or invalid information is set as connection information from the network management unit in correspondence with the ATM header value of, the header value of the received ATM cell is given as an address to the connection information storage unit, and the corresponding address is obtained. Since information indicating validity or invalidity is set in the location and is read out, this can be sent to the network management unit as a determination result as in the above.

As a result, it is only necessary to read the information once from the recognition of the header value of the received ATM cell, and it is possible to realize high speed processing and more connections.

[0026]

FIG. 2 shows an embodiment of an ATM header check circuit (1) according to the present invention, in which a connection information storage unit in which connection information is set from a network management unit is received, and an ATM cell is received. The ATM cell receiving unit that detects and controls the reading of the connection information storage unit, and compares the header value of the ATM cell received by the ATM cell receiving unit with the ATM header value read from the connection information storage unit. The ATM header check unit notifies the network management unit 4 of the comparison result.

FIG. 3 shows an example of the connection information set in the connection information storage section by the network management section. In this example, the connection relating to 32 kinds of ATM cells which is the maximum number used in the network. Information Nos. 1 to 32 are set. In addition,
It is not limited to these 32 types, and various other values are possible.

Each connection information is composed of a 32-bit ATM header and a 1-bit valid / invalid bit.
It consists of 3 bits.

Therefore, the network management unit 3 based on the connection assigned on the ATM connection.
Up to two types of ATM header values of cells to be stored in the connection information storage unit and connection information of valid / invalid bits can be set.

As described above, the 32-bit ATM header in the connection information is the 12-bit VPI.
And 16-bit VCI, 3-bit PTI, and 1-bit CLP.

After the connection information is set in the connection information storage unit by the network management unit in this way, when the ATM cell reception unit receives an ATM cell, the ATM cell reception unit controls the reading of the connection information storage unit. The connection information is given to the ATM header check section.

In this case, as the control signal given from the ATM cell receiving section to the connection information storing section, 32 kinds of ATM header values (32 bits) shown in FIG. 3 are used.
5 bit address so that the ATM cell receiving unit can be addressed, or the ATM cell receiving unit only notifies the connection information storage unit that the ATM cell has been received.
The cell header values may be read sequentially.

In this case, the data read from the connection information storage section is 33-bit parallel bit data, and a 32-bit ATM header value and 1 bit as valid / invalid information are given to the ATM header check section.

Therefore, the ATM header check unit receives the ATM header value received from the ATM cell receiving unit (which virtually passes through the ATM cell receiving unit), and uses the connection information received from the connection information storage unit as shown in FIG. The 32 types of information shown in are compared one by one one by one.

Then, as a result of the comparison, when the valid / invalid bit is valid indication (= 1) and the ATM header values match, it is determined that the ATM cell should be fetched. When all the connection information Nos. 1 to 32 do not match, it is determined as an invalid cell.

The result of this determination is given to the network management unit.

FIG. 4 specifically shows the ATM header check unit. The header value from the ATM cell reception unit and the connection information from the connection information storage unit are compared by one comparison circuit COMP, and the comparison result is shown. The state given to the network management unit is shown, and it can be seen that only one comparison circuit COMP is required even if the connection information increases.

FIG. 5 shows an embodiment (2) of the ATM header check circuit according to the present invention. In this embodiment, as shown in FIG. 6, the network management unit handles up to 128 kinds of ATM cells. A to check
The TM header value and connection information of valid / invalid bit can be set.

In this case, 128 types of connection information are divided into four, and the four connection information are collected into an ATM.
This is what the header check section tries to check.

That is, the number of ATM header values stored in the connection information storage section is 32 types × 4 = 128.
This type of connection information is composed of a 32-bit ATM header and 1-bit valid / invalid bit.

As a result, in the ATM header check unit, as shown in FIG. 7, four comparison circuits COMP1 to COMP1 for connection information A to D (see FIG. 6), respectively.
COMP4 is provided so that the comparison results A to D are output as judgment results from each and are given to the network management unit.

In the operation of such an embodiment, the AT
When the M cell receiving unit receives the ATM cell, it reads 128 types of connection information from the connection information storage unit, four by four. Therefore, as shown in FIG. 5, the address given from the ATM cell receiving section to the connection information storing section is such that 32 pieces of connection information groups are read out by the 5-bit address data as in the embodiment of FIG. .

In this way, the ATM header value (32
4 bits and 4 valid / invalid bits (1 bit)
A total of 132 bits of parallel data are sent to the ATM header check unit, and the ATM header check unit gives the ATM header value input from the ATM cell receiver in common to the comparison circuits COMP1 to COMP4 shown in FIG. Compare with A to D, respectively.

As a result of the comparison, it is determined that the cell is to be taken in only when the valid / invalid bit is valid indication (= 1) and the ATM header values match, and the connection information is determined.
If all of No. 1 to 128 do not match, it is judged as an invalid cell and this comparison result is given to the network management unit.

FIG. 8 shows an embodiment (3) of the ATM header check circuit according to the present invention. In this embodiment, as shown in hexadecimal (h) in FIG. The address of the connection information stored in the connection information storage unit is made to correspond one-to-one, and only the valid / invalid bit is connected in the address of the connection information storage unit 1 thus corresponded, as shown in FIG. It is stored as information.

That is, the network management unit 4 sets the valid bit "1" in the address of the corresponding ATM header value in the connection information storage unit for the connection for which the communication is requested.

When the ATM cell receiving unit receives the ATM cell, the ATM header value is recognized and the AT
By supplying the M header value to the connection information storage unit as an address, the valid / invalid bit stored at the corresponding address as shown in FIG. 9B is read from the connection information storage unit 1.

When this valid / invalid bit is set to valid (= 1), it becomes a valid cell, and the invalid bit (=
When 0) is set, it becomes an invalid cell and is given to the network management unit as a determination result.

In this way, the address data given from the ATM cell receiving section to the connection information storing section becomes parallel address data of 4 bytes (32 bits) when the connection information is 32 kinds as described above.

FIG. 10 shows an embodiment (4) of the ATM header check circuit according to the present invention. This embodiment is the embodiment (1) shown in FIG. 1 and the embodiment (3) shown in FIG. )
It is equivalent to the combination of and.

That is, when it is known in advance that only one type of VPI is received in the ATM cell processing, the fixed value VPI in the ATM header and the variable value VCI are separated. It is focused on that more efficient processing can be performed if header check is performed.

Therefore, the network management unit 4 first sets the VPI set value in a predetermined address in the connection information storage unit 1 as shown in FIG. 11 (2), and the same as in FIG. 9 (2). As shown in 11 (3), the valid / invalid bit is set corresponding to the address of the connection information storage section.

Then, as shown in FIG.
There is a one-to-one correspondence between the header value and the address of the connection information storage unit, and the VCI value of the received ATM cell (16 bits) is variable, and the VCI value is directly used as the address of the connection information storage unit. By storing the valid / invalid bit in the address, the valid setting is made for the VCI of the ATM cell for which the communication is requested.

In the operation of such an embodiment, the AT
When the M cell receiving unit receives the ATM cell, it reads the connection information from the address of the ATM header value of the connection information storage unit, that is, the address of the VCI value, and gives it to the ATM header check.

The ATM header check unit, as shown in FIG. 12, includes one comparison circuit COMP and one determination circuit J.
Of the ATM header input from the ATM cell reception unit, the VPI value is read from the connection information storage unit and the comparison circuit CO.
Compare in MP.

If the result of this comparison is that they match, if the valid / invalid bit read from the connection information storage unit as connection information in the determination circuit JD is valid setting (= 1), it is determined to be a valid cell. This is notified to the network management unit 4.

On the other hand, when the VPI values do not match in the comparison circuit COMP, or V in the comparison circuit COMP.
Even if the PI values match, if the read valid / invalid bit is set to invalid (= 0), the determination circuit JD determines that the cell is an invalid cell and notifies the network management unit.

FIG. 13 shows an embodiment (5) of the ATM header check circuit according to the present invention. This embodiment is a modification of the addressing embodiment shown in FIG. As shown in FIG. 14 (1), the ATM header value and the address of the connection information storage section have a one-to-one correspondence. Further, as shown in (2) of FIG. The difference is that the channel number CHNo. Is additionally set in addition to the invalid bit.

That is, in the upper layer, there is a limiting condition that the capacity that can be processed is only for 8192 channels, and the network management unit stores the connection information in the connection information storage unit so that the processing can be performed using the channel number. The channel number can be additionally set to.

In the operation of such an embodiment, the network management unit sets the effective bit in the address of the corresponding ATM header value in the connection information storage unit and the channel number for the connection for which the communication is requested.

When the ATM cell receiving section receives the ATM cell, it reads the valid / invalid bit and the channel number as the connection information from the address of the ATM header value in the connection information storage section.

Therefore, the valid / read data thus read
The invalid bit and the channel number are given to the network management unit.

In this embodiment, the ATM header can be checked in any pattern, but since the cells in the upper layer are limited to 8192 channels, the channel number is displayed to display the upper layer. Will help the process. (In order to process ATM header bits, it is necessary to have a processing area for 4294967296 channels.)

[0064]

As described above, the AT according to the present invention
According to the M header check circuit, up to n ATM header values and preferably valid / invalid information, which is the maximum number used in the network, are set in the connection information storage unit according to the connection information requested by the network management unit, When an ATM cell is received, the ATM header value is read from the connection information storage unit, the header value of the received ATM cell is compared with the ATM header check unit, and the comparison result is given to the network management unit. It is not necessary to have a comparison circuit of 1
You can check the header.

Further, by addressing the ATM header value, the address can be calculated from the header value pattern of the received ATM cell, and the valid indication of the cell can be detected from the connection information storage section from the address and the network management section can be notified. Therefore, the validity / invalidity of the cell can be determined by reading the information once from the recognition of the header value of the ATM cell, and a large number of connections can be processed at higher speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing in principle the configuration of an ATM header check circuit according to the present invention.

FIG. 2 is a block diagram showing an embodiment (1) of an ATM header check circuit according to the present invention.

FIG. 3 is a diagram showing an example of connection information stored in a connection information storage unit in the embodiment (1) of the present invention.

FIG. 4 is a block diagram specifically showing an ATM header check unit in the embodiment (1) of the present invention.

FIG. 5 is a block diagram showing an embodiment (2) of the ATM header check circuit according to the present invention.

FIG. 6 is a diagram showing an example of connection information stored in a connection information storage unit in the embodiment (2) of the present invention.

FIG. 7 is a block diagram showing an embodiment of an ATM header check unit used in the embodiment (2) of the present invention.

FIG. 8 is a block diagram showing an embodiment (3) of the ATM header check circuit according to the present invention.

FIG. 9 is a diagram showing an example of connection information stored in a connection information storage unit in the embodiment (3) of the present invention.

FIG. 10 is a block diagram showing an embodiment (4) of the ATM header check circuit according to the present invention.

FIG. 11 is a diagram showing an example of connection information stored in a connection information storage unit in the embodiment (4) of the present invention.

FIG. 12 is a block diagram showing an embodiment of an ATM header check unit in the embodiment (4) of the present invention.

FIG. 13 is a block diagram showing an embodiment (5) of the ATM header check circuit according to the present invention.

FIG. 14 is a diagram showing an example of connection information stored in a connection information storage unit in the embodiment (5) of the present invention.

FIG. 15 is a schematic diagram of a general ATM switching network.

FIG. 16 is a diagram for explaining the structure of a general ATM cell and its ATM header.

FIG. 17 is a block diagram for explaining a situation of fetching an ATM cell.

[Description of Codes] Connection information storage unit ATM cell reception unit ATM header check unit Network management unit In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (6)

[Claims] 1. A connection information storage unit capable of setting up to n ATM header values, which is the maximum number used in the network, according to connection information requested by a network management unit, and the connection information storage unit when an ATM cell is received. From the ATM cell receiving unit that controls the reading of the ATM header value from the ATM cell receiving unit to the ATM cell receiving unit that compares the header value of the ATM cell received from the ATM cell receiving unit with the ATM header value read from the connection information storage unit. An ATM header check circuit comprising: an ATM header check unit that outputs the determination result to the network management unit. 2. The ATM header check circuit according to claim 1, wherein the connection information storage unit can set the ATM header values up to n × m (m> 1), and the ATM cell reception unit The ATM header value is read out from the connection information storage unit every n times and read out.
The TM header check unit compares the ATM header with m
An ATM header check circuit, which is characterized in that the processing is carried out until they match one by one. 3. The ATM header check circuit according to claim 1, wherein the connection information further includes a bit indicating whether the ATM header value is valid or invalid for the network. Header check circuit. 4. A connection information storage unit capable of setting valid / invalid information at a corresponding location using up to n ATM header values, which is the maximum number used in the network, as an input address according to the connection information requested by the network management unit for communication. , An ATM cell receiving unit which, when an ATM cell is received, performs read control of the valid / invalid information from the connection information storage unit using the header value of the ATM cell as the input address, and provides the network management unit with the ATM cell receiving unit, An ATM header check circuit characterized by the above. 5. When a fixed value is included among the maximum number n of ATM header values used in the network according to the connection information requested by the network management unit for communication, an ATM header value other than the fixed value is used as an input address. As a connection information storage unit in which valid / invalid information can be set in the corresponding portion and the fixed value can also be set, and an ATM header value other than the fixed value among the header values of the ATM cell when the ATM cell is received, An ATM cell receiving unit that controls reading of the valid / invalid information and the fixed value from the connection information storage unit as the input address, a fixed value in the header value of the ATM cell received from the ATM cell receiving unit, and the connection Until the valid fixed value of the valid / invalid information read from the information storage unit matches ATM header check circuit determination result performed compare, characterized in that and a ATM header checking unit that outputs to the network management unit. 6. The ATM header check circuit according to claim 4 or 5, wherein a channel number required by the network management unit is added to the valid / invalid information.