JPH08162852A - Mixer circuit - Google Patents

Abstract

PURPOSE: To improve the conversion gain without increasing a DC bias current by applying a lower gate bias to an upper stage FET than that to a lower stage FET. CONSTITUTION: In a mixer circuit where an input signal is fed to a gate terminal G1 of a lower stage FET and a local signal is fed to a gate terminal G2 of an upper stage to extract an output signal from a drain terminal in a cascode circuit including the dual gate FET, a gate bias to be given to the upper stage FET is substantially lower than a gate bias given to the lower stage FET. Thus, the conversion gain and the cubic intercept point are improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mixer circuit suitable for application to a wireless field such as mobile communication.

[0002]

2. Description of the Related Art MMIC mainly applied to mobile communication
While research and development of (Monolithic Microwave Integrated Circuit) has been brisk, a lot of research and development of mixer circuits have been made. There are many types of mixer circuits, but especially in a receiving mixer (down converter), leakage of a local signal to an RF terminal (signal input terminal) can be easily reduced, so a dual gate FET (field effect transistor) is used.
A mixer using is often used. Dual gate FE
As an example of a mixer using T, as shown in Technical Report of IEICE, A-P93-155, MW, published in February 1994.
93-158, RCS 93-109, etc., and there are many other application examples.

FIG. 3 shows an explanatory diagram of the operating principle of a mixer using a dual gate FET. Here, the depletion type GaAs MESFET (using gallium arsenide, metal insulator type field effect transistor) is increasingly used for mobile communication.
Shall be used. An equivalent circuit of the dual gate FET can be shown by cascode connection of the FET as shown in FIG. The source of the lower FET1 is S,
The gate of the FET1 is G1, the gate of the upper FET2 is G
2, D the drain of FET1 (source of the upper FET)
1, the drain of FET2 is shown as D2.

Now consider the case of a receive mixer. An RF (high frequency) signal is applied to G1 as an input. The local (local oscillation) signal is applied to the gate G2. Usually, the local signal is given a large enough amplitude to reach saturation.
Therefore, the local input waveform can be considered as a square wave as shown in FIG. The product of the RF signal and the local signal is output from the drain D2. An IF (intermediate frequency) signal having a frequency difference between the RF frequency and the local frequency is output by the output matching circuit having the low-pass characteristic.

The operation of each FET is shown below. FET1, FET
The second gate is biased to Vg1 and Vg2, respectively. The local signal applied to the FET2 is shown in FIG.
As shown in, the AC component is superimposed around Vg2. When the local signal becomes below the pinch-off voltage of FET2, F
ET2 is turned off. When the local signal can be approximated by a square wave, it can be considered that the FET2 operates in two states of on and off. The operation of the FET1 in this state is shown in FIG.
Shown in When the RF signal is weak, the operating point is determined by the bias Vg1 applied to the gate of the FET1. Therefore FE
The operating state of T1 is D when the gate bias is Vg1 and the drain bias is Vdon (Vg2 is in the ON state).
1 potential) and the drain bias is 0 V (V
It can be regarded as two states, i.e., the potential of D1 when g2 is in the off state.

These two states are summarized in FIGS. 4 (a) and 4 (b). The ON state operates as a voltage-current converter having a transconductance gm1 determined by the drain bias current Idon. Here, the relationship between gm1 and Idon is expressed by Equation 1
Given in.

[0007]

## EQU00001 ## gm1 = SQRT (4 * beta * Idon) (Equation 1) Here, beta is a coefficient indicating the driving ability of the FET and is mainly determined by the gate length, gate width, channel ion concentration, and the like. SQRT indicates a square root. In the off state, the FET2 is turned off, and the mutual conductance of the FET1 becomes 0, so that the input / output is blocked.

Now, the transconductance gmMIX which receives the RF frequency voltage signal vg1 (fRF) of the mixer circuit shown in FIG. 4 as an input and outputs the IF frequency current signal id (fIF) is given by the equation 2.

[0009]

[Mathematical formula-see original document] gmMIX = gm1 / circumferential ratio (Equation 2) From Equations 1 and 2, the gain of the mixer is increased by increasing Idon.
You can see that it will increase.

In the above-mentioned example of the mixer using the conventional dual gate FET, Vg1 = Vg2 is set in order to simplify the self-bias. FIG. 2 shows an example of a circuit adopting this conventional bias method. By providing a self-biasing resistor R1 between the source and the ground terminal, an appropriate bias can be applied without applying a negative bias to the gate of the depletion type FET. The two gates G1 and G2 are grounded via resistors R3 and R4. When the potential of the source electrode is Vs, G1,
A bias of -Vs is applied to G2.

Consider increasing the conversion gain in this conventional circuit example. To make the conversion gain higher than in equations 1 and 2, I
Don needs to be increased. Since Idon is limited by Vg1, the self-bias resistor R1
The conversion gain can be increased by decreasing Vg1 and decreasing Vg1 to increase Idon.

[0012]

In the conventional circuit, in order to improve the conversion gain, the resistance value for self-bias is lowered and the DC bias current must be increased.

An object of the present invention is to reduce power consumption.
The purpose is to improve the conversion gain without increasing the DC bias current.

[0014]

In order to solve the above problems, in the present invention, the relationship between the DC biases Vg1 and Vg2 applied to the respective gates G1 and G2 of the dual gate FET is Vg1> Vg2, and the gate G1 is a gate. By biasing shallower than G2, conversion gain is improved without increasing the DC bias current.

[0015]

The function of the present invention will be described again with reference to FIG. When Vg1> Vg2 and the DC bias current is the same as that of the conventional type, the following two points are different from the conventional bias method. (1) Since Vg1 becomes shallower than in the conventional case, Idon becomes large. (2) Since Vg2 becomes deeper than before, the same V as before
A larger local signal is needed to implement don.

With respect to (1), an increase in conversion gain can be achieved by increasing Idon, which is in accordance with the gist of the present invention. Regarding (2), as shown in FIG. 3 (c), when the ON state is deep in the saturation region, almost the same Idon can be realized even if Vdon becomes low in the saturation region. The conversion gain can be increased with a local signal.

The above is summarized in FIG. The solid thin line is FET1
Vd1 and Id characteristics of Vg1
Is. The dotted line shows the Vd1 and Id characteristics of FET2, and the parameter is Vg2. If the RF signal is sufficiently smaller than the local signal, the fluctuation of the operating point due to the RF signal can be ignored. In such a case, the operation of the mixer is V
In the d1-Id plane, it moves along a curve satisfying Vg1 = constant value. The maximum voltage value of the local signal
If Vg2max is set, Vg2 = Vg2max is the limit of mixer operation.

The operation of the mixer at the conventional operating point and the operation of the mixer at the operating point of the present invention are shown in solid lines in FIG. White circles indicate respective DC operating points. Both were set to the same DC bias current. The bias value for the gate G1 in the conventional bias method is Vg11, and the bias value for the gate G1 in the bias method of the present invention is Vg12. The operation by the conventional bias method is Vd1 = 0 when the local signal level is the lowest, and drain current Ido when the local signal level is the highest Vg2 = Vg2max1.
n1 flows. The operation according to the bias method of the present invention is Vd1 = 0 when the local signal level is the lowest, and drain current Idon when the local signal level is the highest Vg2 = Vg2max2.
2 flows.

As described above, according to the present invention, Idon can be increased and the conversion gain can be improved. However, as the bias of Vg2 becomes deeper, Vg2max also becomes lower, and eventually,
Since FET1 cannot operate in saturation and the conversion gain decreases, it is necessary to find an appropriate bias condition.

FIG. 6 shows measured values of the conversion gain when the bias conditions are changed. Device has pinch-off voltage Vp
= -1.0 V GaAs MESFET is used, the input RF frequency is 1.9 GHz and the output IF frequency is 90 MHz. The horizontal axis represents Vg2, and the vertical axis represents the conversion gain Gc (dB). Vg1 was adjusted so that the DC bias current was 3.3 mA. Vg1 = Vg2 is about -0.52V
It is time for It can be seen that the conversion gain is improved by increasing Vg2. The gain improvement is observed even when the local signal level is changed from 0 dBm to -3 dBm. −
At 6 dBm, there is almost no improvement effect, and -9 dBm
On the contrary, it deteriorates. This is because the FET 1 cannot operate in saturation even when the local signal is Vg2max. It is realistic to change the local signal level from 0 dBm to -3 dBm, and the effectiveness of the present invention is confirmed.

FIG. 7 shows measured values of the output third-order intercept point under the same conditions as in FIG. The improvement effect can be confirmed at a local signal level of 0 dBm to -6 dBm.

As described above, the effectiveness of the present invention can be easily shown by experiments.

[0023]

EXAMPLE A first example of the present invention will be described with reference to FIG.
The basis of the present invention is, in a cascode circuit including a dual-gate FET, a mixer circuit for adding an input signal to the gate terminal of the lower FET, adding a local signal to the gate terminal of the upper FET, and extracting an output signal from the drain terminal. In, the gate bias of the upper FET is set to the lower FET
By biasing the gate bias to a potential substantially lower than the gate bias, the conversion gain, the output third-order intercept point, etc. are increased without increasing the DC bias current. The effect can be easily shown by experiments as described above. This embodiment can easily improve the characteristics of the frequency converter for mobile communication.

A second embodiment of the present invention will be described with reference to FIG. In this embodiment, the bias relationship shown in the first embodiment is actually realized on the MMIC. Source bias resistance is R
It is realized by two resistors 1 and R2, and a bias is supplied to the gate G1 from the middle point of the resistor through the resistor R3. Gate G
A bias is supplied to 2 from the ground terminal via the resistor R4. This makes it possible to realize Vg1> Vg2.

A high impedance inductance may be used in place of the bias supply resistors R3 and R4. Further, the matching inductance of the input matching circuit of FIG. 1 can also be used as an element for supplying bias. When a high conversion gain is required and a high S / N ratio is required, the bypass capacitor C2 is indispensable. This is to prevent thermal noise generated from R1 and R2 from entering the gate G1. This embodiment can facilitate MMIC implementation. Although the dual gate FET is used in FIG. 1, a single set of cascode-connected single FETs is also applicable to this embodiment.

A third embodiment of the present invention will be described with reference to FIG. In this embodiment, R2 of the two self-biasing resistors R1 and R2 of the second embodiment is replaced with a diode. By using the diode, the potential difference between Vg1 and Vg2 can be maintained at a constant value independent of the current.

A fourth embodiment of the present invention will be described with reference to FIG. In this embodiment, of the two self-biasing resistors R1 and R2 of the second embodiment, R1 is replaced with a diode. By using the diode, the potential between the gate G1 and the source can be kept at a constant value independent of the current.

[0028]

According to the present invention, the conversion gain of the mixer, the output third-order intercept point, etc. can be increased without increasing the DC bias current. The effect of improving the conversion gain of 1.5 dB and the third-order intercept point of 5 dB as compared with the conventional mixer was confirmed by experiments.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a conventional mixer circuit diagram.

FIG. 3 is an explanatory diagram of a mixer operation according to an embodiment of the present invention.

FIG. 4 is a mixer equivalent circuit diagram.

FIG. 5 is an explanatory diagram of a comparison of operations of the present invention and a conventional circuit.

FIG. 6 is an explanatory diagram of the effect of the present invention on the conversion gain.

FIG. 7 is an explanatory diagram of the effect of the present invention on the third-order intercept point.

FIG. 8 is a circuit diagram of an embodiment of the present invention.

FIG. 9 is a circuit diagram of an embodiment of the present invention.

[Explanation of symbols]

R1, R2, R3, R4 ... Resistance, C1, C2 ... Capacitance, V
dd ... Power supply voltage, G1 ... FET in lower stage of cascode circuit
, G2 ... The gate terminal of the upper FET of the cascode circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsutoshi Sugano 1-280, Higashi Koigokubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (5)

[Claims] 1. A mixer circuit for applying an input signal to the gate terminal of a lower FET of a cascode circuit, adding a local signal to the gate terminal of an upper FET of the cascode circuit, and extracting an output signal from a drain terminal of the cascode circuit. Is biased to a potential substantially lower than the gate bias of the lower FET. 2. The mixer circuit according to claim 1, wherein a dual gate FET is used in the cascode circuit. 3. The F of the lower stage according to claim 1 or 2.
A series connection of a plurality of resistors is connected between the source electrode of the ET and the ground terminal, an impedance element is connected between the intermediate terminal of the series connection of the resistors and the gate terminal of the FET of the lower stage, and the FET of the upper stage is connected. A mixer circuit with an impedance element connected between the gate and ground terminals. 4. The resistor according to claim 3, wherein the resistor closest to the source of the resistors connected in series between the source electrode of the lower FET and the ground terminal is replaced with a diode,
A mixer circuit that connects the source electrode to the anode and the cathode to the resistor. 5. The resistor according to claim 3, wherein a resistor closest to the ground terminal among resistors connected in series of a plurality of resistors between the source electrode of the lower FET and the ground terminal is replaced with a diode, and the resistor is connected to the ground terminal. A mixer circuit that connects the cathode and the anode to the resistor.