JPH08149824A - Parallel operation device of inverter - Google Patents

Abstract

PURPOSE: To enable the output current of inverters in parallel operation to be balanced or load-shared. CONSTITUTION: A parallel operation device of inverters is provided with a phase synchronization instruction device for synchronizing a slave inverter controller 16 to a master inverter controller 17 in terms of frequency and phase, an adder 31 for adding a detection signal for detecting an output current Im of a master inverter 11 and a detection signal for detecting an output current Is of a slave inverter 12, a voltage divider 32 for dividing the added signal by half, and a reference side absolute value circuit 33 for making absolute the voltage-divided signal. Further, the parallel operation device is provided with a feedback-side absolute value circuit 34 for making absolute the output current of the slave inverter and an error amplifier 36 for amplifying the error of the output signal of both absolute value circuits and controlling the slave inverter controller.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel operation device for inverters in which a plurality of inverters stably share currents and operate in parallel.

[0002]

When operating a plurality of inverters in parallel, for example, as shown in Japanese Patent Publication No. 54-12963, the output voltage of each inverter is detected by a voltage detector, and the output current of each inverter is used as a voltage detection signal. Is added, and the current detectors are connected to each other. Then, when imbalance occurs in the output current of the inverter, the signal obtained by adding the current detection signal to the voltage detection signal changes, the error between this signal and the reference value is amplified, each inverter is controlled, and the output current of the inverter is changed. There is no imbalance.

However, since the above-mentioned parallel operation device has a complicated structure, the voltage and frequency are determined by one specific inverter among a plurality of inverters as disclosed in Japanese Patent Publication No. 6-18461. An apparatus has been proposed in which other inverters are operated in parallel so as to follow them.

[0004]

However, it is not clear how to design the load sharing command value in the above-mentioned inverter parallel operation device, and this configuration is complicated.

[0005]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention relates to parallel inverters in which one main inverter and one or more slave inverters are connected in parallel to a load and are operated in parallel. In the operating device, a main inverter controller that controls the main inverter, a slave inverter controller that controls the slave inverter in synchronization with the main inverter controller, a detection signal that detects the output current of the main inverter, and the slave inverter. An adder for adding a detection signal obtained by detecting the output current of the inverter, a voltage divider for dividing the added signal into 1/2, and a reference-side absolute value circuit for converting the signal divided by the voltage divider into absolute values. And an absolute value circuit on the feedback side for converting the detection signal obtained by detecting the output current of the slave inverter into an absolute value, and amplifying the error between the output signals of both absolute value circuits to control the slave inverter. It provided an error amplifier of the slave to enter the error amplifier signal to location.

Further, a detection signal voltage divider for dividing the current detection signal is provided at the input of the adder so that the output of the voltage divider becomes the ratio of the capacity of the slave inverter to the capacity of the main inverter.

Further, the detection signal voltage divider divides the detection signal obtained by detecting the output current of the main inverter and the output current of the slave inverter into the ratio of the capacity of the slave inverter to the capacity of the master inverter, respectively. It is a detection signal voltage divider.

[0008]

The slave inverter controller controlling the slave inverter is synchronized with the master inverter controller controlling the master inverter. Further, the current detection signal detecting the output current of the main inverter and the current detection signal detecting the output current of the slave inverter are added by the adder, and the added addition signal is divided into 1/2 by the voltage divider. . Using the voltage-divided and absolute-valued signal as a reference, the detection signal in which the output current of the slave inverter is detected has the absolute-valued signal as the feedback signal,
The error is amplified by the error amplifier. The slave inverter is controlled by this error-amplified signal. As a result, the sub-inverter follows the main inverter and is operated in parallel. In addition, the sum of the output current of the main inverter and the output current of the slave inverter is the load current, and a signal proportional to 1/2 of the load current is generated in the voltage divider.
Is used as a reference signal, the sub-inverter is feedback-controlled, the output current of the main inverter and the output current of the sub-inverter become the same, and the output currents of both inverters are balanced.

Further, by setting the output of the voltage divider to be the ratio of the capacity of the sub-inverter to the capacity of the main inverter, the sub-inverter is feedback-controlled with this divided signal as a reference signal, and the output current of the main inverter The output current of the inverter is shared according to the capacity of each inverter.

Further, the detection signal detecting the output current of the main inverter and the detection signal detecting the output current of the slave inverter are each divided by the detection signal voltage divider into a ratio of the capacity of the slave inverter to the capacity of the main inverter. To be done. When the divided detection signals are added by the adder and divided by 1/2 by the voltage divider, the divided signal becomes the ratio of the capacity of the slave inverter to the capacity of the main inverter, and this signal is used as a reference. The slave inverter is feedback-controlled as a signal, and the output current of the master inverter and the output current of the slave inverter are shared according to the capacity of each inverter.

[0011]

Embodiment An embodiment of the present invention will be described below with reference to FIGS. Reference numeral 1 denotes a DC power supply device, which may be formed by rectifying a commercial battery or an AC power supply such as an engine generator, as well as a secondary battery such as a storage battery. Reference numeral 3 is a load, 11 is a main inverter, and 12 is a sub-inverter, which operates following the output of the main inverter 11. Reference numerals 16 and 17 denote inverter control devices that perform PWM control of control elements such as transistors, MOSFETs, and IGBTs of the main inverter 11 and the sub-inverter 12, respectively. Reference numerals 21 and 22 denote current detectors that detect the output currents of the main inverter 11 and the slave inverter 12, respectively, and 26 has a voltage setter that sets the output voltage of the main inverter 11 inside. The main error amplifier for amplifying the error of No. 2 is a phase synchronization command device 27 for inputting a signal to follow the frequency and phase of the main inverter 11 to the inverter control device 17 of the sub inverter 12.

Reference numeral 31 is an adder for adding detection signals from both current detectors 21 and 22, 32 is a voltage divider for dividing the voltage into 1/2,
Reference numeral 33 is a reference-side absolute value circuit for full-wave rectifying the divided signal, 34 is a feedback-side absolute value circuit for full-wave rectifying the detection signal of the current detector 22, and 36 is an output of the reference-side absolute value circuit 33. This is a secondary error amplifier that amplifies the error between both signals by using the signal and the feedback side absolute value circuit 34 as the feedback signal. Three
Reference numeral 7 is a low-pass filter for smoothing the error signal, 38 is a correction circuit for correcting the error signal of the main error amplifier 26 and the error signal of the sub error amplifier 36, and inputting the correction signal to the inverter control device 17 of the sub inverter 12. is there.

Now, the output voltage of the main inverter 11 is detected by the voltage detector 25, and this detection signal and the error amplifier 26 are detected.
The error is amplified by comparing with a reference value stored in the controller, the main inverter is controlled through the inverter control device 16, and constant voltage control is performed. In addition, the phase synchronization command device 27 controls the inverter control devices 16 and 17, and the main inverter 11
And the frequency and phase of the slave inverter 12 are synchronized.
Further, the output currents Im and Is of the main inverter 11 and the sub-inverter 12 are detected by the current detectors 21 and 22, respectively, and the detection signals are inputted to the inverter control devices 16 and 17, respectively, and the main inverter 11 and the sub-inverter 12 are respectively inputted. Protects against overcurrent.

The detection signals of the current detectors 21 and 22 are added by the adder 31, the added signal is divided into 1/2 by the voltage divider 32, and the divided signal is absolute by the reference side absolute value circuit 32. It is digitized to obtain an absolute signal e1. Further, a signal e2 obtained by converting the detection signal of the current detector 22 into an absolute value by the feedback side absolute value circuit 32 is obtained. Signal e1
Is used as a reference value, the signal e2 is compared as a feedback signal, the error is amplified by the subordinate error amplifier 36, and the low-pass filter 3
The smoothed signal via 7 and the error amplified signal from the main error amplifier 26 are corrected, and the slave inverter 12 is controlled via the inverter controller 17.

That is, the output current I of the main inverter 11
The sum of m and the output current Is of the sub-inverter 12, that is, 1/2 of the current Io flowing in the load is used as a reference value, and the output current Is of the sub-inverter 12 flows in the load Io.
The slave inverter 12 side is feedback-controlled so that it becomes 1/2 of the above. As a result, the output current Im of the main inverter 11 and the output current Is of the slave inverter 12 become the same current, and the currents are balanced.

FIG. 2 shows an embodiment in which there is one main inverter and two slave inverters, that is, three inverters. That is, the third inverter uses a sub-inverter.
Reference numeral 13 is a sub-inverter, 18 is an inverter control device for controlling the sub-inverter 13, and a command signal for the sub-inverter 13 to synchronize with the frequency phase of the main inverter 11 is input from the phase synchronization command device 27. 23 is a sub-inverter 13
Current detector for detecting the output current of the
An adder for adding the detection signal of 1 and the detection signal of the current detector 23, 52 is a voltage divider for dividing the voltage into 1/2, 53 is a reference side absolute value circuit for full-wave rectifying the divided signal, and 54 is A feedback-side absolute value circuit for full-wave rectifying the detection signal of the current detector 23, a secondary error amplifier 56 for amplifying the error of the outputs of both absolute value circuits, a low pass filter 57, and an error of the main error amplifier 26. This is a correction circuit that corrects the signal and the error signal of the subordinate error amplifier 56 and inputs the correction signal to the inverter control device 18.

According to this, the slave inverter 13 is feedback-controlled so that the error between the output current Im of the main inverter 11 and the output current Is2 of the slave inverter 13 becomes zero, as described above. Therefore, the main inverter 11
Output current Im of the slave inverter 12, the output current Is1 of the slave inverter 12,
The output currents Is2 of the slave inverters 13 are all equal and current balance occurs, and each inverter shares 1/3 of the load current Io.

In the embodiment shown in FIG. 2, the current balance control in the parallel operation of the three inverters has been described.
Even if there are four or more units, operate the inverters in parallel in the same way,
The current can be balanced.

FIG. 3 shows an embodiment in which the load sharing ratio of the main inverter and the slave inverter is changed.
That is, the capacity of the main inverter 11 is, for example, 5 kVA,
The capacity of the sub-inverter 12 is different, for example, 3 kVA, and the load sharing is set to be 5 to 3 according to the capacity of each inverter. The difference from FIG. 1 is that between the current detector 21 and the adder 31, the detection signal voltage divider for dividing the detection signal of the current detector 21 into the ratio of the capacity of the sub-inverter to the capacity of the main inverter, for example, 3/5. 41 is provided, and a detection signal voltage divider 42 is provided between the current detector 22 and the adder 31 to share the detection signal of the current detector 22 with the ratio of the capacity of the sub inverter to the capacity of the main inverter, for example, 3/5. It is a thing.

As a result, when the signals divided by the detection signal voltage dividers 41 and 42 are added by the adder 31 and further divided by the voltage divider 32, the output of the voltage divider 32 is the inverter of the capacity of the main inverter. A capacitance ratio, in the above example, a signal of 3/5 is output, and a value of 3/5 of the reference side absolute value circuit 33 is output.
Inverter 12 is feedback-controlled with the detection signal of current detector 22 as a feedback signal using the signal of
The output current Is of the sub-inverter 12 becomes 3/5 of the output current Im of the main inverter 11, and the current corresponding to the capacity of each inverter is shared.

In the embodiment shown in FIG. 3, the main inverter 11 is used.
However, even if the capacity of the main inverter 11 is smaller than that of the sub-inverter 12, the current can be shared according to the capacity of each inverter. . In this case, the voltage dividers 41 and 42 boost the voltage. Further, in the above embodiment, the voltage divider having the same ratio is provided at the input of the adder, but this can be changed. In this case, the output of the voltage divider 32 may be the ratio of the capacity of the slave inverter to the capacity of the main inverter. Also,
It can also be applied to parallel operation of three or more inverters. In this case, a detection signal voltage divider may be provided at the input of each adder.

[0022]

As described above, according to the present invention, the inverters can be stably operated in parallel with a simple structure, and the output current of the sub-inverter can be shared by the output current of the main inverter according to balance or capacity. . Further, even if there are two inverters, the output commutation can be shared according to the balance or the capacity.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an inverter parallel operation control device of the present invention.

FIG. 2 is a block diagram of another embodiment of the parallel operation control device for inverters of the present invention.

FIG. 3 is a block diagram of another embodiment of the parallel operation control device for inverters of the present invention.

[Explanation of symbols]

 1 DC power supply device 3 load 11 main inverter 12, 13 slave inverter 16, 17, 18 inverter control device 21, 22, 23 current detector 25 voltage detector 26 (main) error amplifier 27 phase synchronization command device 31,51 addition Unit 32,52 Voltage divider 33,53 (reference side) absolute value circuit 34,54 (feedback side) absolute value circuit 36,56 (subordinate) error amplifier 37,57 low-pass filter 38,58 correction circuit 41,42 detection signal Voltage divider

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Makoto Sakurada 2-14-3 Awaji, Higashiyodogawa-ku, Osaka City Osaka Prefecture Sansha Electric Co., Ltd.

Claims (3)

[Claims] 1. A parallel operation device of an inverter, in which one main inverter and one or more sub-inverters are connected in parallel to a load and operated in parallel, the main inverter control device controlling the main inverter, A slave inverter control device that controls the slave inverter in synchronization with the master inverter control device; and an adder that adds a detection signal that detects the output current of the main inverter and a detection signal that detects the output current of the slave inverter. , A voltage divider that divides the added signal into ½, a reference-side absolute value circuit that converts the signal divided by the voltage divider into an absolute value, and a detection signal that detects the output current of the slave inverter as an absolute value. A feedback side absolute value circuit and a sub error amplifier for amplifying the error between the output signals of the both absolute value circuits and inputting the error amplifier signal to the sub inverter control device. Inverter parallel operation device characterized by the above. 2. A detection signal voltage divider that divides a current detection signal at the input of the adder so that the output of the voltage divider is the ratio of the capacity of the slave inverter to the capacity of the main inverter. 1. The parallel operation device of the inverter according to 1. 3. The detection signal voltage divider divides the detection signal of detecting the output current of the main inverter and the detection signal of the output current of the slave inverter into a ratio of the capacity of the slave inverter to the capacity of the main inverter, respectively. The parallel operation device of the inverter according to claim 2 which is a detection signal voltage divider.