JPH08149525A - Optical switch drive circuit - Google Patents

Abstract

PURPOSE: To provide an optical switch drive circuit of the configuration to suppress dispersion in a switching speed for plural optical MOS FETs and drive elements and to avoid useless power consumption. CONSTITUTION: Light emitting diodes 6a, 7a turning on/off optical MOS FETs 6, 7 are connected in series and input output terminals of the light emitting diode 6a receiving a power supply (+V) are connected in parallel with a P channel MOS FET1 and an input terminal of the other light emitting diode 7a is connected to an input terminal of an N channel MOS FET 2 and its output terminal is connected to an input terminal of the N channel MOS FET 3 via each of current limit resistors 4, 5 respectively and output terminals of the N channel MOS FETs 2, 3 are connected to ground level points. Furthermore, logic circuits 8-9 to realize a 2-bit signal logic are provided to gate terminals of the MOS FETs 1-3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for an optical switching element used in a reversing switch circuit or the like, and more particularly to an optical switch drive circuit using an optical MOS type FET as an optical switching element.

[0002]

2. Description of the Related Art When connecting an intra-office line terminating device and a subscriber line in a data transmission system, the polarity of a signal sent to the subscriber line or the polarity of a power supply voltage when supplying power to a subscriber side device is controlled. A reversing switch circuit is used as a switching means. FIG. 3 is a diagram for explaining the application of the reversing switch circuit. When the terminal 31 which is the subscriber side device is connected to the intra-office line terminating device 33 by using the metallic subscriber line 32, the subscriber line 32 is connected to the subscriber line 32. It is shown that the polarity of the signal to be sent or the polarity of the power supply voltage from the power supply circuit 34 when supplying power to the intra-station line termination device on the subscriber line 32 side is switched by the reversing switch circuit 30.
In the illustrated example, the switches S1 and S2 are turned on and the switches S3 and S4 are used when the positive polarity power is supplied, and the switches S1 and S2 are turned off and the switches S3 and S4 are used when the reverse polarity power is supplied. The switches S1 to S4 may be individually controlled to be turned on / off in a line test or the like.

Although such a reversing switch circuit 30 can be realized by a relay circuit, the use of an optical MOS type FET is more preferable because the size of the driving circuit can be simplified and the switching operation can be speeded up. As a conventional technique in which a switch circuit and its drive circuit are configured by using an optical switching element or the like, for example, Japanese Patent Laid-Open No. 63-210889 discloses a "light emitting diode drive circuit". In this technology, a photocoupler is used as an optical switching element. However, both the photocoupler and the optical MOS FET are common in that the light emitting diode is energized and the semiconductor element is turned on / off. Optical MOS
The outline of this prior art will be described by replacing it with a FET.

FIG. 2 is a block diagram of the above-mentioned light emitting diode drive circuit, for example, two optical MOS type FETs 24 and 25.
In this example, the light emitting diodes 24a and 25a included in the above are connected in series, and the switches Sa and Sb are connected in parallel with the light emitting diodes 24a and 25a. In this figure, the switches Sa and Sb are the respective light emitting diodes 24.
It turns on when a current flows in a and 25a, and turns off when a current does not flow. The current to each of the light emitting diodes 24a and 25a is an N-channel MOS type FET connected in parallel with it.
Control is performed on the basis of binary level input signals Ia and Ib externally applied to 21 and 22. The N-channel MOS type FETs 21 and 22 are turned on when the logic levels of the input signals Ia and Ib given to their gate terminals are "high" to bypass the current, so that no current flows through the light emitting diode and the switches Sa, Turn off Sb.

[0005]

In the above-mentioned light emitting diode drive circuit, when controlling a plurality of optical switching elements, the current value for control increases as a whole when a current is passed in parallel to each light emitting diode. In view of the above, a light-emitting diode is connected in series, and a current bypass switching element is connected in parallel to the light-emitting diode to control whether or not to pass a current to each light-emitting diode. Although there is an advantage that the current value is reduced, the following problems remain.

(A) For example, in the example of FIG. 2, there are four combinations of ON / OFF of Sa and Sb with respect to the combination of 2 bits of the input signal, but in any case, there is a current from the power supply to the ground (ground line). Power consumption becomes a problem because the power consumption continues to flow. (B) When the number of light emitting diodes connected in series increases due to the voltage (forward voltage Vf) between the anode and the cathode generated by the current flowing through the light emitting diodes 24a and 25a, the current value for control becomes small and the individual light sources. There is a difference in switching speed between the MOS FETs 24 and 25. This speed difference is due to N-channel MOS type FET2
It is also caused by the difference in potential applied between the gate and the source of 1 and 22 for each element. By the way, in the example of FIG.
The source voltage of the N-channel MOS type FET 21 is the ground potential when the other N-channel MOS type FET 22 is on, but is + Vf when it is off.

The present invention has been made in view of the above problems of the prior art.
An object of the present invention is to provide an optical switch drive circuit configured to suppress wasteful power consumption and variations in switching speed of a plurality of optical MOS FETs and drive elements.

[0008]

An optical switch driving circuit of the present invention which achieves the above object is a pair of optical switching elements which are turned on when a light emitting diode provided therein is turned on and turned off when not turned on, for example, an optical MOS FET. And a first and second N-channel semiconductor element that conducts or blocks the input / output terminal based on a binary signal applied to the gate terminal. , The respective light emitting diodes are connected in series, the input / output terminal of one of the light emitting diodes to which the power is led is connected in parallel to the input / output terminal of the P-channel semiconductor element, and the input terminal of the other light emitting diode is connected to the first N The input terminal of the channel semiconductor element and the output terminal of the other light-emitting diode are connected to the input terminal of the second N-channel semiconductor element through current limiting resistors, respectively. And, and, in which the output terminals of the N-channel semiconductor element and a ground potential. The resistance value of the current limiting resistor is preferably a value that equalizes the current values when only one of the light emitting diodes is energized.

Further, a binary signal inputted from the first signal input terminal is logically inverted and led to the gate terminal of the P-channel semiconductor element, and a binary signal inputted from the second signal input terminal. A second inverter that logically inverts a value signal to lead to a gate terminal of a second N-channel semiconductor element, and a logical sum output of the first inverter output and the second inverter input is the first N-channel. And a logical sum circuit leading to the gate terminal of the semiconductor element.

[0010]

In the optical switch driving circuit of the present invention, the binary signal input from the first signal input terminal is logically inverted by the first inverter and guided to the gate terminal of the P-channel semiconductor element to input the second signal. The binary signal input from the terminal
The inverter is logically inverted and led to the gate terminal of the second N-channel semiconductor element, and the logical sum output of the first inverter output and the second inverter input is led to the gate terminal of the first N-channel semiconductor element. Therefore, even if three semiconductor elements having different types of channels are provided, the logic based on the two binary signals can be easily realized.

Further, the input / output terminal of the P-channel semiconductor element and the input / output terminal of the light-emitting diode to which the power source is led are connected in parallel, and a current limiting resistor is connected to the input terminals of the first and second N-channel semiconductor elements. , If each output terminal is connected to a grounding wire individually, each semiconductor element has only one terminal, which reduces the total number of terminals and the current value when all the optical switching elements are turned off. Is zero, and wasteful power consumption is suppressed. When the power supply level to the first and second inverters and the OR circuit and the power supply level to each light emitting diode have a common value, the voltage applied between the gate terminal and the input / output terminal of the semiconductor element of each channel is common. Therefore, there is no variation in the switching speed, and by properly selecting the resistance value of the current limiting resistor, there is no variation in the operating speed of each optical switching element.

[0012]

Next, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 shows an optical MOS according to an embodiment of the present invention.
FIG. 3 is a configuration diagram of a switch drive circuit, showing an example in which two optical MOS type FETs are used as optical switching elements, and one P-channel MOS type FET and two N-channel MOS type FETs are used as driving semiconductor elements.

Referring to FIG. 1, each optical MOS type FET
First and second light emitting diodes 6a, 7 included in 6, 7
a is connected in series, and the source of the light emitting diode 7a is
N-channel MOS type FET through the current limiting resistor 5
3 is connected to the drain terminal. On the other hand, the cathode of the light emitting diode 6a is connected to the N via the current limiting resistor 4.
It is connected to the drain terminal of the channel MOS type FET 2 and the drain terminal of the P channel MOS type FET 1.

The N-channel MOS type FETs 2 and 3 turn on when a logic level "high" is applied to their gate terminals, and the P-channel MOS type FET 1 has a logic level "low" added to their gate terminals. Sometimes it turns on. The inverters 8 and 9 and the AND circuit 10 set the logic for performing on / off control of each of the MOS FETs 1 to 3 according to the combination of the binary level input signals IA and IB. Table 1 shows a combination of input signals IA and IB (signals a, b, and c of each part) and a switch SA based on the combination.
The relationship of on / off operation of SB is shown.

[0015]

[Table 1]

Here, in order to compare the power consumption of the circuit configuration of this embodiment with that of the conventional circuit configuration shown in FIG. 2, the power supply level is + V = + 5V, and the forward voltage V of the light emitting diode is V.
f = 1.0V, resistance value of current limiting resistor 4 = 670
Ω, the resistance value of the same resistor 5 = 500Ω, and the resistance value of the same resistor 23 of the conventional configuration = 500Ω, the total current value of the circuit for each state of the input signal was measured. Among the measurement results, Table 2 shows the case of the present embodiment, and Table 3 shows the case of the conventional configuration.

[0017]

[Table 2]

[0018]

[Table 3]

Comparing Tables 2 and 3, it is 10 [mA] when the switches Sa and Sb are both off in the conventional configuration, whereas in the case of this embodiment, the switches SA and SB are both off. Has no current in the circuit. Therefore, when the switches SA and SB are both used in the off state for a long time, the advantage of this embodiment becomes more remarkable.

Further, in this embodiment, as an example, the power supply level + V = + 5V and the power supply voltage of the inverters 8, 9 and the AND circuit 10 are also + 5V.
The voltage applied between the gate and the source of ~ 3 has almost the same value. On the other hand, in the case of the configuration shown in FIG.
The gate-source voltage of ET21 is MOS type FET2.
2, depending on the on / off state. Therefore, it can be seen that variations in switching operation are suppressed.

Another advantage of this embodiment is that each M
As the source potential of the OS type FETs 1 to 3, the P-channel one can be the power supply voltage and the N-channel one can be the ground, so that a special terminal for the source terminal is not required, and the driving circuit can be integrated into an LSI. It will be a great advantage.

In the case where the optical switch drive circuit of this embodiment is used to form the reversing switch circuit as shown in FIG. 3, for example, the first and second inverters 8 and 9 (see FIG. 1) are used. By branching each input and further inserting an inverter, four logical combinations can be easily realized.

Although the present embodiment is as described above, the present invention is not necessarily limited to the driving element and switching element of the MOS type FET, and can be applied to other kinds of semiconductor elements or optical switching elements in general. It is a thing. Further, in the present embodiment, the driving procedure of the two sets of switches has been described for the sake of convenience, but it goes without saying that the present invention is not limited to this numerical value.

[0024]

As is apparent from the above description, according to the optical switch drive circuit of the present invention, when all the optical switching elements are turned off, the current value for control becomes zero, resulting in unnecessary power consumption. Has the effect of being suppressed.

Further, the binary signal input from the first signal input terminal is logically inverted by the first inverter and led to the gate terminal of the P-channel semiconductor element, and the binary signal input from the second signal input terminal. The signal is logically inverted by the second inverter and guided to the gate terminal of the second N-channel semiconductor element, and the logical sum output of the first inverter output and the second inverter input is output to the gate of the first N-channel semiconductor element. Since it is led to the terminal, there is an effect that two logics based on two binary signals can be easily realized even if three kinds of semiconductor elements are provided. In that case, the first and second inverters and the logics are provided. Since the power supply level to the summing circuit and the power supply level to each light emitting diode are set to a common value, the voltage applied between the gate terminal and the input / output terminal of the semiconductor element of each channel becomes common, and the switching speed is increased. There is a variation there is no effect on.

This makes it possible to easily realize a reversing switch circuit with low power consumption, high reliability, and high switching speed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an optical MOS switch drive circuit showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of a light emitting diode drive circuit according to a conventional technique.

FIG. 3 is a diagram showing a configuration example of a reversing switch circuit to which the present invention is applied.

[Explanation of symbols]

1A, 1B, 1a, 1b Binary level input signal 1 P-channel MOS type FET 2, 3, 21, 22 N-channel MOS type FET 6, 7, 24, 25 Optical MOS type FET (optical switching element) 6a, 7a , 24a, 25a Light emitting diode 4, 5, 23 Current limiting resistor 30 Inversion switch circuit

Claims (5)

[Claims] 1. A circuit for driving a pair of optical switching elements, each of which is turned on when a light emitting diode included therein is turned on when the light emitting diode is energized and is turned off when the light emitting diode is not turned on, the input / output being based on a binary signal applied to each gate terminal. It comprises a P-channel semiconductor element that conducts or cuts off the terminals and a first and a second N-channel semiconductor element. Each light emitting diode is connected in series, and the input / output terminal of one of the light emitting diodes to which the power source is guided is connected. The input terminal of the other light emitting diode is connected in parallel to the input / output terminal of the P-channel semiconductor element, the input terminal of the other N-channel semiconductor element is connected to the input terminal of the other light-emitting diode, and the output terminal of the other light-emitting diode is connected to the second N
An optical switch drive circuit, characterized in that the input terminals of the channel semiconductor elements are respectively connected through current limiting resistors, and the output terminals of each N-channel semiconductor element are at ground potential. 2. The resistance value of the current limiting resistor is a value that makes the current value the same when only one of the light emitting diodes is energized.
The optical switch drive circuit described. 3. The optical switch drive circuit according to claim 1, wherein the binary signal input from the first signal input terminal is logically inverted and then led to the gate terminal of the P-channel semiconductor element.
Inverter, a second inverter that logically inverts the binary signal input from the second signal input terminal and guides it to the gate terminal of the second N-channel semiconductor element, the first inverter output, and the second inverter. And an inverter input to the gate terminal of the first N-channel semiconductor element. 4. The optical switch drive according to claim 3, wherein the power supply level supplied to the first and second inverters and the OR circuit has a common value with the power supply level supplied to the light emitting diode. circuit. 5. The optical switching element is an optical MOS (me
FET (field effect) of the tal oxide semiconductor type
5. The optical switch drive circuit according to claim 1, wherein the P-channel and N-channel semiconductor elements are MOS type corresponding channel FETs, respectively.