JPH08149363A - Shake reduction device, optical device and camera - Google Patents

Shake reduction device, optical device and camera

Info

Publication number
JPH08149363A
JPH08149363A JP30956094A JP30956094A JPH08149363A JP H08149363 A JPH08149363 A JP H08149363A JP 30956094 A JP30956094 A JP 30956094A JP 30956094 A JP30956094 A JP 30956094A JP H08149363 A JPH08149363 A JP H08149363A
Authority
JP
Japan
Prior art keywords
resistor
output
operational amplifier
reduction device
conversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30956094A
Other languages
Japanese (ja)
Inventor
Akihiro Fujiwara
昭広 藤原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP30956094A priority Critical patent/JPH08149363A/en
Priority to US08/558,527 priority patent/US5805212A/en
Publication of JPH08149363A publication Critical patent/JPH08149363A/en
Pending legal-status Critical Current

Links

Landscapes

  • Mounting And Adjusting Of Optical Elements (AREA)
  • Adjustment Of Camera Lenses (AREA)

Abstract

PURPOSE: To reduce the initializing time and to eliminate the need for the adjustment or a correction means to correct a DC offset by eliminating the need for a capacitor for cutting off a DC component in the shake reduction device for a device operated while a person holds the device by hand so as to attain advantages of cost and mount capacity. CONSTITUTION: The device is provided with a detection means 11 that detects a state of the device and provides an output of the detection state as an analog signal, an amplifier 12 amplifying an output of the detection means 11 by a prescribed gain, an A/D converter means 13 converting an output of the amplifier means 12 into a digital signal, a signal processing means 13 changing 1st and 2nd values in response to an output of the A/D converter means 13, and a correction means 17 operated depending on the 1st value of the signal processing means 151 and also with a D/A converter means 14 converting the 2nd digital value into an analog signal and limiting the operating point of the amplifier means 12 by using the analog signal.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、人間が手で保持した状
態で操作する装置、例えばスチルカメラ、ムービーカメ
ラなどの撮影装置やスコープなどの観察装置、ブレゼン
テーション等に用いられるレーザさし棒や懐中電灯など
の照明装置等のブレ緩和装置、光学装置およびカメラに
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus operated by a human being while holding it by hand, for example, a photographing apparatus such as a still camera or a movie camera, an observation apparatus such as a scope, and a laser rod used for a presentation. The present invention relates to a blur reduction device such as a lighting device such as a flashlight or a flashlight, an optical device, and a camera.

【0002】[0002]

【従来の技術】図5は例えば、ビデオムービーカメラに
応用した従来のブレ緩和装置を示す構成図である。図5
において、11は光学装置およびカメラ等の手持ち操作
装置(図示せず)の状態を検知する検知手段であり、例
えばジャイロを用いて装置の挙動の角速度を検出してい
る。このジャイロの出力である角速度信号はまずコンデ
ンサC21と抵抗R21で構成される低域カットフィル
タによって直流成分がカットされ、アンプ(演算増幅
器)12の正入力に加えられ、(抵抗R22と同R23
で設定される)所定の利得で増幅される。
2. Description of the Related Art FIG. 5 is a block diagram showing a conventional blur reduction device applied to a video movie camera, for example. Figure 5
In the figure, 11 is a detection means for detecting the state of a hand-held operating device (not shown) such as an optical device and a camera, for example, using a gyro to detect the angular velocity of the behavior of the device. The DC signal component of the angular velocity signal, which is the output of the gyro, is first cut by the low-pass cut filter composed of the capacitor C21 and the resistor R21, and is added to the positive input of the amplifier (operational amplifier) 12 (the resistor R22 and the resistor R23.
It is amplified with a predetermined gain (set by).

【0003】増幅されたジャイロの出力は、A/D変換
回路13によってデジタル値に変換され、以後デジタル
処理される。
The amplified output of the gyro is converted into a digital value by the A / D conversion circuit 13 and thereafter digitally processed.

【0004】まず、A/D変換回路13の出力は可変カ
ットオフ周波数の低域カットフィルタ手段21を介して
次段の積分回路22に加えられる。この積分回路22で
は制限された角速度信号が角度信号に変換される。そし
て、積分回路22の出力の一方は、シーケンス処理手段
23によって、その振幅が評価され、低域カットフィル
タ手段21のカットオフ周波数を適切にコントロールす
る。また、積分回路22の出力の他方は、インターフェ
イス24を介して画像切り出し制御回路25に伝達さ
れ、撮影画像の切り出し位置が決定され、ブレ緩和がな
される。また、上記シーケンス処理手段23は、電源投
入時等での初期化処理に於いて、アナログスイッチSW
2を閉じて、コンデンサC21の電荷を定常状態に設定
する処理を行う。
First, the output of the A / D conversion circuit 13 is added to the integration circuit 22 of the next stage via the low-pass cut filter means 21 having a variable cutoff frequency. The integrating circuit 22 converts the limited angular velocity signal into an angle signal. The amplitude of one of the outputs of the integration circuit 22 is evaluated by the sequence processing means 23, and the cutoff frequency of the low-pass cut filter means 21 is appropriately controlled. The other output of the integration circuit 22 is transmitted to the image cutout control circuit 25 through the interface 24, the cutout position of the captured image is determined, and the blurring is reduced. Further, the sequence processing means 23 uses the analog switch SW in the initialization processing such as when the power is turned on.
2 is closed and a process of setting the electric charge of the capacitor C21 to a steady state is performed.

【0005】図6は他の従来装置を示す構成図であり、
ムービーカメラに応用されるブレ緩和装置である。
FIG. 6 is a block diagram showing another conventional apparatus,
This is a blur reduction device applied to movie cameras.

【0006】図6において、オペアンプ12と抵抗R3
1、R32は反転増幅回路51を構成する。また、オペ
アンプ30と抵抗R33とコンデンサC31は積分回路
52を構成し、上記の反転増幅回路51の出力の平均D
C電圧を基準電圧(図ではグランド)にオペアンプ12
と同30によるフィールドバック回路で安定化する働き
がある。装置の挙動の角速度を検出したジャイロの出力
である角速度信号はアンプ12において、(抵抗R31
と同R32で設定される)所定の利得で増幅される。
In FIG. 6, an operational amplifier 12 and a resistor R3 are provided.
1, R32 form an inverting amplifier circuit 51. Further, the operational amplifier 30, the resistor R33, and the capacitor C31 form an integrating circuit 52, and the average D of the outputs of the above inverting amplifier circuit 51.
Operational amplifier 12 with C voltage as reference voltage (ground in the figure)
And the field back circuit by 30 has the function of stabilizing. The angular velocity signal, which is the output of the gyro that detects the angular velocity of the behavior of the device, is output from the amplifier 12 (resistor R31
(Set by the same R32) is amplified with a predetermined gain.

【0007】積分回路31ではアンプ12を介して入力
された角速度信号が角度信号に変換される。この積分回
路31の出力は補正手段17の入力になっているととも
に絶対値回路32−1と関数回路32−2によって構成
される制限回路32にも加えられ、その制限回路32の
特性を制御する。
In the integrating circuit 31, the angular velocity signal input via the amplifier 12 is converted into an angle signal. The output of the integrating circuit 31 is input to the correcting means 17 and is also added to the limiting circuit 32 constituted by the absolute value circuit 32-1 and the function circuit 32-2, and the characteristic of the limiting circuit 32 is controlled. .

【0008】制限回路32の出力を受けてアナログスイ
ッチSW3がオン状態になると、抵抗R34、R35と
コンデンサC32の効果はなく、一次のHPFの特性に
なる。一方、アナログスイッチSW3がオフ状態になる
と、抵抗R34、R35とコンデンサC32の効果が加
わり、パンニングに対しても飽和しにくい特性になる。
そこで、アナログスイッチSW3のスイッチングを制限
回路32の出力であるデューティーが連続的に変化する
矩形信号で駆動することによって、周波数特性を連続的
に変化させることが出来る。
When the analog switch SW3 is turned on in response to the output of the limiting circuit 32, the resistors R34 and R35 and the capacitor C32 have no effect and the characteristic of the primary HPF is obtained. On the other hand, when the analog switch SW3 is turned off, the effects of the resistors R34 and R35 and the capacitor C32 are added, and the characteristics are less likely to be saturated even with panning.
Therefore, the frequency characteristic can be continuously changed by driving the switching of the analog switch SW3 with the rectangular signal whose duty is continuously changed, which is the output of the limiting circuit 32.

【0009】なお、補正手段17内の差分回路17a、
駆動回路17b、可変頂角プリズム17cの動作につい
ての説明は省略する。
The difference circuit 17a in the correction means 17 is
Descriptions of operations of the drive circuit 17b and the variable apex angle prism 17c are omitted.

【0010】[0010]

【発明が解決しようとしている課題】従来のブレ緩和装
置は以上のように構成されているので、多少の差こそあ
れ、直流成分カット等のために大容量のコンデンサを用
いる必要があり、コスト上や実装容積上で不利な点とな
っていた。また、電気的特性上では、無視出来ないコン
デンサのリーク電流のために、これを補正する何らかの
補正手段やフィルタ手段が必要になるという問題点があ
った。
Since the conventional vibration reduction device is constructed as described above, it is necessary to use a large capacity capacitor for the purpose of cutting the DC component, etc., although there are some differences, which is costly. It was also a disadvantage in terms of mounting volume. Further, in terms of electrical characteristics, there is a problem that some kind of correction means or filter means for correcting the leakage current of the capacitor, which cannot be ignored, is required.

【0011】出願に係る第1乃至8の発明の目的は、上
記のような従来の問題点を解消することを課題になされ
たもので、コンデンサを不要としたブレ緩和装置を得る
ことを目的とする。
An object of the first to eighth inventions of the application is to solve the above-mentioned conventional problems, and an object thereof is to obtain an image stabilization device which does not require a capacitor. To do.

【0012】本出願に係る第2の発明の目的は、上記請
求項1のブレ緩和装置を備えた光学装置を得ることを目
的とする。
A second object of the present invention is to obtain an optical device equipped with the shake reduction device of the first aspect.

【0013】本出願に係る第3の発明の目的は、上記請
求項1のブレ緩和装置を備えたカメラを得ることを目的
とする。
A third object of the present invention is to obtain a camera provided with the shake reduction device of the above-mentioned claim 1.

【0014】[0014]

【課題を解決するための手段】上記の目的を達成するた
めに、本出願に係る第1の発明は、装置の状態を検知
し、検知状態をアナログ信号として出力する検知手段
と、前記検知手段の出力を所定の利得で増幅する増幅手
段と、前記増幅手段の出力をデジタル信号に変換するA
/D変換手段と、前記A/D変換手段の出力に応じて第
1と第2の値が変化する信号処理手段と、前記信号処理
手段の第1の値に応じて動作する手段とを有する装置に
おいて、デジタル信号である前記第2の値をアナログ信
号に変換し、変換後のアナログ信号によって前記増幅手
段の動作点を制御するためのD/A変換手段を具備した
ことにより、アナログ部にコンデンサを持たず、最小規
模のデジタル処理で、更に性能の安定した低コストのブ
レ緩和装置を実現させるものである。
In order to achieve the above object, a first aspect of the present invention relates to a detecting means for detecting the state of a device and outputting the detected state as an analog signal, and the detecting means. Means for amplifying the output of the amplifier with a predetermined gain, and A for converting the output of the amplifier means into a digital signal.
It has an A / D conversion means, a signal processing means whose first and second values change according to the output of the A / D conversion means, and a means which operates according to the first value of the signal processing means. In the device, since the second value, which is a digital signal, is converted into an analog signal, and the D / A conversion means for controlling the operating point of the amplification means according to the converted analog signal is provided, the analog section is provided. This is to realize a low-cost shake reduction device with stable performance and minimum digital processing without a capacitor.

【0015】また、検知手段の出力を直流結合の増幅回
路で増幅し、この増幅回路の出力信号が基準電位を中心
に振幅するように、この出力信号に応じて直流結合増幅
回路の動作点をフィードバック制御する系を有し、この
増幅回路の出力から制御入力までの間をA/D変換とD
/A変換を含むデジタル処理系で行なうように構成した
ことにより、大容量コンデンサを排除することを可能と
したものである。
Further, the output of the detection means is amplified by a DC-coupling amplifier circuit, and the operating point of the DC-coupling amplifier circuit is set in accordance with the output signal so that the output signal of the amplifier circuit has an amplitude around a reference potential. It has a system for feedback control, and A / D conversion and D
Since the digital processing system including the A / A conversion is used, the large-capacity capacitor can be eliminated.

【0016】本出願に係る第2の発明は、上記第1の発
明の作用効果を有するブレ緩和装置を備えた光学装置を
得ることである。
A second invention relating to the present application is to obtain an optical device equipped with a shake reduction device having the operation and effect of the first invention.

【0017】本出願に係る第3の発明は、上記第1の発
明の作用効果を有するブレ緩和装置緒備えたカメラを得
ることである。
A third invention according to the present application is to obtain a camera equipped with a shake reduction device having the operation and effect of the first invention.

【0018】[0018]

【実施例】【Example】

第1の実施例 図1は本発明の特徴を最もよく表わすブレ緩和装置の構
成図であり、同図において、不図示の光学装置およびカ
メラ等の手持ち操作装置の挙動の角速度を検知する検知
手段としてのジャイロ11の出力である角速度信号は、
アンプ12において、抵抗R11と同R12で設定され
る所定の利得の増幅手段120で増幅される。この増幅
された角速度信号は直ちにA/D変換回路13にてデジ
タル値V1に変換され、このデジタル値V1は以後3つ
のデジタル処理に用いられる。
First Embodiment FIG. 1 is a configuration diagram of an image stabilization apparatus that best represents the features of the present invention. In FIG. 1, a detection means for detecting the angular velocity of the behavior of an optical device (not shown) and a handheld operating device such as a camera. The angular velocity signal output from the gyro 11 is
In the amplifier 12, it is amplified by the amplifying means 120 having a predetermined gain set by the resistors R11 and R12. The amplified angular velocity signal is immediately converted into a digital value V1 by the A / D conversion circuit 13, and this digital value V1 is used for three digital processes thereafter.

【0019】上記増幅手段120は、演算増幅器12と
2個の抵抗R11、R12とで構成し、その抵抗の一方
R11の一端は前記検出手段11の出力端に、該抵抗R
11の他端と別の抵抗R12の一端は演算増幅器12の
負入力端に、この別の抵抗R12の他端とA/D変換手
段13の入力端は演算増幅器12の出力端に、D/A変
換手段14の出力端は演算増幅器12の正入力端に各々
接続されている。
The amplifying means 120 comprises an operational amplifier 12 and two resistors R11 and R12, one of the resistors R11 having one end at the output end of the detecting means 11 and the resistor R11.
The other end of the resistor R12 and the other end of the resistor R12 are at the negative input end of the operational amplifier 12, and the other end of the other resistor R12 and the input end of the A / D conversion means 13 are at the output end of the operational amplifier 12, and D / The output terminal of the A conversion means 14 is connected to the positive input terminal of the operational amplifier 12, respectively.

【0020】まず、デジタル値V1の一つ目の行先は積
分手段151であり、角速度信号はここで積分されて角
度信号に変換される。この積分手段151は所定の時定
数で減衰する特性を持たせてあるため、正確にはカット
オフ周波数のかなり低いローパスフィルタとなってい
る。そして、積分手段151の出力V2は一方ではD/
A変換回路16にてアナログ信号に変換され、光学系に
よる補正手段17に伝達され、光学的にブレが補正され
る。また、上記出力V2は絶対値回路152−1と関数
回路152−2によって構成される制限回路32にも加
えられて利得設定値(KK)に変換される。この利得設
定値KKは利得可変増幅回路153を制御し、デジタル
値V1に対して0倍から1倍までの間で増幅率を変化さ
せる。この制限手段152では出力V2の絶対値をとっ
て所定の関数で最小から最大までの利得設定値が選択さ
れる。
First, the first destination of the digital value V1 is the integrating means 151, and the angular velocity signal is integrated here and converted into an angle signal. Since the integrator 151 has a characteristic of being attenuated with a predetermined time constant, it is accurately a low-pass filter having a considerably low cutoff frequency. The output V2 of the integrating means 151 is D /
It is converted into an analog signal by the A conversion circuit 16 and transmitted to the correction means 17 by the optical system to optically correct the blur. The output V2 is also applied to the limiting circuit 32 constituted by the absolute value circuit 152-1 and the function circuit 152-2 and converted into the gain setting value (KK). The gain setting value KK controls the variable gain amplifying circuit 153 to change the amplification factor between 0 and 1 times the digital value V1. The limiting means 152 takes the absolute value of the output V2 and selects a gain setting value from the minimum to the maximum by a predetermined function.

【0021】上記デジタルV1の2つ目の行き先は可変
利得増幅手段153であり、その可変利得増幅手段15
3の出力は一定利得K5が乗ぜられて高域通過フィルタ
155に加えられ、出力V4を得る。また、デジタル値
V1の3つ目の行き先は所定利得増幅回路154であ
り、ここでK_FIL倍されて出力V5となり、この出
力V5は上述の出力V4と加算されて積分手段156に
て積分される。
The second destination of the digital V1 is the variable gain amplifying means 153, which is the variable gain amplifying means 15.
The output of 3 is multiplied by a constant gain K5 and added to the high pass filter 155 to obtain the output V4. The third destination of the digital value V1 is the predetermined gain amplifying circuit 154, which is multiplied by K_FIL to become the output V5. This output V5 is added to the above-mentioned output V4 and integrated by the integrating means 156. .

【0022】この積分手段16の出力値(V7)はD/
A変換回路14によって再びアナログ信号に変換され、
増幅回路12の正入力に加えられる。
The output value (V7) of the integrating means 16 is D /
The signal is again converted into an analog signal by the A conversion circuit 14,
Applied to the positive input of amplifier circuit 12.

【0023】つぎにA/D変換からD/A変換に至るま
での処理機能について説明する。
Next, the processing functions from A / D conversion to D / A conversion will be described.

【0024】演算増幅回路12と抵抗R11、R12に
よって構成される増幅回路、所定利得増幅回路154、
積分手段156によって一次のローパスフィルタが形成
されている。これによって、直流的に不確定なジャイロ
出力が所定の電位を中心にして変化し、且つ必要な増幅
を施された信号としてA/D変換に加えられる。
An amplifier circuit composed of the operational amplifier circuit 12 and resistors R11 and R12, a predetermined gain amplifier circuit 154,
The integrating means 156 forms a first-order low-pass filter. As a result, the gyro output, which is indeterminate in terms of direct current, changes around a predetermined potential and is added to the A / D conversion as a signal that has undergone the necessary amplification.

【0025】また、電源投入時等の系の初期化が必要な
時期においては、必要時間だけ所定利得増幅回路154
の所定利得を大きい値に設定して系を動作させることに
よって、系を速やかに安定状態に設定することが可能で
ある。
In addition, at the time when system initialization is required, such as when the power is turned on, the predetermined gain amplification circuit 154 is required for the required time.
It is possible to quickly set the system to a stable state by setting the predetermined gain of 1 to a large value and operating the system.

【0026】パンニング時など、装置が大きく角度を変
化させた場合、積分手段151の出力V2は大きく中心
からズレようとすると、制限手段152がこれを検知し
て可変利得増幅手段153の利得を大きい方に変化させ
る。
When the device greatly changes the angle, such as during panning, when the output V2 of the integrating means 151 tends to deviate from the center, the limiting means 152 detects this and the gain of the variable gain amplifying means 153 is increased. Change to one direction.

【0027】第2の実施例 以上のように動作する上記のA/D変換からD/A変換
の処理部分は、ハードウエアロジック回路で構成しても
よいし、コンピュータで実現してもよい。以下、コンピ
ュータで実現する場合のプログラム例を示す。
Second Embodiment The processing portion for the above A / D conversion to D / A conversion which operates as described above may be constituted by a hardware logic circuit or may be realized by a computer. The following is an example of a program when implemented by a computer.

【0028】記述言語はCであり、図1に示した各値に
対応した変数を用いてデジタル処理の部分のみを抜粋し
て記述している。
The description language is C, and only the digital processing portion is extracted and described using the variables corresponding to the respective values shown in FIG.

【0029】諸定数はサンプリング周波数500Hz程
度の場合の例であり、ジャイロ感度は約1mV/deg
/secのものを用い、アンプゲインは約45倍、補正
系の光学補正量は約1deg/V、各変数の単位はVo
ltである。
The constants are examples when the sampling frequency is about 500 Hz, and the gyro sensitivity is about 1 mV / deg.
/ Sec, the amplifier gain is about 45 times, the optical correction amount of the correction system is about 1 deg / V, and the unit of each variable is Vo.
It is lt.

【0030】 { #define GAIN 0.07 #define K_FIL -0.0003 #define K3 0.995 #define K_INT 0.9999 #define K5 -0.002 float V1,V2,V3,V4,V5,V6,V7: float KK; float z[4]; V2=V1*GAIN+z[3]*K_INT; KK=V2; if(KK<0.0)KK=-KK; // 絶対値 KK=-0.75+(KK*2.5); if(KK<0.0)KK=0.0; if(KK<1.0)KK=1.0; // 関数 V3=V1*KK*K5; V4=V3-z[2]+z[1]*3; V5=V1*K_FIL; V6=V4+V5; V7=V5+z[0]; z[0]=V6;z[1]=V4;z[2]=V3;z[3]=V2; } 電源投入時等では初期化は定数K_FILをより絶対値
の大きな値に設定し、所定回数の繰り返し処理を施せば
実現出来るし、駆動のON/OFFは定数GAINをゼ
ロと切り替えると実現出来る。
{#Define GAIN 0.07 #define K_FIL -0.0003 #define K3 0.995 #define K_INT 0.9999 #define K5 -0.002 float V1, V2, V3, V4, V5, V6, V7: float KK; float z [4]; V2 = V1 * GAIN + z [3] * K_INT; KK = V2; if (KK <0.0) KK = -KK; // absolute value KK = -0.75 + (KK * 2.5); if (KK <0.0) KK = 0.0; if (KK <1.0) KK = 1.0; // Function V3 = V1 * KK * K5; V4 = V3-z [2] + z [1] * 3; V5 = V1 * K_FIL; V6 = V4 + V5; V7 = V5 + z [0]; z [0] = V6; z [1] = V4; z [2] = V3; z [3] = V2;} Initialization is a constant K_FIL when the power is turned on. Can be realized by setting a larger absolute value and repeating a predetermined number of times, and ON / OFF of driving can be realized by switching the constant GAIN to zero.

【0031】以上の動作を図2に示すフローチャートを
用いて説明する。ここに示すシステムは電源の投入によ
って動作を開始し(501)。ハードウエアを含めた系
全体の初期設定が、502から506の処理のループで
行われる。まず、502では各変数が収束しやすいよう
に定数が設定され、503ではA/D入力からD/A変
換回路16のD/A出力までの演算、504ではA/D
入力からD/A変換回路14のD/A出力までの演算、
505では遅延要素の更新が行われる。
The above operation will be described with reference to the flowchart shown in FIG. The system shown here starts its operation when the power is turned on (501). Initialization of the entire system including hardware is performed in a loop of processing from 502 to 506. First, in 502, constants are set so that each variable easily converges. In 503, calculation from A / D input to D / A output of D / A conversion circuit 16 is performed. In 504, A / D is performed.
Calculation from input to D / A output of D / A conversion circuit 14,
At 505, the delay element is updated.

【0032】定数K_FILは通常の値よりも大きい絶
対値が設定され、アナログアンプ12を含むフィードバ
ックループを速やかに安定の状態に収束させる。ここで
はループ回数を100に設定しており、約0.2秒で安
定状態になる。
The constant K_FIL is set to an absolute value larger than a normal value, and the feedback loop including the analog amplifier 12 quickly converges to a stable state. Here, the number of loops is set to 100, and the stable state is reached in about 0.2 seconds.

【0033】初期設定が完了すると、507で通常動作
状態での各定数が設定され、通常の500Hzサンプリ
ングの無限ループに入る。まず、508に於いて防振ス
イッチのON/OFFがチェックされ、ONの時はGA
INを然るべき値に、OFFの時はゼロに設定する。5
09はA/D入力からD/A入力からD/A変換回路1
6のD/A出力までの演算処理である。
When the initial setting is completed, the constants in the normal operation state are set at 507, and the normal 500 Hz sampling infinite loop is entered. First, at 508, ON / OFF of the anti-vibration switch is checked, and when ON, GA
Set IN to the appropriate value and zero when OFF. 5
Reference numeral 09 denotes an A / D input to D / A input to D / A conversion circuit 1
6 is a calculation process up to D / A output.

【0034】510は積分出力値の絶対値をとる処理、
511は折れ線関数の処理で、510と511の処理で
図3に示す変換が行われる。ここで得られた利得設定値
KKがパンニング制御の強さを示している。512はA
/D入力からD/A入力からD/A変換回路14のD/
A出力までの演算処理で、上で求めた利得設定値KKが
関与している。513では遅延要素の更新が行なわれ
る。
Reference numeral 510 is a process for taking the absolute value of the integrated output value,
Reference numeral 511 denotes a polygonal line function process, and the conversion shown in FIG. 3 is performed by the processes 510 and 511. The gain setting value KK obtained here indicates the strength of the panning control. 512 is A
/ D input to D / A input to D / A of D / A conversion circuit 14
The gain setting value KK obtained above is involved in the arithmetic processing up to the A output. At 513, the delay element is updated.

【0035】以上が1回のサンプリングの処理であり、
次のサンプリング処理が開始されるタイミングまで待機
する。
The above is the processing of one sampling,
The process waits until the next sampling process starts.

【0036】本システムによると、以上で示したような
極めて単純なプログラムでパンニング処理も含めて実現
できるため、安価なマイクロコンピュータでも十分であ
り、また、同装置内に他の目的のためのA/D変換やD
/A変換、マイクロコンピュータ等(例えば、ビデオカ
メラなどでは、オートフォーカスのための高機能マイク
ロコンピュータや、さまざまな目的のための多入力A/
D変換器や多出力D/A変換器)であれば、全て100
%活用されているとは限られないので、これらの余剰部
分を活用することによってほとんどコストアップ無し
に、ブレ緩和システムの制御部を構成することができ
る。
According to the present system, since an extremely simple program as described above can be realized including the panning processing, an inexpensive microcomputer is sufficient, and the A for other purposes can be installed in the same device. / D conversion and D
A / A conversion, microcomputer, etc. (for example, in a video camera, etc., a high-performance microcomputer for autofocusing, multi-input A / for various purposes)
If it is a D converter or a multi-output D / A converter), all 100
Since it is not necessarily used, the control unit of the blurring reduction system can be configured with almost no increase in cost by utilizing these surplus portions.

【0037】第3の実施例 図4は上記増幅手段120の種々の構成例を示したもの
で、図4(a)は演算増幅器12と2個の抵抗R41
1、R412とで構成し、その一方の抵抗R412の一
端をD/A変換手段14の出力端に該抵抗の他端と別の
抵抗R411の一端を演算増幅器12の負入力端に、こ
の別の抵抗411の他端とA/D変換手段13の入力端
を演算増幅器12の出力端に、検出手段11の出力端は
演算増幅器12の正入力端に各々接続されている。
Third Embodiment FIG. 4 shows various structural examples of the amplifying means 120. FIG. 4A shows an operational amplifier 12 and two resistors R41.
1 and R412, one end of the resistor R412 is used as an output end of the D / A conversion means 14 and the other end of the resistor R411 is used as a negative input end of the operational amplifier 12, and The other end of the resistor 411 and the input end of the A / D conversion means 13 are connected to the output end of the operational amplifier 12, and the output end of the detection means 11 is connected to the positive input end of the operational amplifier 12.

【0038】図4(b)は演算増幅器12と3個の抵抗
R421、R422、R423とで構成し、その抵抗R
421の一端を検出手段11の出力端に該抵抗の他端と
別の抵抗R422、R423の一端を演算増幅器12の
負入力端に、この別の抵抗R422の他端とA/D変換
手段13の入力端を演算増幅器12の出力端に、抵抗R
423の他端をはD/A変換手段14の出力端に、演算
増幅器12の正入力端を所定電位に各々接続されてい
る。
FIG. 4B is composed of an operational amplifier 12 and three resistors R421, R422 and R423, and the resistor R
One end of 421 is the output end of the detection means 11 and the other end of the resistance is another resistance R422, R423 is the negative input end of the operational amplifier 12, the other end of the other resistance R422 and the A / D conversion means 13 To the output terminal of the operational amplifier 12, the resistor R
The other end of 423 is connected to the output end of the D / A conversion means 14, and the positive input end of the operational amplifier 12 is connected to a predetermined potential.

【0039】図4(c)は演算増幅器12と4個の抵抗
R431〜R434とで構成し、その抵抗R431の一
端を所定電位に該抵抗の他端と抵抗R432の一端をは
演算増幅器12の負入力端に、この抵抗R432の他端
とA/D変換手段13の入力端を演算増幅器12の出力
端に、抵抗R433の一端を検出手段11の出力端に、
該抵抗の他端と抵抗R434の一端を演算増幅器12の
正入力端に、この抵抗R434の他端をD/A変換手段
14の出力端に各々接続されている。
FIG. 4C is composed of an operational amplifier 12 and four resistors R431 to R434. One end of the resistor R431 is set to a predetermined potential and the other end of the resistor R432 and one end of the resistor R432 are connected to the operational amplifier 12. At the negative input end, the other end of the resistor R432 and the input end of the A / D conversion means 13 are used as the output end of the operational amplifier 12, and one end of the resistor R433 is used as the output end of the detection means 11.
The other end of the resistor and one end of the resistor R434 are connected to the positive input end of the operational amplifier 12, and the other end of the resistor R434 is connected to the output end of the D / A conversion means 14.

【0040】[0040]

【発明の効果】以上説明したように、本出願に係る第1
の発明によれば、次のような特有の効果が得られる。 (1)直流成分のカットや長時間の時定数実現のために
要していた大容量のコンデンサが全て排除できて、コス
ト上と実装容積上で有利になった。 (2)時定数制御を全てデジタル処理することにより、
電源投入時等での初期化に要する時間が大幅に短縮でき
た。 (3)A/D変換器の入力段階ですでに大振幅入力に対
する制限がかかっているので、A/D変換のダイナミッ
クレンジまたは有効ピット数が節約できた。 (4)コンデンサを不要としたので、コンデンサに対す
るリーク電流もない。このため、オペアンプのオフセッ
ト電圧に起因する直流的オフセットを補正するための調
節や補正手段が不要になった。
As described above, the first aspect of the present application
According to the invention, the following unique effects can be obtained. (1) All the large-capacity capacitors required for cutting the DC component and realizing the long time constant can be eliminated, which is advantageous in terms of cost and mounting volume. (2) By digitally processing all time constant control,
The time required for initialization when the power was turned on was greatly reduced. (3) Since the large amplitude input is already limited at the input stage of the A / D converter, the dynamic range of A / D conversion or the number of effective pits can be saved. (4) Since no capacitor is required, there is no leakage current to the capacitor. Therefore, no adjustment or correction means for correcting the DC offset caused by the offset voltage of the operational amplifier is required.

【0041】本出願に係る第2の発明によれば、上記第
1の発明の作用効果を有するブレ緩和装置を備えた光学
装置を得ることができるという効果がある。
According to the second invention of the present application, there is an effect that it is possible to obtain an optical device equipped with the shake reduction device having the operation and effect of the first invention.

【0042】本出願に係る第3の発明によれば、上記第
1の発明の作用効果を有するブレ緩和装置を備えたカメ
ラを得ることができるという効果がある。
According to the third invention of the present application, there is an effect that it is possible to obtain a camera equipped with the shake reduction device having the operation and effect of the first invention.

【図面の簡単な説明】[Brief description of drawings]

【図1】図1は本発明の第1の実施例に係るブレ緩和装
置の構成図。
FIG. 1 is a configuration diagram of a blur reduction device according to a first embodiment of the present invention.

【図2】図2は本発明の第2の実施例に係るブレ緩和装
置の処理動作を説明するフローチャート。
FIG. 2 is a flowchart illustrating a processing operation of a blur reduction device according to a second embodiment of the present invention.

【図3】図3はパンニング処理の強さを示す関数特性
図。
FIG. 3 is a function characteristic diagram showing the strength of panning processing.

【図4】図4は本発明の第3の実施例に係る増幅手段の
構成図。
FIG. 4 is a configuration diagram of an amplification means according to a third embodiment of the present invention.

【図5】図5は従来のブレ緩和装置の構成図。FIG. 5 is a block diagram of a conventional blur reduction device.

【図6】図6は従来のブレ緩和装置の構成図。FIG. 6 is a block diagram of a conventional blur reduction device.

【符号の説明】[Explanation of symbols]

11 ジャイロ(検知手段) 12 演算増幅器(増幅手段) 13 A/D変換回路 14、16 D/A変換回路 17 補正手段 151 積分手段(信号処理手段) 153 可変利得増幅手段 154 所定利得増幅手段 22、151、156 積分手段 Reference Signs List 11 gyro (detection means) 12 operational amplifier (amplification means) 13 A / D conversion circuit 14, 16 D / A conversion circuit 17 correction means 151 integration means (signal processing means) 153 variable gain amplification means 154 predetermined gain amplification means 22, 151, 156 integrating means

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】 装置の状態を検知し、検知状態をアナロ
グ信号として出力する検知手段と、前記検知手段の出力
を所定の利得で増幅する増幅手段と、前記増幅手段の出
力をデジタル信号に変換するA/D変換手段と、前記A
/D変換手段の出力に応じて第1と第2の値が変化する
信号処理手段と、前記信号処理手段の第1の値に応じて
動作する手段とを有する装置において、デジタル信号で
ある前記第2の値をアナログ信号に変換し、変換後のア
ナログ信号によって前記増幅手段の動作点を制御するた
めのD/A変換手段を具備したことを特徴とするブレ緩
和装置。
1. A detection means for detecting the state of the device and outputting the detection state as an analog signal, an amplification means for amplifying the output of the detection means with a predetermined gain, and an output of the amplification means converted to a digital signal. A / D conversion means for
An apparatus having a signal processing unit whose first and second values change according to the output of the D / D conversion unit, and a unit operating according to the first value of the signal processing unit, wherein the device is a digital signal. An image stabilization device comprising a D / A conversion means for converting the second value into an analog signal and controlling the operating point of the amplification means by the converted analog signal.
【請求項2】 前記装置とは光学装置、前記装置状態と
は位置と姿勢(角度)の少なくとも1つ、前記検知手段
とは速度センサ、加速度センサ、角速度センサ、角加速
度センサの何れか少なくとも1つであり、前記動作する
手段とはプリズムの頂角を変える手段、レンズを光軸と
直角方向にシフトさせる手段、レンズを光軸と直交する
軸のまわりに回動させる手段、撮像素子を光軸と直角方
向にシフトさせる手段、ミラーの反射角を変える手段、
撮像画面の切り出し領域を電子的に変える手段の何れか
少なくとも1つであることを特徴とする請求項1記載の
ブレ緩和装置。
2. The device is an optical device, the device state is at least one of position and orientation (angle), and the detection means is at least one of a velocity sensor, an acceleration sensor, an angular velocity sensor, and an angular acceleration sensor. The means for operating are means for changing the apex angle of the prism, means for shifting the lens in the direction perpendicular to the optical axis, means for rotating the lens around an axis orthogonal to the optical axis, and optical means for the image pickup device. Means for shifting in the direction perpendicular to the axis, means for changing the reflection angle of the mirror,
2. The blur reduction device according to claim 1, wherein the blur reduction device is at least one of means for electronically changing a cutout area of an image pickup screen.
【請求項3】 前記信号処理手段は、前記A/D変換手
段の出力値を積分し、所定の時定数で減衰する第1の積
分手段と、前記第1の積分手段の出力値(V2)に応じ
て利得が変化し、前記A/D変換手段の出力値(V1)
を入力とする利得可変増幅手段と、前記A/D変換手段
の出力値を入力とする所定利得増幅手段と、前記利得可
変増幅手段の出力値(V3)に応じて変化する値(V
4)に、前記所定利得増幅手段の出力値(V5)を加え
て積分する第2の積分手段とを有し、前記第2の値は前
記第2の積分手段の出力値(V7)に応じて変化するこ
とを特徴とする請求項1記載のブレ緩和装置。
3. The signal processing means integrates an output value of the A / D conversion means and attenuates with a predetermined time constant, and an output value (V2) of the first integration means. Gain changes according to the output value (V1) of the A / D conversion means.
A variable gain amplifying means having an input, a predetermined gain amplifying means having an output value of the A / D converting means as an input, and a value (V that changes according to the output value (V3) of the variable gain amplifying means.
4) and a second integrating means for adding and integrating the output value (V5) of the predetermined gain amplifying means, the second value depending on the output value (V7) of the second integrating means. The blurring reduction device according to claim 1, wherein the blurring reduction device changes.
【請求項4】 前記利得可変増幅手段の出力値(V3)
に応じて変化する値(V4)の周波数特性は低域利得が
高域利得より低いことを特徴とする請求項3記載のブレ
緩和装置。
4. The output value (V3) of the variable gain amplifying means.
4. The vibration reduction device according to claim 3, wherein the frequency characteristic of the value (V4) that changes according to is that the low-frequency gain is lower than the high-frequency gain.
【請求項5】 前記増幅手段は、第1の抵抗の一端を前
記検知手段の出力端に、この第1の抵抗の他端と第2の
抵抗の一端を演算増幅器の負入力端に、この第2の抵抗
の他端とA/D変換手段の入力端を前記演算増幅器の出
力端に、D/A変換手段の出力端を前記演算増幅器の正
入力端に接続して構成したことを特徴とする請求項1記
載のブレ緩和装置。
5. The amplifying means has one end of a first resistor as an output end of the detecting means, and the other end of the first resistor and one end of a second resistor as a negative input end of an operational amplifier. The other end of the second resistor and the input end of the A / D conversion means are connected to the output end of the operational amplifier, and the output end of the D / A conversion means is connected to the positive input end of the operational amplifier. The shake reduction device according to claim 1.
【請求項6】 前記増幅手段は、第1の抵抗の一端をD
/A変換手段の出力端に、この第1の抵抗の他端と第2
の抵抗の一端を演算増幅器の負入力端に、この第2の抵
抗の他端とA/D変換手段の入力端を前記演算増幅器の
出力端に、前記検知手段の出力端を演算増幅器の正入力
端に接続して構成したことを特徴とする請求項1記載の
ブレ緩和装置。
6. The amplifying means connects one end of the first resistor to D.
The other end of the first resistor and the second end are connected to the output end of the / A conversion means.
One end of the resistor is the negative input end of the operational amplifier, the other end of the second resistor and the input end of the A / D conversion means are the output end of the operational amplifier, and the output end of the detection means is the positive end of the operational amplifier. The vibration reduction device according to claim 1, wherein the vibration reduction device is configured to be connected to the input end.
【請求項7】 前記増幅手段は、第1の抵抗の一端を前
記検知手段の出力端に、この第1の抵抗の他端と第2、
第3の抵抗の一端を演算増幅器の負入力端に、この第2
の抵抗の他端とA/D変換手段の入力端を前記演算増幅
器の出力端に、前記第3の抵抗の他端をD/A変換手段
の出力端に、前記演算増幅器の正入力端を所定電位に接
続して構成したことを特徴とする請求項1記載のブレ緩
和装置。
7. The amplifying means has one end of the first resistor as an output end of the detecting means, the other end of the first resistor and a second end,
One end of the third resistor is connected to the negative input end of the operational amplifier and the second
The other end of the resistor and the input end of the A / D conversion means to the output end of the operational amplifier, the other end of the third resistor to the output end of the D / A conversion means, and the positive input end of the operational amplifier. The vibration reduction device according to claim 1, wherein the vibration reduction device is configured to be connected to a predetermined potential.
【請求項8】 前記増幅手段は、第1の抵抗の一端を所
定電位に、この第1の抵抗の他端と第2の抵抗の一端を
演算増幅器の負入力端に、この第2の抵抗の他端とA/
D変換手段の入力端を前記演算増幅器の出力端に、第3
の抵抗の一端を前記検知手段の出力端に、この第3の抵
抗の他端と第4の抵抗の一端を前記演算増幅器の正入力
端に、この第4の抵抗の他端をD/A変換手段の出力端
に接続して構成したことを特徴とする請求項1記載のブ
レ緩和装置。
8. The amplifying means has one end of a first resistor at a predetermined potential, the other end of the first resistor and one end of a second resistor as a negative input end of an operational amplifier, and the second resistor. And the other end of
The input terminal of the D conversion means is connected to the output terminal of the operational amplifier,
One end of the resistor is the output end of the detecting means, the other end of the third resistor and the fourth resistor are the positive input end of the operational amplifier, and the other end of the fourth resistor is D / A. The shake reduction device according to claim 1, wherein the shake reduction device is configured to be connected to an output end of the conversion means.
【請求項9】 請求項1に記載のブレ緩和装置を備えた
ことを特徴とする光学装置。
9. An optical device comprising the shake reduction device according to claim 1.
【請求項10】 請求項1に記載のブレ緩和装置を備え
たことを特徴とするカメラ。
10. A camera comprising the shake reduction device according to claim 1.
JP30956094A 1994-11-17 1994-11-17 Shake reduction device, optical device and camera Pending JPH08149363A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP30956094A JPH08149363A (en) 1994-11-17 1994-11-17 Shake reduction device, optical device and camera
US08/558,527 US5805212A (en) 1994-11-17 1995-11-16 Vibration correcting apparatus controlling the gain of the control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30956094A JPH08149363A (en) 1994-11-17 1994-11-17 Shake reduction device, optical device and camera

Publications (1)

Publication Number Publication Date
JPH08149363A true JPH08149363A (en) 1996-06-07

Family

ID=17994497

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30956094A Pending JPH08149363A (en) 1994-11-17 1994-11-17 Shake reduction device, optical device and camera

Country Status (1)

Country Link
JP (1) JPH08149363A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005340799A (en) * 2004-04-27 2005-12-08 Hitachi High-Tech Instruments Co Ltd Electronic component mounting method and electronic component mounting equipment
JP2010225066A (en) * 2009-03-25 2010-10-07 Rohm Co Ltd Servo control circuit, controller of actuator, and imaging device
JP2011018918A (en) * 2004-04-27 2011-01-27 Hitachi High-Tech Instruments Co Ltd Electronic component mounting method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005340799A (en) * 2004-04-27 2005-12-08 Hitachi High-Tech Instruments Co Ltd Electronic component mounting method and electronic component mounting equipment
JP2011018918A (en) * 2004-04-27 2011-01-27 Hitachi High-Tech Instruments Co Ltd Electronic component mounting method
JP2010225066A (en) * 2009-03-25 2010-10-07 Rohm Co Ltd Servo control circuit, controller of actuator, and imaging device

Similar Documents

Publication Publication Date Title
US7917022B2 (en) Shaking sensing and correction apparatus and method
US20020047906A1 (en) Photographing apparatus having variable image blur correction control characteristics for still photography and motion picture photography
JPH03204280A (en) Picture processing unit
US5099694A (en) Vibration detecting apparatus
KR20080106981A (en) Angular velocity sensor interface circuit and angular velocity determining apparatus
JPH05142614A (en) Image blurring preventing device
JP4776974B2 (en) Image blur correcting lens device and correction method thereof
JPH05323436A (en) Image blur preventive device
JP2001188272A (en) Image pickup device, and device and method for vibration- proofing
US5890018A (en) Camera shake amplitude detecting device
JPH08149363A (en) Shake reduction device, optical device and camera
JP2006292845A (en) Imaging apparatus
JP4329151B2 (en) Shake detection device and camera shake correction camera
JP3416953B2 (en) Screen shake detection circuit and screen shake detection method
JP3569948B2 (en) Runout detection device
JP3524202B2 (en) Runout mitigation device
JP3437339B2 (en) Image stabilizer
JP2003131281A (en) Device for correcting image blurring
JPH08262522A (en) Shake correction device
JP3253067B2 (en) Imaging device
JPH08265634A (en) Shake correction device
JPH05199448A (en) Vibration proof camera
JPH1090742A (en) Shake detecting device
JPH0918779A (en) Vibration buffer device
JPH10161172A (en) Device for preventing image blurring

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20031226

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20040106

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040308

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20040928