JPH08149003A - Pll frequency synthesizer and device using the synthesizer - Google Patents

Abstract

PURPOSE: To provide a PLL frequency synthesizer which can shorten the waiting time needed for setting a dividing ratio and also can quickly set the dividing ratio. CONSTITUTION: The input signal received from an input terminal 2 and the reference signal received from an input terminal 6 are divided by a counter 8 and a reference counter 9 respectively. The output signals of both counters 8 and 9 are compared with each other by a phase comparator 10, and this comparison output is supplied to an output terminal 13 or to an output terminal 12 via a switch 11. If the setting data are inputted from an input terminal 3 while an LE (load enable) signal is kept at 'L', the setting data are fetched by a shift register 7. Then the LE signal is changed to 'H' and a latch clock is outputted from a latch clock generating circuit 15 at the rise of the LE signal. Thus the setting data are transferred to the counters 8 or 9 from the register 7, and the dividing ratios of both counters are changed. The switch 11 is turned on and the terminal 12 is effective while the LE signal is kept at 'H'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL frequency synthesizer suitable for use in a cellular radio or the like.

[0002]

2. Description of the Related Art In a radio device such as a cellular radio telephone, a PLL frequency synthesizer is provided in its transmitting portion and receiving portion in order to make the oscillation frequency of a local oscillator variable so that the channel can be switched or stabilized. .

FIG. 12 is a block diagram showing an example of such a conventional PLL frequency synthesizer, 1 being the P
LL frequency synthesizer, 2 to 6 are input terminals, 7 is a shift register, 8 is a counter, 9 is a reference counter, 10 is a phase comparator, 11 is a switch, 12 and 13 are output terminals, and 14 is a loop filter.

In FIG. 1, the PLL frequency synthesizer 1 is composed of a shift register 7, a counter 8 including a prescaler, a swallow counter, a program counter, a reference counter 9, a phase comparator 10 and a switch 11, and an output terminal. The time constant of the loop filter 14 is switched by the output signals from 12 and 13. Although not shown, the output signal of the loop filter 14 is, for example, a VCO as a local oscillator of a transmitter or a receiver.
It is supplied as a control signal to the (voltage controlled oscillator), and the oscillation frequency of the VCO is controlled by this control signal.

The output signal F _{VCO of} this VCO is input terminal 2
Is input from the input terminal 1 and is frequency-divided by the counter 8 by the frequency dividing ratio m, and then supplied to the phase comparator 15. Further, a reference signal F _OSC having a stable frequency from a reference oscillator (not shown) using a crystal oscillator or the like is input from the input terminal 6, divided by the reference counter 9 by the division ratio n, and then the phase comparator 10 Is supplied to. In the phase comparison 10, the phases of these two frequency-divided output signals are compared, and a signal corresponding to the phase difference is output, and this output signal is supplied to the switch 11 and the output terminal 13. When the switch 11 is off, the output signal of the phase comparator 10 obtained at the output terminal 13 is supplied as a control signal to the VCO via the loop filter 14, and the switch 1
When 1 is on, the loop filter 14 is switched to one having a small time constant, and the output signal of the phase comparator 10 passes through the switch 11 and is output as a control signal to the VCO via the output terminal 12 and this loop filter 14. Supplied.

When the frequency of the reference signal F _OSC output from the reference oscillator is f _OSC , a PLL is formed by such a configuration, and the frequency f _VCO of the output signal F _VCO of the _VCO is f _VCO.
Stabilizes at f _VCO = f _OSC · m / n.

The frequency division ratio m of the counter 8 and the frequency division ratio n of the reference counter 9 are calculated from the input terminal 3 to the shift register 7.
The value is set to a value according to the setting data DT in the data DH input to.

When the load enable signal LE input from the input terminal 5 is "L" (low level), the input terminal 3
Serial data DH is input from the input terminal and is input to the shift register 7 in synchronization with the clock φ input from the input terminal 4. As shown in FIG. 13, the data DH is composed of a predetermined number of bits of setting data DT from the most significant bit MSB to the least significant bit LSB, and a 1-bit register selection bit HorL following the setting data DT. The bit MSB to the register selection bit HorL are serially input from the input terminal 3, and these bits are sequentially captured in the shift register 7 at the rising edge of the clock φ. Register selection bit HorL
Determines whether the setting data DT is to be set in the counter 8 or the reference counter 9.

After the data DH is fetched by the shift register 7, the load enable signal LE is set to "H" (high level) or "OPEN" as shown in FIG.
Accordingly, the setting data DT is transferred from the shift register 7 to the counter 8 or the reference counter 9 designated by the register selection bit HorL as parallel data, and the counter 8 or the reference counter 9 responds to the setting data DT. The division ratio m or n is set.

When the load enable signal LE becomes "H" or "OPEN" as described above, the switch 1
When 1 is turned on, the time constant of the loop filter 14 becomes small, and the control signal is sent from the loop filter 14 to the VCO with this time constant. As a result, the lockup speed after setting the frequency division ratio m or n in the counter 8 or the reference counter 9 can be increased.

[0011]

As described above, in the conventional PLL frequency synthesizer, generally, the time constant of the loop filter 14 can be switched, and the shift register 7 can be switched.
The load enable signal LE is set to "H" after the end of capturing the data DH at 1, so that the switch 11 is turned on and the time constant of the loop filter 14 is reduced. Meanwhile, in order to speed up the lock-up, it is necessary to a certain longer period constant is small when the loop filter 14, and thus, only the uptake terminated after a predetermined time setting data in the shift register 7 t _LE Road The enable signal LE must be held at "H".
On the other hand, when the data DH is input when the load enable signal LE is “H”, the data DH passes through the shift register 7 and is transferred to the counter 8 or the reference counter 9, and the frequency division set therein is performed. It destroys the ratio m or n. Therefore, when inputting the data DH, the load enable signal LE must be "L".

Therefore, as shown in FIG. 14, after the frequency division ratio m or n of the counter 8 or the reference counter 9 is set by the first data DH, the new second data DH is set in the shift register. 7, the frequency division ratio m or n of the counter 8 or the reference counter 9
When changing the second data D, the load enable signal LE which is “H” is once set to “L” for a period t ₂ longer than the period t ₁ of the second data DH, and the second data D is changed within this period t ₂ .
After loading H into the shift register 7, the operation of setting the load enable signal LE to “H” again is performed, but the load enable from the setting of loading the first data DH to the loading of the second data DH period t _LE signal LE is "H", it must be greater than or period is made smaller the time constant of the loop filter 14 needed to increase the speed of the lock-up.

That is, in order to fetch the next second data DH after the first data DH is fetched and set, at least the load enable signal LE is set to "H" in order to speed up the lockup. The predetermined time t _LE which must be kept must be passed, and new data DH is not inputted from the input terminal 3 while the load enable signal LE is “H”. Therefore, in the conventional PLL frequency synthesizer described above, when it is desired to change the frequency division ratio m or n by the counter 8 or the reference counter 9, the load enable signal LE is "L".
It was necessary to wait until, and it was difficult to achieve even higher speeds.

This is a particularly important problem in, for example, a cellular radiotelephone system using such a PLL frequency synthesizer. In such a system,
A plurality of channels are set in cells divided into regions, and in each cell, the central station of each cell permits the use of unused channels. Therefore, when the cellular radiotelephone is mounted on a car, a use channel is designated every time the car passes through the cell and enters a new cell. Therefore, for example, when an automobile moves along the boundary of two cells and alternately enters and leaves these cells in a short time, channel switching is instructed in a short time. However, the conventional PLL frequency synthesizer described above is used. When it is used, the switching of the frequency division ratio cannot follow the channel switching instruction, and a situation may occur in which the call is momentarily interrupted.

An object of the present invention is to provide a PLL frequency synthesizer which solves such a problem, shortens the waiting time when changing the frequency division ratio, and can change the frequency division ratio quickly. It is in.

[0016]

In order to achieve the above object, the present invention has, in addition to the above-mentioned conventional configuration, a first control signal (corresponding to the load enable signal) for setting the switch to an ON state. Means for generating a second control signal (latch clock) having a short pulse width by detecting a rising edge of the shift register, and the shift register divides the frequency according to the set data taken in by the second control signal. The ratio is set to the first counter or the second counter.

[0017]

When the first control signal rises, the switch is held in the ON state for a predetermined period, but the second control signal generated at the rising edge of the first control signal has a short pulse width. , When the shift register sets the frequency division ratio of the first or second counter by the second control signal,
The shift register is ready to take in the next setting data. Therefore, in order to speed up the lockup, even if the "H" period of the first control signal (that is, the ON period of the switch) is lengthened, the next setting data is fetched into the shift register during this period. You can keep it
The time required to set the frequency division ratio of the first and second counters can be shortened.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a PLL frequency synthesizer according to the present invention, in which reference numeral 15 is a latch clock generation circuit, portions corresponding to those in FIG.

In the figure, this embodiment has the same configuration as the conventional PLL frequency synthesizer 1 shown in FIG. 12 except that a latch clock generation circuit 15 is provided. Again, according to this embodiment, P
It is assumed that LL is formed.

The latch clock generation circuit 15 uses the load enable signal LE input from the input terminal 5 as input data and the reference signal F _OSC from a reference oscillator (not shown) input from the input terminal 6 as a clock. Te, this reference signal F _OSC detects a rising edge of the load enable signal LE, and generates the latch clock L _C of one cycle of the pulse width of the reference signal F _OSC synchronized in phase to the reference signal F _OSC.

When the load enable signal LE is "L", the data DH consisting of the serial setting data DT and the register selection bit HorL as shown in FIG.
Is inputted and is taken into the shift register 7 by the clock φ from the input terminal 4. Then, as shown in FIG. 13, when the load enable signal LE becomes "H", the latch clock generation circuit 15 sends the shift register 7 a latch clock L of "H" immediately after the rising edge thereof.
_C is supplied, whereby the setting data DT is transferred as parallel data from the shift register 7 to the counter 8 or the reference counter 9 designated by the register selection bit HorL. In this way, the frequency division ratio m or n of the counter 8 or the reference counter 9 is changed at the timing of the latch clock L _C.

Here, the reference counter 9 and the prescaler frequency division ratio setting register are set as one set, and the program counter and the swallow counter in the counter 8 are set as one set.
For example, when the register selection bit HorL is "H", the reference counter 9 and the prescaler frequency division ratio setting register are selected, the setting data DT is set in the prescaler frequency division ratio setting register, and the register selection bit HorL is " When L ", the program counter and the swallow counter register in the counter 8 are selected, the setting data DT is set in the swallow counter register, and the division ratio n or m is changed respectively.

The data length of the data DH is equal to the bit length of the shift register 13 immediately before the load enable signal LE becomes "H". When the data DH exceeds the bit length of the shift register 13, the setting data D is set.
The data from the most significant bit MSB of T to the bit length exceeding the bit length of the shift register 13 is ignored (P in this case).
In the LL frequency synthesizer, such data is not necessary.) The register selection bit HorL and the portion of the setting data DT which is the bit length of the shift register 13 counting from the least significant bit LSB are valid. Are taken into the shift register 7.

Here, after assuming that the PLL including this embodiment is configured as described above, the output terminal 1
The loop filter 14 as shown in FIG. 12 is connected to 2 and 13, the load enable signal LE becomes “H”, the switch 11 is turned on, and the loop filter 14 is switched to one having a smaller time constant. However, even if the load enable signal LE is in the "H" state, the load enable signal LE is inverted from "L" to "H" after the load enable signal LE rises and the latch clock L _C is once supplied. Since the latch clock L _C of “H” is not supplied to the shift register 7 until then, the shift register 7 is in a state in which the data DH can be taken in (that is, the data DH passes through the shift register 7 as it is and the counter 8 or the reference It is not sent to the counter 9 and remains in the shift register 7).

Therefore, in this embodiment, even when the load enable signal LE is "H", the shift register 7 takes in the data DH and transfers it to the counter 8 or the reference counter 9 at the next latch clock L _C , The frequency division ratios m and n can be changed, which will be described more specifically with reference to FIG.

After the setting of the first data DH, the load enable signal LE becomes "L" when the predetermined "H" period t _LE of the load enable signal LE required for speeding up the lockup has elapsed. , Load enable signal LE
Can be set to "H" at any time when it becomes "L". Further, as described above, the latch clock L _C having a pulse width of one cycle of the reference signal F _OSC is generated at the rise of the load enable signal LE, and after this, the shift register 7 can take in the data DH. It will be in a state. Further, as described above, the data DH is input just before the rise of the load enable signal LE.

From the above, the load enable signal L
A period sufficiently shorter than immediately (that is, the period t _{DH of the} data _DH (equal to the period t ₂ in FIG. 14)) immediately after the predetermined time t _LE when E is “H” becomes “L”. Even if the data DH is input from the input terminal 3 at a timing such that the load enable signal LE becomes “H” (after t ₃ has elapsed), the shift register 7 can take in the data DH and set data thereof. The DT can also be transferred from the shift register 7 to the counter 8 or the reference counter 9.

According to this, the waiting time for changing the frequency division ratio of the counter 8 and the reference counter 9 can be greatly reduced. This will be described in comparison with a conventional PLL frequency synthesizer.

FIG. 3 shows the case where the minimum "H" period t _LE of the load enable signal LE required for speeding up the lockup is longer than the period t _{DH of the} data DH. In the PLL frequency synthesizer of No. 3, as shown in FIG. 3A, the load enable signal LE becomes “L” after the period t _LE has elapsed, and the next data DH can be taken into the shift register 7. However, in the case of this embodiment, as shown in FIG. 3B, the data DH can be taken in during the period t _LE in which the load enable signal LE is "H", and this period t _LE If There the load enable signal LE is "L" has elapsed, it is possible to capture data DH to the shift register 7 at timing such that immediately "H" via the short period t _3. From this, the timing of fetching the data DH into the shift register 7 after the load enable signal LE becomes "H" is the same as in the conventional PLL.
The period t _{DH of the} data DH can be moved ahead of that of the frequency synthesizer by almost the same amount, and the waiting time for changing the frequency division ratio can be shortened accordingly.

FIG. 4 is a view illustrating the case where the period t _LE <period t _DH, in the conventional PLL frequency synthesizer, as shown in FIG. 4 (a), the load enable this period t _LE has elapsed While the signal LE becomes "L", the next data DH can be taken into the shift register 7. In this embodiment, as shown in FIG. 4B, the load enable signal LE is "H". Near the beginning of the period (ie
The data DH can be taken in immediately after the latch clock L _C ), the period t _LE has elapsed during the input period of the data DH, and the load enable signal LE becomes “L”. The data DH can be taken into the shift register 7 at a timing such that LE becomes "H". From this, the timing of fetching the data DH to the shift register 7 after the load enable signal LE becomes "H" can be advanced by the period t _{LE in} comparison with the conventional PLL frequency synthesizer in this embodiment. Therefore, the waiting time for changing the division ratio can be shortened.

As described above, in this embodiment, the load enable signal LE is "H" in order to speed up the lockup.
Even during the period, the data DH can be taken into the shift register 7, the waiting time for changing the frequency division ratio of the counter 8 and the reference counter 9 can be significantly reduced, and the frequency division ratio can be changed quickly. be able to.

In the above description, the data DH is input just before the rising edge of the load enable signal LE. However, the data DH is not limited to this and may be input from the input terminal 3 immediately after the latch clock L _C. However, since the clock φ is supplied to the shift register 7 during the input period of the data DH, this data DH can be taken into the shift register 7. Therefore, in FIG. 3B, the data DH is input at the timing closer to the falling side of the load enable signal LE, but the data DH is input at the timing closer to the rising side of the load enable signal LE. However, this data DH is taken into the shift register 7. The clock φ may be always supplied, and the same applies in this case. However, the fetched data DH is transferred to the counter 8 or the reference counter 9 by the latch clock _RC generated by the rise of the load enable signal LE immediately after the "H" period t _LE of the load enable signal LE has elapsed. It goes without saying that it will be transferred.

FIG. 5 is a block diagram showing a specific example of the latch clock generation circuit 15 in FIG.
Reference numeral 7 is a D-type flip-flop circuit (hereinafter, referred to as D-FF), 18 is an inverter circuit, and 19 is a NOR circuit.

FIG. 6 is a timing chart showing the signals of the respective parts in FIG. 5, and the signals corresponding to those in FIG. 5 are designated by the same reference numerals.

In FIGS. 5 and 6, the reference signal F _OSC having the period t _OSC input from the input terminal 6 is supplied to the D-FFs 16 and 17 as a clock. In D-FF16,
Load enable signal LE inputted from the input terminal 5 is sampled and held at every rising edge of the clock F _OSC, Q ₁ rising edge is synchronized in phase with the rising edge of the rising edge of the immediately following clock F _OSC load enable signal LE Output is obtained. This Q ₁ output is D-FF
17 serve as an input D ₂ is sampled and held at every rising edge of the clock F _OSC of, than Q ₁ outputs of the D-FF16 rises with a delay of one period t _OSC of the clock F _OSC Q ₂ output.

The Q ₁ output of the D-FF 16 is level-inverted by the inverter circuit 18 and is supplied to the NOR circuit 19 as the output Q _b , and the Q ₂ output of the D-FF 17 is supplied to the NOR circuit 19 at its level. It Therefore, the NOR circuit 1
From 9 the output Q _b of the inverter circuit 18 and the D-FF 17
A signal that is "H" is output during the period when both Q ₂ outputs are "L". This output signal is the latch clock L _C.
Is. The latch clock L _C is the clock F _OSC (that is, immediately after the rising edge of the load enable signal LE).
Phase synchronization with the rising edge of the reference signal F _OSC ), and
This is a "H" signal having a pulse width equal to one cycle t _OSC of the clock F _OSC regardless of the "H" period length of the load enable signal LE.

Latch clock L thus obtained
_C is supplied to the shift register 7 of FIG. 1, and the setting data DT is transferred from the shift register 7 to the counter 8 or the reference counter 9 during the period of the latch clock L _C , and the division ratio of these is dependent on the setting data DT. It is set to a new value. Therefore, in order to speed up the lockup, the setting data D for resetting the frequency division ratio of the counter 8 or the reference counter 9 even during the period when the load enable signal LE is held in the "H" state.
T can be input from the input terminal 3, and can be stored in the shift register 7 by the clock φ from the input terminal 4.

In FIG. 1, as described above, the counter 8
Alternatively, when the change of the frequency division ratio to the reference counter 9 is completed, the signal FVCO input from the input terminal 2 for the output signal of the external VCO or the like is frequency-divided by the counter 8 and the The reference signal F _OSC input to the input terminal 6 is _divided by the reference counter 9 and these output signals are compared by the phase comparator 10.
The output signal of the phase comparator 10 is output from the switch 11 and the output terminal 12 when the switch 11 is on.
Is supplied to the VCO as a control signal after being processed by a loop filter whose time constant is set to a small value, and then, when the switch 11 is turned off, the output terminal 13 supplies the loop filter switched to a large time constant. It is processed, processed, and supplied to the VCO as a control signal.

In this way, the formed PLL is stably locked at a frequency corresponding to the frequency division ratios m and n set in the counter 8 and the reference counter 9.

Although the reference signal F _OSC is used as the clock of the latch clock generation circuit 15 in the above embodiments, the input signal F _VCO from the input terminal 2 may be used.

FIG. 7 is a block diagram showing an application example of the embodiment shown in FIG. 1, in which 20 is a VCO, 21 is a reference oscillator using a highly stable crystal oscillator, and 22 is a control circuit. The same reference numerals are given to the parts corresponding to the above drawings.

In the figure, the output terminal 13 of the phase comparator 10 (FIG. 1) is connected to the loop filter 14, and the output terminal of this loop filter 14 is connected to the VCO 20.
The output signal F _{VCO of the VCO} 20 is supplied to the input terminal 2 of the PLL frequency synthesizer 1 described with reference to FIG. Further, the output signal F _OSC of the reference oscillator 21 is supplied to the input terminal 6 of the PLL frequency synthesizer 1. The PLL is configured by the above configuration.

When the oscillation frequency f _VCO of the _{VCO 20} is changed, the control circuit 22 supplies the data DH to the input terminal 3 of the PLL frequency synthesizer 1 and the clock φ to the input terminal 4, and supplies the data DH. Upon completion, the load enable signal LE supplied to the input terminal 5 of the PLL frequency synthesizer 1 is changed from "L" to "H". As a result, the frequency division ratio m or n of the counter 8 or the reference counter 9 (FIG. 1) is changed, and at the same time, the phase comparison is performed from the output terminal 12 of the PLL frequency synthesizer 1 for a predetermined period t _LE from the rise of the load enable signal LE. The output signal of the device 10 (FIG. 1) is output, and the time constant of the loop filter 14 becomes small, and the signal processed with this time constant is supplied to the VCO 20 as an oscillation frequency control signal.

As described above, since the time constant of the loop filter 14 is set to be small for the predetermined period t _LE , the capacitor of the loop filter 14 is charged and discharged at high speed, and the VCO 20 determines the counter 8, which is determined by the above change.
A new oscillation frequency corresponding to the frequency division ratio m, n of the reference counter 9 is quickly and accurately locked, and when this predetermined period t _LE elapses, the PLL frequency synthesizer 1 shifts from the output terminal 13 to the loop filter 14. Phase comparator 1
Since the output signal of 0 is supplied, the time constant of the loop filter 14 is switched to a large value, and the VCO 20
The oscillation frequency of is stably locked to the above new frequency.

In such an application example, the VCO 20 can be used as a local oscillator in a radio transmitter / receiver such as a portable cellular radio telephone, a radio transmitter, a radio receiver, etc., and an oscillation frequency for channel switching of such a device. The switching can be performed quickly with less waiting time.

FIG. 8 is a block diagram showing a transmitter using the PLL shown in FIG. 7. Reference numeral 23 is a modulator, 24 is an amplifier, and 25 is a transmission terminal. The parts corresponding to FIG. 7 are the same. I have attached a code. However, the loop filter 14 shown in FIG. 7 is assumed to be included in the PLL frequency synthesizer 1 of the present invention.

In the figure, the transmission VCO 20 generates a transmission carrier, and the modulator 23 amplitude-modulates the transmission carrier by controlling the transmission VCO 20 by an external information signal. The PLL frequency synthesizer 1 described above constitutes a PLL together with the reference oscillator 21 and the transmission VCO 20.
As described above, the transmission VCO 20 is controlled so that the VCO 20 operates stably at the transmission carrier frequency according to the data DH from the control circuit 22. The modulated transmission carrier is amplified by the amplifier 24 and then transmitted from the transmission terminal 25.

When new data DH is supplied from the control circuit 22, the transmission carrier frequency of the transmission VCO is quickly changed to the frequency corresponding to this new data DH, whereby channel switching is performed quickly.

FIG. 9 is a block diagram showing a receiver using the PLL shown in FIG. 7, in which 26 is a receiving terminal and 27 is an R.
The F section, 28 is an IF section, and 29 is a demodulation section, and the portions corresponding to those in FIG. However, the loop filter 14 shown in FIG. 7 is assumed to be included in the PLL frequency synthesizer 1 of the present invention.

In the figure, the receiving VCO 20 operates as a local oscillator, and a desired channel of the received signal from the receiving terminal 26 is converted into an IF signal of a predetermined frequency by the RF unit 27 by this output. This IF signal is
After being extracted and amplified by the IF unit 28, it is demodulated by the demodulation unit 29 and output.

The PLL frequency synthesizer 1 described above
Constitutes a PLL together with the reference oscillator 21 and the receiving VCO 20, and, as described above, the data DH from the control circuit 22.
The VCO 20 for reception is controlled so that the VCO 20 operates stably at the local oscillation frequency corresponding to. Control circuit 2
When new data DH is supplied from 2, the reception VCO
The local oscillation frequency of the signal is rapidly changed to the frequency corresponding to this new data DH, so that in the RF unit 27, the received signals of the other channels are I of the predetermined frequency.
It becomes the F signal and is extracted by the IF unit 28. In this way, channel switching is performed quickly.

FIG. 10 is a block diagram showing a transceiver using the PLL shown in FIG. 7. 1a is the PLL frequency synthesizer of the receiving side of the present invention described above, and 1b is the transmitting side of the present invention described above. PLL frequency synthesizer,
20a is a VCO on the receiving side, 20b is a VCO on the transmitting side, 3
Reference numeral 0 is a modulation / demodulation unit, 31 is a transmission / reception changeover switch, and 32 is a transmission / reception terminal. The parts corresponding to those in FIGS. However, the loop filter 14 shown in FIG. 7 is assumed to be included in the PLL frequency synthesizers 1a and 1b of the present invention.

In the figure, the receiving section has the same structure as the receiver shown in FIG. 8, and the transmitting section has the same structure as the transmitter shown in FIG. The reference oscillator 21 is shared by the transmission / reception unit. The transmission / reception change-over switch 31 is switched between transmission and reception, and at the time of transmission, the amplifier 24 side is selected to transmit a transmission signal to the transmission / reception terminal 3.
2 is transmitted, and at the time of reception, the RF unit 27 is selected and the reception signal input from the transmission / reception terminal 32 is sent to the RF unit 27. The modulation / demodulation unit 30 receives the reception I from the IF unit 28 during reception.
The F signal is demodulated and output, and at the time of transmission, the transmission carrier of the transmission VCO 20b is amplitude-modulated by an information signal from the outside to generate a transmission signal.

Here, the transmission frequency band and the reception frequency band are different. At the time of channel switching, the control circuit 22 simultaneously sends different data DH corresponding to each newly set frequency band to the PLL frequency synthesizer 1a on the receiving side and the PLL frequency synthesizer 1b on the transmitting side. As a result, the setting is switched to the new channel. In this embodiment, the transmission and reception can be performed simultaneously.

Also, a radio apparatus such as a cellular radio telephone can have the same configuration as that of the embodiment shown in FIG. 10, as shown in FIG.

[0056]

As described above, according to the present invention,
In order to speed up the lockup of the voltage controlled oscillator,
Even when the "H" period of the first control signal is lengthened, it is possible to fetch the setting data for newly setting the division ratio within this period, and to wait for the setting of the division ratio. The time can be greatly shortened, and the division ratio of the counter can be set in a short time.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a PLL frequency synthesizer according to the present invention.

FIG. 2 is a timing chart showing a frequency division ratio resetting operation in the embodiment shown in FIG.

FIG. 3 is a diagram showing a comparative example of the time required to load setting data between the conventional PLL frequency synthesizer and the embodiment shown in FIG.

FIG. 4 is a diagram showing another comparative example of the time required to fetch the setting data between the conventional PLL frequency synthesizer and the embodiment shown in FIG.

5 is a block diagram showing a specific example of a latch clock generation circuit in FIG.

FIG. 6 is a timing diagram showing signals of various parts in FIG.

FIG. 7 is a configuration diagram showing an application example of a PLL frequency synthesizer according to the present invention.

FIG. 8 is a block diagram showing an embodiment of a transmitter using a PLL frequency synthesizer according to the present invention.

FIG. 9 is a block diagram showing an embodiment of a receiver using a PLL frequency synthesizer according to the present invention.

FIG. 10 is a block diagram showing an embodiment of a transceiver using a PLL frequency synthesizer according to the present invention.

FIG. 11 is a block diagram showing an embodiment of a wireless device using a PLL frequency synthesizer according to the present invention.

FIG. 12 is a block diagram showing an example of a conventional PLL frequency synthesizer.

FIG. 13 is a diagram showing a data setting method of a shift register.

FIG. 14 is a timing chart showing a frequency division ratio resetting operation of the counter of the conventional PLL frequency synthesizer.

[Explanation of symbols]

 1 PLL frequency synthesizer 2 Signal input terminal 3 Setting data input terminal 4 Clock input terminal 5 Load enable signal input terminal 6 Reference signal input terminal 7 Shift register 8 Counter 9 Reference counter 10 Phase comparator 11 Switch 12, 13 Output terminal 14 Loop filter 15 Latch clock generation circuit 16, 17 D-type flip-flop circuit 18 Inverter circuit 19 NOR (NOR) circuit 20 Voltage controlled oscillator 21 Reference oscillator 22 Control circuit 23 Modulator 24 Amplifier 25 Transmission terminal 26 Reception terminal 27 RF Section 28 IF section 29 demodulation section 30 modulation / demodulation section 31 transmission / reception changeover switch 32 transmission / reception terminal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuo Watanabe 5-20-1, Kamimizuhoncho, Kodaira-shi, Tokyo Inside Hitachi Semiconductor Company Division (72) Inventor Shinichi Hagiya 1410 Inada, Hitachinaka City, Ibaraki Hitachi, Ltd. Personal Media Equipment Division

Claims (9)

[Claims] 1. A first counter that divides a first input signal, a second counter that divides a second input signal, and a phase difference between output signals of the first and second counters. A phase comparator that outputs a corresponding signal, a switch to which the output signal of the phase comparator is supplied, and a first control signal at the timing of a first control signal that receives and inputs the setting data of the frequency division ratio.
A shift register for setting a frequency division ratio according to the setting data taken in by the counter, the switch being ON / OFF controlled by the first control signal, and the first or the second by the shift register. In a PLL frequency synthesizer that is kept in the ON state for a predetermined period t _LE after setting the frequency division ratio in the counter, even when the switch is in the ON state, the setting data can be taken into the shift register. A PLL frequency synthesizer provided with means for enabling it. 2. The output signal of the phase comparator according to claim 1, wherein the output signal of the switch is supplied to a circuit whose time constant can be switched, and the output signal of the switch is used as a time constant switching control signal of the circuit, A PLL frequency synthesizer characterized in that the time constant of the circuit is switched according to ON / OFF. 3. The setting data according to claim 1, wherein the setting data is taken into the shift register immediately before the rising edge of the first control signal, and the means detects the rising edge of the first control signal. Then, a second control signal for a predetermined period t _CK (where t _CK << t _LE ) is generated, and the shift register uses the second control signal to divide the frequency of the first or second counter. PLL which is set to a value according to the setting data that has been loaded.
Frequency synthesizer. 4. The means according to claim 3, wherein the means inputs the first or second input signal having the predetermined period t _CK as a cycle, and the rising edge of the first control signal is generated by the clock. Is detected and the second control signal is generated.
LL frequency synthesizer. 5. The first D-type flip-flop circuit according to claim 4, wherein the means samples and holds the first control signal at an edge of the clock, and an output of the first D-type flip-flop circuit. A second D-type flip-flop circuit that samples and holds a signal at the same edge of the clock; an inverter circuit that inverts an output signal of the first D-type flip-flop circuit; and a second D-type flip-flop circuit. A PLL frequency synthesizer, comprising a NOR circuit having an output signal and an output signal of the inverter circuit as input signals. 6. A transmitter comprising the PLL frequency synthesizer according to claim 5. 7. A receiver comprising the PLL frequency synthesizer according to claim 5. 8. A transceiver comprising the PLL frequency synthesizer according to claim 5. 9. A radio apparatus comprising the PLL frequency synthesizer according to claim 5.