JPH08148575A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE: To manufacture a high-peformance complementary bipolar transistor (BipTr) by adding the minimum process as compared with the conventional manufacturing process of BipTr. CONSTITUTION: When using a p-type semiconductor substrate, processes are in the order of (1) Formation of n<+> -type buried collector region 2 of V-NPNTr, (2) Formation of n-type buried separation region 6 of V-PNPTr, (3) Formation of an element isolation region 9 (LOCOS oxidation), and (4) Formation of p<+> -type buried collector region 13C of V-PNPTr. The processes (1) and (3) are performed under the most severe high-temperature heat treatment conditions for a long time in bipolar process. By placing the processes (2) and (4) at the later stages, the upper diffusion of the buried separation region 6 and the buried collection region 13C into an n-type epitaxial layer (n-Epi) 7 can be suppressed to certain extent, thus enabling n-Epi 7 to be thin and suppressing the Kirk effect of V-NPNTr for speeding up operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical type N on the same substrate.
The present invention relates to a semiconductor device including a complementary (complementary) bipolar transistor formed with a PN transistor and a vertical PNP transistor, and a method for manufacturing the same, and particularly to a complementary bipolar transistor in which the thickness of an n-type epitaxial layer is suppressed to improve high-speed operability. The present invention relates to a transistor and a method for manufacturing the transistor by adding a minimum number of steps as compared with a conventional process.

[0002]

2. Description of the Related Art A complementary bipolar transistor, which is a combination of an NPN transistor and a PNP transistor, has been conventionally used as a component of a push-pull circuit in a high output amplification stage of audio equipment. In recent years, system-on-chip has been promoted in high-frequency LSIs represented by UHF television tuner video intermediate frequency amplification / detection circuits or high-speed communication and optical communication signal processing circuits. There is also a demand for a method of manufacturing a complementary bipolar transistor circuit which is faster and has a higher degree of integration in a smaller number of steps.

FIG. 38 shows an example of the structure of a typical conventional complementary bipolar transistor. In this bipolar transistor, the junction between the emitter / base / collector is in the depth direction of the substrate, that is, in the vertical direction (Vertical).
Vertical NPN transistor (V-NPNT)
r) and the vertical PNP transistor (V-PNPTr) are formed on the same substrate.

In the V-NPNTr portion on the left side of the figure, p
An n ⁺ type buried collector region 103 (n ⁺ -BL) is formed in a boundary region between the type substrate (p-Sub) 101 and the n-type epitaxial layer 105 (n-Epi) thereon. The upper portion of the n-type epitaxial layer 105 is LO.
Element isolation region 1 formed by COS (selective oxidation isolation) method
It is separated into several island-shaped element formation regions by 07, and the p-type base region 11 is formed in the surface layer portion of this element formation region.
0, and n connected to the buried collector region 103
^{A +} type collector extraction region 109 is formed.

Three types of extraction electrodes made of a polysilicon layer are contacted with the upper surface of the element formation region via a SiO ₂ interlayer insulating film 113. That is, in the portion facing the base region 110, the emitter extraction electrode 11
4En (subscript n represents a component of an NPN transistor. The same applies hereinafter) and base extraction electrode 114.
Bn is brought into contact with the n ⁺ -type emitter regions 115En and p ⁺ by diffusion of impurities from these electrodes.
The base take-out area 115Bn of the mold is the base area 11
0. A collector extraction electrode 114Cn is contacted with a portion facing the collector extraction region 109, and n ^{+ is formed} by impurity diffusion from this electrode.
The collector take-out region 115Cn of the mold is formed.

Each of these extraction electrodes 114En, 114B
An emitter electrode 117En, a base electrode 117Bn, and a collector electrode 117Cn, which are each made of an Al-based multilayer film, are connected to n and 114Cn through openings formed in the SiO ₂ interlayer insulating film 116.

On the other hand, in the V-PNPTr portion on the right side of the drawing, this transistor is formed on the boundary region between the p-type substrate (p-Sub) 101 and the n-type epitaxial layer 105 (n-Epi) thereon. An n-type buried isolation region 102 (N-Pocket) for electrical isolation, and p ⁺
The buried collector region 104C of the type is sequentially formed, and the p-type well 106 (p-Well) is formed on the upper side of the buried collector region 104C by implanting ions into the n-type epitaxial layer. The p-type well 106 has its upper layer portion separated into several island-shaped element formation regions by an element isolation region 107 formed by a LOCOS (selective oxidation separation) method, and n is formed in the surface layer portion of this element formation region. A p ⁺ -type collector extraction region 108C connected to the p-type base region 111 and the p + -type buried collector region 104C is formed.

On the upper surface of the element formation region, three types of extraction electrodes made of a polysilicon layer are in contact with each other through a SiO ₂ interlayer insulating film 113. That is, in the region facing the base region 111, the emitter extraction electrode 11
4Ep (subscript p represents a constituent element of a PNP transistor. The same applies hereinafter) and base extraction electrode 114.
Bp is contacted, and p ⁺ -type emitter region 115Ep and n ⁺ -type base take-out region 115Bp, respectively, by impurity diffusion or ion implantation from these electrodes.
112 are formed in the base region 111. Further, a collector extraction electrode 114Cp is contacted with a region facing the collector extraction region 108C, and a p ⁺ -type collector extraction region 115Cp is formed by impurity diffusion from this electrode.

Each of these extraction electrodes 114Ep, 114B
An emitter electrode 117Ep, a base electrode 117Bp, and a collector electrode 117Cp, which are each made of an Al-based multilayer film, are connected to p and 114Cp through an opening provided in the SiO2 interlayer insulating film 116.

An element isolation region 1 is provided between the V-NPNTr and the V-PNPTr, and between other elements (not shown).
They are separated by a p ⁺ type channel stop layer formed on the lower side of 07. This channel stop layer is
The lower layer side channel stop layer 104iso and the upper layer side channel stop layer 108iso are stacked vertically in two stages according to a so-called face-to-face separation.

[0011]

By the way, in the complementary bipolar transistor, it is necessary to secure a certain thickness in the n-type epitaxial layer 105 in order to satisfy the performance required for the V-PNPTr. This is related to the process circumstances described below.

In the manufacturing process of the complementary bipolar transistor, it is necessary to form the n type buried isolation region 102 for electrically isolating the p ⁺ buried collector region 104C of the V-PNPTr from the p type substrate 101. The process is long and complicated as compared with the usual bipolar transistor manufacturing process. The embedded isolation region 102 needs to be formed as thick as possible and at a deep portion in the substrate, and is generally first formed in the p-type substrate 101 by vapor-diffusing n-type impurities. However, if the n ⁺ -type buried collector region 103 that requires the most severe heat treatment condition at high temperature in the manufacturing process of the complementary bipolar transistor is driven in after this, the buried isolation region 102 is n-type epitaxial. Upward diffusion occurs towards the interior of layer 105. Therefore, the thickness of the n-type epitaxial layer 105 must be secured to some extent from the beginning.

Further, the formation of the p ⁺ type buried collector region 104C of the V-PNPTr is also performed by the n type epitaxial layer 1
This is a cause of requiring 05 to have a certain thickness. The buried collector region 104C is generally formed before the n-type epitaxial layer 105, and after the n-type epitaxial layer 105 is formed, the element isolation region 107 is formed.
A LOCOS process is performed to form the. However, since this LOCOS step includes a heat treatment step that requires the second severest high temperature and long time condition in the manufacturing process of the complementary bipolar transistor, the buried collector region 104 is formed into the n-type epitaxial layer during this step. An upward diffusion occurs toward the inside of 105. In preparation for this upward diffusion, it is necessary to make the n-type epitaxial layer 105 thick.

However, forming the n-type epitaxial layer 105 thick as described above means that the V-NPNT is formed.
For r, it leads to the expansion of the collector layer, resulting in the base widening effect (or Kirk effect), lowering the cutoff frequency and lowering the operating speed.
That is, when trying to secure the performance of the V-PNPTr,
The performance of the V-NPNTr deteriorates.

Further, the increase in the thickness of the n-type epitaxial layer 105 also causes another structural complication. The above-mentioned face-to-face separation is one example.
This is because the n-type epitaxial layer 105 must be made thicker, and therefore the element isolation region 107 and the channel for one layer are formed.
This is because electrical isolation between the bipolar transistors is not possible with the stop layer alone. Here, the lower channel stop layer 104iso is V-PNPT.
The channel stop layer 108is on the upper layer side by the ion implantation process common to the buried collector region 104C of r.
o is formed by the same ion implantation process as the collector extraction region 108C of the V-PNPTr. That is, two ion implantation steps are spent on the face-to-face separation.

Moreover, the channel stop layer 1 on the upper layer side
The collector extraction region 108C of the V-PNPTr formed at the same time as 08iso is an unnecessary structure in a normal non-complementary bipolar transistor in which the n-type epitaxial layer 105 is thin. Because the n-type epitaxial layer is thin in a normal bipolar transistor, the connection between the buried collector region 104C and the collector extraction electrode 114Cp is connected to the collector extraction electrode 11C.
This is because only the collector extraction region 115Cp formed by impurity diffusion from 4Cp is sufficient.

That is, in the manufacturing process of the conventional complementary bipolar transistor, the n-type epitaxial layer 10 is used.
Since 5 is thick, face-to-face separation and an extra collector take-out region are required, which requires two ion implantation steps. In the semiconductor industry, cost reduction is an important issue that determines the survival of the industry itself.
Such an increase in the number of steps must be suppressed as much as possible.

Therefore, the present invention solves these problems,
A semiconductor device having a high-performance complementary bipolar transistor in which thickening of the n-type epitaxial layer 105 is prevented, and forming the semiconductor device by a minimum increase in the number of steps as compared with the conventional bipolar transistor manufacturing process. It is an object of the present invention to provide a manufacturing method capable of

[0019]

In the present invention, the V-PN which is a factor that hinders the thinning of the n-type epitaxial layer.
In order to suppress the upward diffusion of the buried isolation region and the buried collector region of the PTr as much as possible, the formation process of these problem regions is placed at a stage subsequent to the process in which the heat treatment condition is generally the most severe in the manufacturing process of the bipolar transistor. .

In the present invention, based on this basic idea, 2
Take street measures. The first measure is to form a buried collector region of a vertical bipolar transistor of a first conductivity type having a buried collector region of a conductivity type opposite to that of a semiconductor substrate, and then to embed a conductivity type opposite to that of the semiconductor substrate. Forming the buried isolation region of a second conductivity type vertical bipolar transistor having an isolation region and a buried collector region of the same conductivity type. The second measure is to form an element isolation region for electrically separating the vertical bipolar transistors of both conductivity types on the substrate, and then form the buried collector of the vertical bipolar transistor of the second conductivity type. Forming a region. These first
The second measure and the second measure may be implemented individually, but they are more effective if they are implemented together.

In the first measure, high-energy ion implantation capable of setting a projection range deep in the semiconductor substrate when forming a buried isolation region of a vertical bipolar transistor of the second conductivity type which requires a particular depth and thickness. Is preferable. Here, depending on the ion species, it is approximately 3
The ion acceleration energy is not less than 00 keV and is 0.
Ion implantation capable of achieving a projection range of 4 μm or more is defined as high energy ion implantation.

In the second countermeasure, the buried collector region of the vertical bipolar transistor of the second conductivity type is
They may be simultaneously formed in the impurity introduction step for forming the channel stop region of the first conductivity type vertical bipolar transistor. In this impurity introducing step, the impurity profile may be controlled by performing ion implantation a plurality of times under conditions of different ion acceleration energies.

Further, in the present invention, in addition to the structure of the substrate deep layer portion as described above, by devising the order of forming the structure of the substrate surface layer portion, the increase in the number of steps can be minimized. That is, the above-mentioned vertical bipolar type of the first conductivity type
The graft base region of the transistor can be formed at the same time as the collector extraction region of the second conductivity type vertical bipolar transistor, or both the collector extraction region and the emitter region, by a common impurity introduction process.

The semiconductor device formed according to the present invention has the thickness of the epitaxial layer of the complementary bipolar transistor optimized to a necessary minimum, whereby the collector of the vertical bipolar transistor of the first conductivity type is obtained. The expansion of layers is suppressed. Therefore, the Kirk effect is suppressed, and the operation speed is increased. Further, since the thickness of the epitaxial layer is reduced, face-to-face separation and formation of the collector extraction region are unnecessary, so that the number of ion implantation steps for element separation can be reduced once in the manufacturing process.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Considering the case of using a p-type semiconductor substrate as a general case, a vertical bipolar transistor of the first conductivity type in the present invention is a V-NPNT.
The vertical bipolar transistor of the second conductivity type is V-PNPTr. Therefore, the first measure is to form the n ⁺ type buried collector region of the V-NPNTr and then the n-type buried isolation region of the V-PNPTr, and the second measure is to form the element isolation region by LOCOS oxidation. After that, a p ⁺ type buried collector region of the V-PNPTr is formed. When the first measure and the second measure are combined, formation of the n ⁺ -type buried collector region of the V-NPNTr → n of the V-PNPTr
Formation of mold embedded isolation region → LOCOS oxidation → V-PNP
The order of steps is to form the p ⁺ -type buried collector region of Tr.

Further, as a method of suppressing the number of steps as small as possible, at the same time to form a V-NPNTr the p ⁺ -type common impurity doping process and a channel stop region and the buried collector region of the p ⁺ -type said V-PNPTr of be able to. Alternatively, for structures close to the surface layer of the substrate, and a V-NPNTr the p + -type graft base region and the V-PNPTr p ⁺ -type collector extraction region of or in addition to the p ⁺ -type emitter region, They can be simultaneously formed by a common impurity introduction step. These graft base region, collector extraction region and emitter region are usually formed by solid phase diffusion from an impurity-containing polysilicon film formed in contact with a semiconductor substrate. This impurity-containing polysilicon film becomes a base extraction electrode, a collector extraction electrode, and an emitter extraction electrode through patterning.

Specific embodiments of the present invention will be described below.

First Embodiment In this embodiment , a V-NPNTr and a V-NPNTr are used by utilizing a manufacturing process of a two-layer polysilicon type vertical bipolar transistor in which a base region and an emitter region are formed in a self-aligned manner.
A complementary bipolar transistor IC was formed adjacent to PNPTr.

First, this manufacturing process will be described with reference to FIGS.

First, a p-type <111> Si substrate 1 (p-S
ub), a SiO ₂ film (not shown) having a thickness of about 300 nm is formed by thermal oxidation, and this SiO ₂ film is VN
Open at PNTr formation region, about 1200 ° C. using Sb ₂ O _3, antimony (Sb) is vapor-phase diffused through the opening by performing vapor-phase diffusion in the conditions of 0.5 to 1 hour, n ⁺ -type Embedded collector region 2 was formed.
At this time, the sheet resistance ρ s of the buried collector region 2 is, for example, 20 to 50 Ω / □, and the junction depth xj is 1 to 2 μm.

Next, the entire surface of the substrate is thermally oxidized to a thickness of about 1
A thin 0 nm SiO ₂ film 3 was formed to prevent channeling, and a resist mask 4 was formed thereon. The resist mask 4 is provided with an opening 5 in the V-PNPTr formation region.

Next, high energy through the opening 5
By performing ion implantation, phosphorus (P ⁺ ) is introduced at a projected range of 0.4 μm or more, and the n-type buried isolation region 6 is formed.
Was formed. The ion implantation conditions at this time are, for example, an ion acceleration energy of 300 keV or more and a dose of 1 × 1.
It was set to 0 ^13-15 / cm ² .

Incidentally, a conventional general complementary bipolar
In the transistor manufacturing process, the n-type buried isolation region 6 is formed before the n ⁺ -type buried collector region 2, but the order is reversed in the present invention. Further, although it is feared that crystal defects will occur due to high-energy ion implantation at the time of forming the buried isolation region 6, since crystal defects are generally concentrated near the projection range,
This does not hinder the subsequent epitaxial growth. Rather, there is a merit that the total dose amount can be reduced as compared with the case where low energy ion implantation is performed on the substrate surface. FIG. 1 shows the steps up to this point.

Next, in order to recover the crystal defects caused by the ion implantation, annealing was performed at a temperature of 800 ° C. or higher. At this time, the n-type buried isolation region 6 expands due to the upward diffusion of the impurities, but since the impurities are originally introduced into the deep portion of the substrate, the impurity concentration near the substrate surface is kept low. In addition, this annealing is performed as a pre-treatment for the growth step of the n-type epitaxial layer 7 described below.
When hydrogen annealing is performed to reduce the native oxide film on the surface, it may be omitted. The hydrogen annealing in this case is generally performed in high-concentration hydrogen at 800 to 1100 ° C. under the condition of several tens of minutes.

Next, after removing the SiO ₂ film 3, an n-type epitaxial layer 7 (n-Epi) was grown. This n
The type epitaxial layer 7 had a resistivity of 1 to 5 Ωcm and a thickness of 0.7 to 2 μm. In the conventional complementary bipolar transistor manufacturing process, the p ⁺ type buried collector region of V-PNPTr (reference numeral 13C in FIG. 4) and the channel stop region of V-NPNTr (at the time of growing the n-type epitaxial layer 7). Since the reference numeral 13iso in FIG. 4 is formed, these upward diffusion and boron auto-
N-type epitaxial with anticipation of doping effect 7
Had to be formed thick. Also, this auto
There is also a problem that the concentration of the n epitaxial layer 7 cannot be controlled as designed by the doping. However, according to the present invention, the thickness of the n-type epitaxial layer 7 is about half that of the conventional one, and the problem associated with auto-doping does not occur.

Next, the substrate is oxidized by the LOCOS method,
The element isolation region 9 was formed. In this LOCOS method, a thickness of 2 is formed on the entire surface of the substrate by a thermal oxidation method according to a conventional method.
A pad oxide film of 0 to 50 nm is formed and further reduced pressure CV
A Si ₃ N ₄ film (not shown) having a thickness of 50 to 100 nm was formed by D. These film thicknesses were optimized in consideration of the bird's beak length, the controllability of stress and defect generation due to selective oxidation. Next, using a resist mask, Si ₃ N
_{The four} films and the pad oxide film were sequentially etched to form an oxidation mask. Further, the n-type epitaxial layer 7 exposed in the opening of the oxidation mask was further etched to form a recess so that the surface of the substrate after the selective oxidation became substantially flat. The depth of the recess was set to about half the designed film thickness of the element isolation region 4.

In this state, at 1000 to 1050 ° C., 2
~ 6 hours of pyrogenic oxidation, thickness 0.8 ~
A device isolation region 9 of 1.5 μm was formed. In the conventional complementary bipolar transistor manufacturing process, this L
Since the ion implantation for forming the p ⁺ -type buried collector region of the V-PNPTr has already been performed at the time of performing the OCOS oxidation, impurities are diffused in a wide range under the severe heat treatment condition, and as a result, n is obtained. The type epitaxial layer 7 had to be formed thick. However, the present invention does not cause such a concern.

Thereafter, Si ₃ N _{4 was} added using a hot phosphoric acid solution.
The film was removed. FIG. 2 shows the steps up to this point.

Next, phosphorus was ion-implanted through a resist mask (not shown) in order to form an n ⁺ -type collector extraction region of the V-NPNTr. Ion implantation conditions at this time are, for example, ion acceleration energy of 40 to 10
0KeV, was dose of 1 × 10 ^15-16 / cm ^2.

Subsequently, an SiO ₂ film (not shown) for flattening is formed on the entire surface of the substrate by CVD to a thickness of about 100 to 600 nm, and annealing for impurity activation is performed at 900 to 1000 ° C. for about 30 minutes. . By this annealing, an n ⁺ type collector extraction region 10C connected to the buried collector region 2 was formed.

Further, after a resist film (not shown) is formed by coating to substantially flatten the surface of the substrate, etching back is performed under the condition that the selection ratio between the resist film and the SiO ₂ film is 1: 1. Then, the bird's head and the pad oxide film in the element isolation region 9 were removed. FIG. 3 shows the steps up to this point.

Next, thermal oxidation is performed at 900 ° C. to form a thin SiO ₂ film (not shown) having a thickness of 10 to 30 nm on the surface of the substrate, and a resist mask 11 as shown in FIG. 4 is formed. Then, boron (BF ₂ ⁺ ) was ion-implanted through the opening 12. Ion implantation conditions at this time are, for example, ion acceleration energy of 200 to 50.
The dose was 0 keV and the dose was 1 × 10 ¹³ -14 / cm ² . By this ion implantation, V-NPN is formed below the element isolation region 9.
The p ⁺ -type channel stop region 13iso of tr, also in a region that overlaps the upper end of the buried isolation region 6 of the V-PNPTr to simultaneously form a buried collector region 13C of the p ⁺ -type.

When it is desired to optimize the impurity profile of the buried collector region 13C of the V-PNPTr to achieve high speed, low energy ion implantation with an ion acceleration energy of about 100 keV is added before or after the above ion implantation. However, the impurity concentration in the base / collector boundary region may be supplemented. Since the impurities at the time of low energy ion implantation are taken into the element isolation region 9 in the vicinity of the channel stop region 13iso, the isolation characteristics are not affected at all. FIG. 4 shows the steps up to this point.

Then, the entire surface of the substrate is made to have a thickness of 50 by CVD.
A SiO ₂ interlayer insulating film 14 of ˜200 nm is deposited, and this film is formed, for example, by C through a resist mask not shown.
The opening was formed by dry etching using a mixed gas of HF ₃ / O ₂ . This opening is V-NPNT
The base / emitter formation portion of r and the base / emitter formation portion and collector formation portion of the V-PNPTr are formed respectively.

Subsequently, the entire surface of the substrate is deposited by CVD to a thickness of 1
A first polysilicon layer 15 having a thickness of 00 to 300 nm was formed.

Next, in the first polysilicon layer 15, the portions which will later become the base extraction electrode (reference numeral 15Bn in FIG. 7) of the V-NPNTr and the collector extraction electrode (reference numeral 15Cp in FIG. 7) of the V-PNPTr. In order to contain p-type impurities in the resist, a resist mask 16 having an opening 17 exposing a rather wide range including these parts is formed,
Boron (BF ₂ ⁺ ) was ion-implanted. The ion implantation conditions at this time are, for example, ion acceleration energy of 30 to 70.
The keV and dose amount were set to 1 × 10 ^{14 -16} / cm ² . Figure 5
Shows the steps up to here.

Next, as shown in FIG. 6, a portion of the first polysilicon layer 15 to be a base extraction electrode (reference numeral 15Bp in FIG. 7) of the V-PNPTr later contains n-type impurities. A resist having an opening 19 exposing a rather wide range including the V-PNPTr.
A mask 18 was formed and arsenic (As ⁺ ) was ion-implanted. The ion implantation conditions at this time are, for example, an ion acceleration energy of 30 to 70 keV and a dose of 1 × 10 ^{14 -16.}
/ Cm ² .

Next, the first polysilicon layer 15 is, for example, C ₂ Cl through a resist mask (not shown).
Etching was performed using a ₃ F ₃ / SF ₆ mixed gas. As a result, as shown in FIG. 7, the base extraction electrode 15Bn of the V-NPNTr (the subscript n represents a constituent element of the V-NPNTr. The same applies hereinafter), and the V-PN.
Base extraction electrode 15Bp of PTr (subscript p is V-PN
Indicates that it is a component of PTr. The same applies below. ) And a collector extraction electrode 15Cp are formed.

Further, SiO 2 is deposited on the entire surface of the substrate by CVD.
_The inter-layer insulating film 20 was deposited to a thickness of 300 to 500 nm, and a resist mask 21 having openings 22 respectively corresponding to opening the emitter windows of V-NPNTr and V-PNPTr was formed.

Next, the SiO ₂ interlayer insulating film 20 and the base lead-out electrode 1 are placed through the resist mask 21.
5Bn are sequentially etched, and as shown in FIG.
Emitter windows for NPNTr and V-PNPTr were formed. Subsequently, the resist mask 21 is removed, a thin SiO ₂ film (not shown) having a thickness of 5 to 30 nm is formed by thermal oxidation, and then a resist mask 23 is newly provided to cover only the V-PNPTr formation region. Formed. Boron (BF ₂ ⁺ ) was ion-implanted through the opening 24 of the resist mask 23 to form the p-type intrinsic base region 25IB of the V-NPNTr. The ion implantation conditions at this time are, for example, ion acceleration energy of 20 to 100.
The keV and dose amount were set to 1 × 10 ^13-14 / cm ² .

Here, in order to further improve the high frequency characteristics of the V-NPNTr, phosphorus is ion-implanted continuously,
It is preferable to form an n ⁺ type pedestal region 26 in contact with the upper end of the buried collector region 2. Ion implantation conditions at this time are, for example, ion acceleration energy of 300 to 500 k.
The eV and dose amount can be set to the order of 10 ¹² / cm ² .

Next, as shown in FIG. 9, the V-NPN
By forming a resist mask 27 covering the Tr formation region and ion-implanting arsenic through the opening 28, the n-type intrinsic base region 29IB of the V-PNPTr is formed.
Was formed. Ion implantation conditions at this time are, for example, ion acceleration energy of 20 to 100 keV and dose of 1 ×.
It was set to 10 ^13-14 / cm ² .

Here, when it is desired to further improve the high frequency characteristics of the V-PNPTr, or when the upper diffusion end of the buried isolation region 6 exceeds the p ⁺ type buried collector region 13C and reaches the surface direction of the substrate, Subsequently, boron (B ⁺ ) is ion-implanted to form the p ⁺ type pedestal region 30 reaching the upper end of the buried collector region 13C. The ion implantation conditions at this time are, for example, an ion acceleration energy of 300 to 500 keV and a dose of 1 × 10.
It can be set to about ¹² / cm ² . FIG. 9 shows the steps up to this point.

Next, a SiO ₂ film for forming sidewalls was deposited on the entire surface of the substrate by CVD to a thickness of 300 to 600 nm and annealed at 800 to 950 ° C. for 10 to 60 minutes. By this annealing, the intrinsic base region 25IB is activated in the V-NPNTr forming region, and the p ⁺ -type graft basted region 32GBn is formed by the impurity diffusion from the base extraction electrode 15Bn. In the V-PNPTr formation region, the intrinsic base region 29IB is activated, and impurity diffusion from the base extraction electrode 15Bp and the collector extraction electrode 15Cp causes n ⁺ -type graft base region 32GBp and p ⁺ -type graft base region 32GBp, respectively. The collector extraction region 32C was simultaneously formed.

By this annealing, V-PNPT
The p + type buried collector region 13C of r is also activated,
Expanded. However, this annealing condition is L
Since the buried collector region 13C does not excessively diffuse upward because it is milder than the annealing condition at the OCOS oxidation, the n-type epitaxial layer 7 is not present.
Did not have to be made thick. This is a difference from the conventional manufacturing process of a general complementary bipolar transistor in which the p ⁺ type buried collector region 13C is formed before the LOCOS oxidation, and is an advantage of the present invention.

Next, SiO for forming the side wall
₂ film is etched back, V-NPNTr and V-PNPT
Sidewalls 31 were formed in the emitter window openings of r. FIG. 10 shows the steps up to this point.

Next, a second polysilicon layer 33 was deposited on the entire surface of the substrate by CVD to a thickness of 50 to 200 nm. Subsequently, among the second-layer polysilicon layer 33, after through a resist mask, not shown in the slightly wider range including a portion serving (code 33Ep in Figure 12) the emitter extraction electrode of V-PNPTr boron (BF ₂ ⁺ ) Was ion-implanted. The ion implantation conditions at this time are, for example, an ion acceleration energy of 30 to 100 keV and a dose of 1 × 1.
It was set to 0 ^15-16 / cm ² .

Next, of the same second polysilicon layer 33, the emitter extraction electrode of the V-NPNTr is formed later (see FIG. 12).
Arsenic is ion-implanted into a rather wide range including the portion of the reference numeral 33En) through the opening 35 of the resist mask 34 shown in FIG. Ion implantation conditions at this time are, for example, ion acceleration energy of 30 to 100 ke.
The V and dose were set to 1 × 10 15 ^-16 / cm ² .

Next, the entire surface of the substrate is covered with a SiO ₂ film (not shown), and the temperature is kept at 800 to 950 ° C. for several tens of minutes or 95.
Annealing was performed at 0 to 1100 ° C. for several seconds to several tens of seconds.
By this annealing, as shown in FIG.
In the PNTr formation region, the emitter extraction electrode 33E
By n-type impurity diffusion from n and p-type impurity diffusion from the emitter extraction electrode 33Ep in the V-PNPTr forming region, n ⁺ -type emitter regions 36En and p are respectively formed.
A + type emitter region 36Ep is formed. In addition, the collector extraction region 3 of the V-PNPTr is formed by this annealing.
2C is enlarged and connected to the p ⁺ type buried collector region 13C.

After that, the SiO ₂ film was removed by wet etching to form a resist mask 37 that selectively covered the emitter window openings of both bipolar transistors. Furthermore, this resist mask 37
The second polysilicon layer 20 is dry-etched through the V-NPNTr to extract the emitter extraction electrodes 33En and V.
-The emitter extraction electrode 33Ep of PNPTr was formed.

Next, the emitter extraction electrodes 33En,
Each extraction electrode 15Bn, 15Bp, 15 other than 33Ep
Collector extraction region 10 of Cp and V-NPNTr
In order to contact the upper layer wiring with C, dry etching is first performed using a resist mask (not shown) to open a contact hole in the SiO ₂ interlayer insulating film 20 or in addition to this SiO ₂ interlayer insulating film 14. . Subsequently, the resist mask was removed, and a laminated wiring film made of, for example, a barrier metal and an Al-1% Si film was deposited on the entire surface of the substrate by sputtering, and this was patterned. In this way, as shown in FIG. 13, the base electrode 38Bn, the emitter electrode 38En, the collector electrode 38Cn, and the V-P of the V-NPNTr are formed.
Base electrode 38Bp and emitter electrode 38E of NPTr
p and a collector electrode 38Cp were formed.

After that, the complementary bipolar transistor I is subjected to the usual processes such as multi-layer wiring and passivation.
Completed C.

Here, the IC formed as described above
1 shows the impurity profile of the V-PNPTr part of FIG.
4 shows. For comparison, the conventional complementary bipolar transistor V-PNPTr shown in FIG. 38 is used.
39 shows the impurity profile of the portion. Conventionally, the total depth of this transistor, that is, the depth from the substrate surface (the surface of the n-type epitaxial layer) to the lower end of the n-type buried isolation region (n-Pocket) (indicated by an arrow in the figure) is 8.68 μm. However, in the present invention, it was reduced to 2.50 μm, which is less than 30%. The largest contributor to this reduction is the reduction in collector thickness. This is because the p ⁺ -type buried collector region 13C of the present invention is formed after the n-type epitaxial layer 7 and the element isolation region 9, and the epitaxial growth and LOC are performed.
Since it does not have to undergo the severe heat treatment of OS oxidation,
This is because upward diffusion to the type epitaxial layer 7 side is suppressed. The next major contributor is the thickness of the substrate separation. This is also because the n-type buried isolation region 6 in the present invention is formed after the n ⁺ -type buried collector region 2 of the V-NPNTr and does not have to undergo severe drive-in. This is because upward diffusion to the layer 7 side was suppressed.

By suppressing these upward diffusions, the thickness of the n-type epitaxial layer 7 can be reduced by half as compared with the conventional one, whereby the high frequency characteristics of the complementary bipolar transistor can be greatly improved.

Second Embodiment Here, in the first embodiment, the region where the upper wiring is in direct contact with the substrate, that is, V-NPNT is used.
The collector extraction electrode was formed while leaving the first polysilicon layer also in the collector extraction region of r, and the phosphorus ion implantation step for forming the n ⁺ type collector extraction region was omitted. A manufacturing process of the complementary bipolar transistor IC according to the present embodiment will be described with reference to FIGS. However, the description of the parts common to the above manufacturing process will be briefly described.

In this process, first, as shown in FIG. 15, n ⁺ type buried collector region 2 is formed, n type buried isolation region 6 is formed, n type epitaxial layer 7 is formed, and element isolation is performed by the LOCOS method. The formation of the region 9 and the flattening of the substrate surface were performed in the same manner as in the first embodiment.
However, during the steps up to this point, the ion implantation for forming the collector extraction region (reference numeral 10C in FIG. 3) of the V-NPNTr is omitted once.

Next, as shown in FIG. 16, the channel stop layer 13iso of the V-NPNTr and the p ⁺ buried collector region 13C of the V-NPNPTr are formed by ion implantation of boron, and the SiO ₂ interlayer insulating film 14 is formed. First Embodiment: Full Surface Deposition and Patterning, First Surface Polysilicon Layer 15 Full Surface Deposition, and Introduction of p-Type Impurity into First Layer Polysilicon Layer 15 through Opening 17 of Resist Mask 16 I went the same way. However, the above SiO ₂
When patterning the interlayer insulating film 14, V-NPNTr is used.
A window is also opened in the collector extraction portion of the first polysilicon layer 15 to contact the n-type epitaxial layer 7.

Next, as shown in FIG. 17, another resist mask 41 was formed, and arsenic was ion-implanted through the opening 42. The ion implantation of the n-type impurity is V
-In addition to the base / emitter formation region of PNPTr, V-
The difference from the first embodiment is that it is also performed in the collector extraction region of the NPNTr.

Next, as shown in FIG. 18, the first polysilicon layer is patterned to form a base lead electrode 15Bn and a collector lead electrode 15C of the V-NPNTr.
n and V-PNPTr base extraction electrode 15Bp
A collector extraction electrode 15Cp was formed. Where V
The collector extraction electrode 15Cn of the -NPNTr is an extraction electrode not formed in the first embodiment.

Further, a SiO ₂ interlayer insulating film 20 was deposited on the entire surface of the substrate, and a resist mask 21 having openings 22 corresponding to the base / emitter forming regions of both bipolar transistors was formed thereon.

Next, as shown in FIG. 19, the emitter window is opened by dry etching, and the intrinsic base region 25I is formed.
B, 29IB, ion implantation for forming the pedestal regions 26, 30, ion-implantation for forming the pedestal regions 26, 30, covering the entire surface of the substrate with a sidewall forming SiO2 film, graft base regions 32GBn, 32GBp by annealing,
The collector extraction regions 43C and 32C were formed, and the side wall 31 was formed by etching back the SiO2 film.

Subsequently, as shown in FIG. 20, the second polysilicon layer is entirely deposited, impurities are introduced into the second polysilicon layer, and the emitter extraction electrode is formed by patterning the second polysilicon layer. Formation of 33En, 33Ep,
Contact holes were formed by patterning the SiO ₂ interlayer insulating film 20, and each electrode was formed by an Al-1% Si film-based multilayer film.

After this, the IC was completed through steps such as ordinary multilayer wiring and passivation.

Also in this process, the n-type epitaxial layer 7 is thinned by suppressing the upward diffusion of the n-type buried isolation region 6 and the p ⁺ -type buried collector region 13C.
I was able to do the same. The advantage of this process is V
Since the ion implantation step for forming the n ⁺ -type collector extraction region of -NPNTr can be omitted, one photomask is not required, and the step of forming a resist mask for ion implantation can be omitted.

Third Embodiment In this embodiment , a so-called double polysilicon base / emitter self-aligned structure in which a base region and an emitter region are formed in a self-aligned manner by impurity diffusion from two polysilicon layers Is adopted only for V-NPNTr,
The emitter region and the base region of the V-PNPTr have a so-called single polysilicon structure in which they are formed side by side by impurity diffusion from the second polysilicon layer. Third
A manufacturing process of the complementary bipolar transistor IC according to the embodiment will be described with reference to FIGS. 21 to 29. However, the description of the parts common to the above manufacturing process will be briefly described.

In this process, first, the formation of the p ⁺ type channel stop layer 13iso and the buried collector region 13C shown in FIG. 4 described above is performed in the same manner as in the first embodiment, and then the process shown in FIG. As shown, V-PNPT
A resist mask 51 having an opening 52 corresponding to the base / emitter forming region of r was formed, and arsenic was ion-implanted through the opening 52 to form an n-type base region 53B. The ion implantation conditions at this time are, for example, an ion acceleration energy of ²⁰ to 100 keV and a dose amount of 1 × 10 ^{13 -14} / cm ² .

Next, as shown in FIG. 22, SiO ₂
The entire surface of interlayer insulating film 14 was deposited and patterned, and the entire surface of first polysilicon layer 15 was deposited in the same manner as in the first embodiment. Then, boron (BF ₂ ⁺ ) was ion-implanted into the entire surface of the first polysilicon layer 15.

Next, as shown in FIG. 23, the first polysilicon layer 15 is patterned to form V-NPNT.
r base extraction electrode 15Bn, V-PNPTr collector extraction electrode 15Cp and emitter extraction electrode 15
Ep was formed. Subsequently, the SiO ₂ interlayer insulating film 20 was deposited on the entire surface of the substrate to form a resist mask 54 having an opening 55 corresponding to the base / emitter formation region of the V-NPNTr.

Next, as shown in FIG. 24, V-NP
A window is opened in the base / emitter formation region of NTr, and V
-Ion implantation of boron was performed to form the p-type intrinsic base region 25IB of -NPNTr. Further, in this state, phosphorus ion implantation (not shown) was continuously performed to form an n ⁺ -type pedestal region 26.

[0080] Next, as shown in FIG. 25, after fully coating a substrate by sidewall forming SiO ₂ film, an annealing, and the graft base region 32GBn the p ⁺ -type V-NPNTr, V The P + -type collector extraction region 32C of PNPTr was simultaneously formed. Further, the SiO ₂ film was etched back to form sidewalls 31.

Then, the SiO ₂ interlayer insulating films 20 and 1 are formed.
4, a resist mask 56 having an opening 57 was formed in order to open a contact hole facing the emitter formation region and the base extraction electrode formation region of the V-PNPTr.

Next, as shown in FIG. 26, the SiO ₂ interlayer insulating films 20 and 14 were dry-etched through the openings 57 to form contact holes.

Then, a second polysilicon layer 58 was deposited on the entire surface of the substrate. Further, in order to introduce a p-type impurity into a region of the second-layer polysilicon layer 58 which will later become an emitter extraction electrode (reference numeral 58Ep of FIG. 28) of the V-PNPTr, the second-layer polysilicon layer 58 is formed on the second-layer polysilicon layer 58. Opening 6
A resist mask 59 having 0 was formed and boron ion implantation was performed.

Next, as shown in FIG. 27, of the second polysilicon layer 58, an emitter extraction electrode (reference numeral 58En in FIG. 28) and V-NPNTr are formed later.
Base extraction electrode of PNPTr (reference numeral 58B in FIG. 28)
Arsenic was ion-implanted into the second polysilicon layer 58 in order to introduce an n-type impurity into the region to be p).

Next, as shown in FIG. 28, the second polysilicon layer 58 is patterned to form an emitter extraction electrode 58En of the V-NPNTr, and an emitter extraction electrode 58Ep and a base extraction electrode 58B of the V-PNPTr.
p was formed. Then, the entire surface of the substrate is covered with an SiO2 interlayer insulating film 63 and annealed to remove the n of V-NPNTr.
^{The +} type emitter region 36En, the p ⁺ type emitter region 36Ep of the V-PNPTr and the n ⁺ type graft base region 36GB were simultaneously formed.

Thereafter, as shown in FIG. 29, SiO 2
Opening of contact holes by dry etching of the _two interlayer insulating films 63, 20 and formation of each electrode by the Al-based laminated film were performed in the same manner as in the first embodiment.

Also in this process, the n-type epitaxial layer 7 is thinned by suppressing the upward diffusion of the n-type buried isolation region 6 and the p ⁺ -type buried collector region 13C.
I was able to do the same. The advantage of this process is V
-By not adopting the self-aligned structure in the base / emitter region of the PNPTr, the number of photomasks and the number of steps can be reduced.

Fourth Embodiment Here, a double polysilicon base / emitter
The self-aligned structure is adopted only for V-NPNTr, and V
The -PNPTr has a single polysilicon structure, and the emitter region and the collector extraction region are formed by impurity diffusion from the first polysilicon layer. A manufacturing process of such a complementary bipolar transistor IC is shown in FIG.
It will be described with reference to FIGS. The reference numerals in these drawings are partly common to the already-explained reference numerals, and the description of the parts common to the previous manufacturing process will be briefly described.

In this process, first, the steps up to formation of the p ⁺ type channel stop layer 13iso and the buried collector region 13C shown in FIG. 4 are performed in the same manner as in the first embodiment, and then the process shown in FIG. As shown, V-PNPT
A resist mask 51 having an opening 52 corresponding to the base / emitter forming region of r was formed, and phosphorus (P ⁺ ) was ion-implanted through the opening 52 to form an n-type base region 64B. Ion implantation conditions at this time are, for example, ion acceleration energy of 160 to 200 k.
The eV and dose amount were set to 1 × 10 ^13-14 / cm ² .

Next, as shown in FIG. 31, V-PN
A resist mask 65 having an opening 66 corresponding to the base extraction area of the PTr was formed, and arsenic (As ⁺ ) was ion-implanted through the opening 66 to form an n ⁺ -type base extraction area 67B. Ion implantation conditions at this time are, for example, ion acceleration energy of 20 to 10
0KeV, was dose of 1 × 10 ^15-16 / cm ^2.

Next, as shown in FIG. 32, SiO ₂
The entire surface of the interlayer insulating film 14 was deposited and patterned, and the entire surface of the first polysilicon layer 15 was deposited in the same manner as in Example 1. Then, boron (BF ₂ ⁺ ) was ion-implanted into the entire surface of the first polysilicon layer 15.

Next, as shown in FIG. 33, the first polysilicon layer 15 is patterned to form V-NPNT.
r base extraction electrode 15Bn, V-PNPTr collector extraction electrode 15Cp and emitter extraction electrode 15
Ep was formed. Subsequently, the SiO ₂ interlayer insulating film 20 was deposited on the entire surface of the substrate to form a resist mask 54 having an opening 55 corresponding to the base / emitter formation region of the V-NPNTr.

Next, as shown in FIG. 34, V-NP
A window is opened in the base / emitter formation region of NTr, and V
Ion implantation of boron (BF ₂ ⁺ ) was performed to form the p-type intrinsic base region 25IB of -NPNTr. Further, phosphorus (P ⁺ ) ions were continuously implanted in this state to form an n ⁺ type pedestal region 26.

[0094] Next, as shown in FIG. 35, after fully coating a substrate by sidewall forming SiO ₂ film, an annealing, V-NPNTr the p ⁺ -type graft base region 32GBn, and V -P ^{+ of} PNPTr
The collector-extracting region 32C of the type and the emitter region 32E of the p ⁺ type are formed simultaneously. Further, the SiO ₂ film was etched back to form sidewalls 31. Then, a second-layer polysilicon layer 58 was deposited on the entire surface of the substrate, and arsenic (As ⁺ ) was ion-implanted on the entire surface. This arsenic is for forming the emitter region of the V-NPNTr.

Next, as shown in FIG. 36, the second polysilicon layer 58 is patterned to form V-NPNT.
An emitter electrode 58En of r was formed. Subsequently, the entire surface of the base is covered with the SiO ₂ interlayer insulating film 63, and annealing is performed to diffuse arsenic from the emitter electrode 58En.
^{A +} type emitter region 36En was formed.

Thereafter, as shown in FIG. 37, SiO 2
Opening of contact holes by the soil of the _two interlayer insulating films 63, 20 and formation of each electrode by the Al-based laminated film were performed in the same manner as the first embodiment.

Although the present invention has been described with respect to the four embodiments, the present invention is not limited to these embodiments, and the design rule, each process condition, IC
The details of the configuration can be changed as appropriate.

[0098]

As is apparent from the above description, according to the present invention, it is possible to obtain a high degree of integration equivalent to the conventional one by adding a minimum number of steps to the conventional bipolar transistor manufacturing process. It is possible to fabricate a complementary bipolar transistor including a V-NPNTr having a high speed performance and a V-PNPTr having a higher speed performance than the conventional one. Therefore, for example, a high frequency LS represented by an amplifier / detector circuit for a video intermediate frequency of a UHF television tuner or a signal processing circuit for high speed communication or optical communication.
It is possible to manufacture I without significantly increasing the current cost.

[Brief description of drawings]

FIG. 1 is a plan view of a bipolar transistor manufacturing process according to a first embodiment of the present invention, wherein an n ⁺ type buried collector region of a V-NPNTr is formed on a p type Si substrate, and then high energy ion implantation is performed. V-PNPT
FIG. 3 is a schematic cross-sectional view showing a state in which an n-type embedded isolation region of r is formed.

FIG. 2 is a schematic cross-sectional view showing a state in which an n-type epitaxial layer is grown on the Si substrate of FIG. 1 and an element isolation region is formed by the LOCOS method.

FIG. 3 shows a V-NPNTr on the n-type epitaxial layer of FIG.
FIG. 3 is a schematic cross-sectional view showing a state in which a collector extraction region of is formed and the substrate surface is flattened.

4 is a plan view of the substrate of FIG.
FIG. 6 is a schematic cross-sectional view showing a state in which a channel stop layer of r and a buried collector region of V-PNPTr are formed.

FIG. 5 is a patterning of a SiO ₂ interlayer insulating film on the substrate of FIG. 4, a first polysilicon layer is entirely deposited, and a p-type impurity is selectively introduced into the first polysilicon layer. It is a typical sectional view showing a state.

FIG. 6 is a schematic cross-sectional view showing a state in which selective n-type impurity introduction is performed to another region of the first polysilicon layer in FIG.

FIG. 7 is a schematic view showing a state in which each extraction electrode is formed by patterning the first polysilicon layer in FIG. 6, the SiO ₂ interlayer insulating film is entirely deposited, and a resist mask for opening an emitter window is formed. FIG.

8 is a schematic cross-sectional view showing a state in which an emitter window is opened on the substrate of FIG. 7 and a base region and a pedestal region of V-NPNTr are formed by ion implantation.

9 is a plan view of the substrate of FIG.
It is a typical sectional view showing the state where the base field and pedestal field of PNPTr were formed.

10 is a schematic cross-sectional view showing a state in which a graft base region and a collector extraction region have been formed by impurity diffusion from each extraction electrode in FIG. 9, and a sidewall has been formed by etchback.

11 is a schematic cross-sectional view showing a state in which the second polysilicon layer is entirely deposited on the substrate of FIG. 10 and selective n-type impurity ion implantation is performed.

FIG. 12 is a plan view showing that the second polysilicon layer of FIG.
FIG. 5 is a schematic cross-sectional view showing a state in which after ion implantation of type impurities, patterning is performed to form an emitter extraction electrode, and an emitter region is formed by impurity diffusion.

FIG. 13 is a schematic cross-sectional view showing a state in which the SiO ₂ interlayer insulating film of FIG. 12 is patterned and the upper wiring is formed.

FIG. 14 is a complementary bipolar device manufactured according to the present invention.
It is an impurity profile figure of V-PNPTr in a transistor IC.

FIG. 15 is a view showing a process of manufacturing a complementary bipolar transistor according to a second embodiment of the present invention, in which an n ⁺ type buried collector region of a V-NPNTr is formed on a p-type Si substrate, and a V-PNPTr is formed. FIG. 5 is a schematic cross-sectional view showing a state in which an n-type buried isolation region is formed, an n-type epitaxial layer is grown, an element isolation region is formed, and a substrate is planarized in order.

16 is a plan view showing a step of forming a channel stop region and a buried collector region of V-PNPTr in the substrate of FIG. 15 and then patterning an SiO ₂ interlayer insulating film on the substrate; FIG. 6 is a schematic cross-sectional view showing a state in which a p-type impurity is selectively introduced into the first-layer polysilicon layer after the above.

FIG. 17 is a schematic cross-sectional view showing a state in which selective n-type impurity introduction is performed to another region of the first-layer polysilicon layer of FIG.

FIG. 18 is a schematic diagram showing a state in which each extraction electrode is formed by patterning the first polysilicon layer of FIG. 17, and is covered with an SiO ₂ interlayer insulating film, and a resist mask for opening an emitter window is formed. FIG.

FIG. 19 is a plan view showing a base region of FIG. 18 formed by ion implantation; a sidewall-forming SiO ₂ film is entirely deposited; and a graft base region and a collector extraction region are formed by impurity diffusion from each extraction electrode. SiO
FIG. 3 is a schematic cross-sectional view showing a state where sidewalls have been formed by etching back _two films.

FIG. 20 is a full-face deposition of a second polysilicon layer on the substrate of FIG. 19, formation of an emitter region by impurity diffusion from the second polysilicon layer, and formation of a contact hole by patterning a SiO ₂ interlayer insulating film. FIG. 3 is a schematic cross-sectional view showing a state in which the upper wiring and the upper wiring are formed.

FIG. 21 is a view showing a V-PNPTr forming region of a substrate on which a channel stop layer and a buried collector region of V-PNPTr have been formed in a manufacturing process of a complementary bipolar transistor according to a third embodiment of the present invention; FIG. 3 is a schematic cross-sectional view showing a state in which a base region is formed by selectively performing ion implantation.

22 is a schematic diagram showing a state in which the SiO ₂ interlayer insulating film is patterned, the first-layer polysilicon is entirely deposited, and p-type impurities are introduced into the first-polysilicon layer on the substrate of FIG. 21. FIG.

FIG. 23 is a schematic cross section showing a state in which each extraction electrode is formed by patterning the first polysilicon layer in FIG. 22, the entire surface of an SiO ₂ interlayer insulating film is deposited, and a resist mask for opening an emitter window is formed. It is a figure.

FIG. 24 is a schematic cross-sectional view showing a state in which an emitter window of V-NPNTr is opened on the substrate of FIG. 23 and an intrinsic base region and a pedestal region of V-NPNTr are formed by ion implantation.

FIG. 25 is an S for forming a sidewall on the substrate of FIG.
via iO ₂ film over the entire surface of the deposition, the formation of the graft base region and a collector take-out region by impurity diffusion from the extraction electrode, the formation of the SiO ₂ film is etched back by the side walls, and V-PNPTr emitter / base FIG. 6 is a schematic cross-sectional view showing a state where a resist mask for opening a window has been formed.

26 shows an emitter / base window opening of the V-PNPTr by etching the SiO ₂ interlayer insulating film of FIG. 25, the entire surface of the second polysilicon layer is deposited, and selective p-type impurities in the emitter formation region of the V-PNPTr. It is a typical sectional view showing the state where it is introducing.

27 is a schematic cross-sectional view showing a state where selective n-type impurity introduction is performed to another region of the second-layer polysilicon layer of FIG.

FIG. 28 is a patterning of the _second polysilicon layer of FIG. 27, a blanket deposition of an SiO ₂ interlayer insulating film, and an annealing process to form an emitter region of V-NPNTr and an emitter region and base region of V-PNPTr. It is a typical sectional view showing a state.

29 is a schematic cross-sectional view showing a state in which contact holes have been formed by patterning the SiO ₂ interlayer insulating film and upper layer wirings have been formed in FIG. 28.

FIG. 30 is a view showing a channel in the manufacturing process of the bipolar transistor according to the fourth embodiment of the present invention.
FIG. 6 is a schematic cross-sectional view showing a state in which a base region is formed by selectively ion-implanting n-type impurities into a V-PNPTr forming region of a substrate in which formation of a stop layer and a buried collector region of V-PNPTr is completed. is there.

FIG. 31 is a schematic cross-sectional view showing a state in which n-type impurity ions are selectively implanted into a V-PNPTr formation region to form a base extraction region.

32 is a state in which the SiO ₂ interlayer insulating film is patterned on the substrate of FIG. 31, the entire surface of the first polysilicon layer is deposited, and p-type impurity ions are implanted into the first polysilicon layer. It is a schematic cross-sectional view showing.

33 shows the formation of each extraction electrode by patterning the first polysilicon layer in FIG. 32, the overall deposition of an SiO ₂ interlayer insulating film, and the formation of a resist mask for opening an emitter window in the V-NPNTr formation region. It is a typical sectional view showing the state where it performed.

34 is a diagram of a V-NPNT formed by opening an emitter window of a V-NPNTr and implanting p-type impurity ions on the substrate of FIG. 33;
FIG. 4 is a schematic cross-sectional view showing a state in which an intrinsic base region of r and an pedestal region are formed by ion implantation of n-type impurities.

35 is an S for forming a side wall on the substrate of FIG.
After the entire surface of the iO ₂ film is deposited, the graft base region of the V-NPNTr and the V-NPNTr are diffused from each extraction electrode by diffusion of impurities.
-Formation of collector region and emitter region of PNPTr, formation of side wall by etching back of the above-mentioned side wall-forming SiO ₂ , second surface polysilicon layer deposition, n-type impurity on the second layer polysilicon layer FIG. 5 is a schematic cross-sectional view showing a state in which the ion implantation is performed.

FIG. 36 is a schematic cross-sectional view showing a state in which the second polysilicon layer in FIG. 35 is patterned, the SiO ₂ interlayer insulating film is entirely deposited, and the emitter region of the V-NPNTr is formed by annealing.

37 is a schematic cross-sectional view showing a state where contact holes have been formed by patterning the SiO ₂ interlayer insulating film in FIG. 36 and upper layer wirings have been formed.

FIG. 38 is a schematic cross-sectional view showing a configuration example of a complementary bipolar transistor manufactured by a conventional manufacturing method.

FIG. 39 is a conventional complementary bipolar transistor IC.
5 is an impurity profile diagram of V-PNPTr in FIG.

[Explanation of symbols]

1 p-type Si substrate 2 buried collector region (of V-NPNTr) 6 buried isolation region (of V-PNPTr) 7 n-type epitaxial layer 9 element isolation region 10C (V-NPNTr) collector extraction region 13iso channel stop region 13C Buried collector region (of V-PNPTr) 15Bn (V-NPNTr) base extraction electrode 15Bp, 58Bp (of V-PNPTr) base extraction electrode 15Cn (V-NPNTr) collector extraction electrode 15Cp (V-PNPTr) collector extraction electrode Electrode 15Ep (V-PNPTr) emitter extraction electrode 20 SiO2 interlayer insulating film 25IB (V-NPNTr) intrinsic base region 29IB (V-PNPTr) intrinsic base region 32GBn (V-NPNTr) graft base region 32GBp Graft base region (of V-PNPTr) 32C (V-PNPTr) collector extraction region 32E, 36Ep (V-PNPTr) emitter region 33En, 58En (V-NPNTr) emitter extraction electrode 33Ep, 58Ep (V-PNPTr) ) Emitter extraction electrode 36En (V-NPNTr) emitter region 36GB (V-PNPTr) graft base region 53B, 64B (V-PNPTr) base region 67B (V-PNPTr) base extraction region

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 29/73

Claims (12)

[Claims] 1. A semiconductor device comprising a vertical NPN transistor and a vertical PNP transistor formed on a p-type semiconductor substrate, wherein an n-type buried isolation region of the vertical PNP transistor is the vertical NPN transistor. formed by high energy ion implantation after the n ⁺ type buried collector region,
In addition, since the p ⁺ -type buried collector region of the vertical PNP transistor is formed after the n-type epitaxial layer thereabove and the element isolation region formed in the n-type epitaxial layer, the thickness of the n-type epitaxial layer is increased. A semiconductor device that is optimized to the minimum required. 2. A semiconductor substrate having a predetermined conductivity type,
A first conductivity type vertical bipolar transistor having a buried collector region of a conductivity type opposite to the semiconductor substrate; and a second having a buried isolation region of a conductivity type opposite to the semiconductor substrate and a buried collector region of the same conductivity type as the semiconductor substrate. A method of manufacturing a semiconductor device for forming a conductivity type vertical bipolar transistor, comprising: forming a buried collector region of the first conductivity type vertical bipolar transistor; and thereafter forming the second conductivity type vertical bipolar transistor. A method of manufacturing a semiconductor device, wherein the buried isolation region of a transistor is formed. 3. A method of manufacturing a semiconductor device according to claim 2, wherein the impurities are introduced into the buried isolation region of the vertical bipolar transistor of the second conductivity type by high energy ion implantation. 4. The graft base region of the first conductivity type vertical bipolar transistor and the collector extraction region of the second conductivity type vertical bipolar transistor are simultaneously formed by a common impurity introduction step. 2. The method for manufacturing a semiconductor device according to 2. 5. The graft base region of the first conductivity type vertical bipolar transistor and the collector extraction region and the emitter region of the second conductivity type vertical bipolar transistor are simultaneously formed by a common impurity introduction step. The method for manufacturing a semiconductor device according to claim 2, wherein the semiconductor device is formed. 6. The vertical bipolar transistor of the first conductivity type is a vertical NPN transistor, and the second bipolar transistor of the second conductivity type is a vertical NPN transistor.
Conductive vertical bipolar transistor is vertical PNP
The method of manufacturing a semiconductor device according to claim 2, wherein the semiconductor substrate is a transistor, and the semiconductor substrate is a p-type semiconductor substrate. 7. A semiconductor substrate having a predetermined conductivity type,
A first conductivity type vertical bipolar transistor having a buried collector region of a conductivity type opposite to the semiconductor substrate; and a second having a buried isolation region of a conductivity type opposite to the semiconductor substrate and a buried collector region of the same conductivity type as the semiconductor substrate. In a method of manufacturing a semiconductor device for forming a conductivity type vertical bipolar transistor, electrically separating the first conductivity type vertical bipolar transistor and the second conductivity type vertical bipolar transistor. A method for manufacturing a semiconductor device, wherein the buried collector region of the vertical bipolar transistor of the second conductivity type is formed after the element isolation region is formed. 8. The buried collector region of the second conductivity type vertical bipolar transistor is simultaneously formed in an impurity introduction step for forming a channel stop region of the first conductivity type vertical bipolar transistor. A method of manufacturing a semiconductor device according to claim 7. 9. The method of manufacturing a semiconductor device according to claim 8, wherein in the impurity introducing step, ion implantation is performed a plurality of times under conditions of different ion acceleration energies. 10. The vertical bipolar type of the first conductivity type
8. The method of manufacturing a semiconductor device according to claim 7, wherein the graft base region of the transistor and the collector extraction region of the vertical bipolar transistor of the second conductivity type are simultaneously formed by a common impurity introduction step. 11. A vertical bipolar transistor of the first conductivity type.
8. The method of manufacturing a semiconductor device according to claim 7, wherein the graft base region of the transistor and the collector extraction region and the emitter region of the second conductivity type vertical bipolar transistor are simultaneously formed by a common impurity introduction step. 12. A vertical bipolar transistor of the first conductivity type.
The transistor is a vertical NPN transistor, and the vertical bipolar transistor of the second conductivity type is a vertical PN transistor.
The method of manufacturing a semiconductor device according to claim 7, wherein the semiconductor substrate is a P-transistor, and the semiconductor substrate is a p-type semiconductor substrate.