JPH08148454A - Substrate polishing method - Google Patents

Substrate polishing method

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Publication number
JPH08148454A
JPH08148454A JP28775694A JP28775694A JPH08148454A JP H08148454 A JPH08148454 A JP H08148454A JP 28775694 A JP28775694 A JP 28775694A JP 28775694 A JP28775694 A JP 28775694A JP H08148454 A JPH08148454 A JP H08148454A
Authority
JP
Japan
Prior art keywords
polishing
substrate
polished
polishing liquid
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28775694A
Other languages
Japanese (ja)
Inventor
Takashi Nagano
隆史 永野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP28775694A priority Critical patent/JPH08148454A/en
Publication of JPH08148454A publication Critical patent/JPH08148454A/en
Pending legal-status Critical Current

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  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE: To provide a polishing method with which a polishing liquid can be spread to the center part of the surface to be polished when a substrate is polished using a polishing liquid, and the whole surface of the substrate can be polished excellently and uniformly. CONSTITUTION: When the surface 2 to be polished of the substrate 1 (semiconductor wafer, etc.) is polished using a polishing liquid, grooves 3, to be used for feeding of the polishing liquid to reach the center part of the surface 2 to be polished of the substrate, are formed on the surface 2 to be polished, on scribe lines, for example, and a polishing operation is conducted.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、基板の研磨方法に関す
る。本発明は、基板を研磨液を用いて研磨する工程を有
する各種の基板の研磨において使用することができる。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for polishing a substrate. INDUSTRIAL APPLICABILITY The present invention can be used in polishing various substrates having a step of polishing a substrate with a polishing liquid.

【0002】[0002]

【従来の技術及びその問題点】従来より、基板(例えば
半導体基板)を研磨する場合、研磨液を被研磨面に供給
してこれを用いて研磨が行われている。例えば、はり合
わせSOI基板を形成する場合に、はり合わせた一方の
基板から研磨を行う際に用いられる。
2. Description of the Related Art Conventionally, when a substrate (for example, a semiconductor substrate) is polished, a polishing liquid is supplied to the surface to be polished and the polishing is performed using this. For example, when forming a bonded SOI substrate, it is used for polishing from one bonded substrate.

【0003】従来の研磨方法においては、例えばフラッ
トな半導体ウェーハと、フラットな研磨パッド(クロ
ス)による従来の研磨方法では、ウェーハ中心まで十分
に研磨液が供給できず、研磨量が不均一になるという問
題がある。即ち、図4に示すように、ウェーハホルダー
5に把持されたウェーハ10を、研磨パッド6により研
磨する場合、ウェーハ10と研磨パッド6との間に研磨
液4を供給しようとしても、必ずしもウェーハ10の中
心までは十分に研磨液が供給できない。これは、ウェー
ハ10が大口径化するとき、特に顕著になる。
In the conventional polishing method, for example, in the conventional polishing method using a flat semiconductor wafer and a flat polishing pad (cross), the polishing liquid cannot be sufficiently supplied to the center of the wafer, and the polishing amount becomes uneven. There is a problem. That is, as shown in FIG. 4, when the wafer 10 held by the wafer holder 5 is polished by the polishing pad 6, even if an attempt is made to supply the polishing liquid 4 between the wafer 10 and the polishing pad 6, the wafer 10 is not always removed. The polishing liquid cannot be sufficiently supplied to the center of the. This becomes particularly remarkable when the wafer 10 has a large diameter.

【0004】上記問題を研磨パッド(クロス)に研磨液
を導く溝を形成して解消しようとする考え方もできる
が、この場合、溝形成時のパッドの加工歪みが、研磨均
一性及び研磨面粗さを悪化させるという問題がある。
It is possible to solve the above problem by forming a groove for guiding a polishing liquid to a polishing pad (cloth), but in this case, the processing strain of the pad at the time of forming the groove causes the polishing uniformity and the polishing surface roughness. There is a problem that it worsens.

【0005】更に、研磨パッドに溝があると、この溝に
被研磨基板であるウェーハ等のエッジが引っ掛かり、ウ
ェーハが割れたり、またはかけるという問題が生じる。
Further, if the polishing pad has a groove, there is a problem that the edge of a wafer or the like as a substrate to be polished is caught in the groove and the wafer is cracked or broken.

【0006】[0006]

【発明の目的】本発明は、上記従来技術の問題点を解決
して、基板を研磨液を用いて研磨する際、基板の被研磨
面の中心部にまで研磨液を十分に行き渡らせることがで
き、よって全面にわたる均一で良好な研磨を実現できる
基板の研磨方法を提供しようとするものである。
SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems of the prior art, and when polishing a substrate with a polishing liquid, the polishing liquid can be sufficiently spread to the center of the surface to be polished of the substrate. Therefore, it is an object of the present invention to provide a method for polishing a substrate that can realize uniform and excellent polishing over the entire surface.

【0007】[0007]

【目的を達成するための手段】本出願の請求項1の発明
は、基板を研磨液を用いて研磨する基板の研磨方法にお
いて、基板の被研磨面に、研磨液を基板の被研磨面の中
心部まで導く研磨液供給用の溝を形成して、研磨を行う
ことを特徴とする基板の研磨方法であって、これにより
上記目的を達成するものである。
According to the invention of claim 1 of the present application, in a method of polishing a substrate for polishing a substrate with a polishing liquid, the polishing liquid of the substrate is polished on the surface to be polished of the substrate. A method for polishing a substrate is characterized in that a groove for supplying a polishing liquid that leads to the central portion is formed and polishing is performed, thereby achieving the above object.

【0008】本出願の請求項2の発明は、基板が半導体
基板形成用の半導体ウェーハであることを特徴とする請
求項1に記載の基板の研磨方法であって、これにより上
記目的を達成するものである。
The invention according to claim 2 of the present application is the method for polishing a substrate according to claim 1, characterized in that the substrate is a semiconductor wafer for forming a semiconductor substrate. It is a thing.

【0009】本出願の請求項3の発明は、基板が、はり
合わせSOI基板形成用の基板であることを特徴とする
請求項1に記載の基板の研磨方法であって、これにより
上記目的を達成するものである。
The invention of claim 3 of the present application is the method for polishing a substrate according to claim 1, characterized in that the substrate is a substrate for forming a bonded SOI substrate. To achieve.

【0010】本出願の請求項4の発明は、半導体デバイ
ス製造の際のスクライブラインとなる個所に研磨液供給
用の溝を形成したことを特徴とする請求項2または3に
記載の基板の研磨方法であって、これにより上記目的を
達成するものである。
The invention according to claim 4 of the present application is characterized in that a groove for supplying a polishing liquid is formed at a position which becomes a scribe line at the time of manufacturing a semiconductor device. A method for achieving the above object.

【0011】本発明の構成について、後記詳述する本発
明の一実施例を示す図1の例示を用いて説明すると、次
のとおりである。
The structure of the present invention will be described below with reference to the example of FIG. 1 showing an embodiment of the present invention which will be described later in detail.

【0012】図1は、被研磨基板1(図示例では半導体
ウェーハ)の被研磨表面2の平面図である。本発明は、
基板1を研磨液を用いて研磨する際、基板1の被研磨面
2(図1に見えている表面)に、研磨液を基板の被研磨
面2の中心部まで導く研磨液供給用の溝3を形成して、
研磨を行う構成としたものである。
FIG. 1 is a plan view of a surface to be polished 2 of a substrate to be polished 1 (semiconductor wafer in the illustrated example). The present invention
When polishing the substrate 1 with the polishing liquid, a groove for supplying the polishing liquid to the surface 2 to be polished of the substrate 1 (the surface visible in FIG. 1) that guides the polishing liquid to the central portion of the surface 2 to be polished of the substrate. Form 3
It is configured to perform polishing.

【0013】図示例では、溝3は、基板1の表面(被研
磨面2)に縦横に全体を多数の方形で区切るように形成
されている。
In the illustrated example, the groove 3 is formed on the surface of the substrate 1 (the surface 2 to be polished) so as to divide the whole vertically and horizontally into a large number of squares.

【0014】なお、後に示す実施例では、SOI基板形
成用研磨、層間平坦化研磨、ベアSi鏡面研磨について
本発明を適用した各具体例を示すが、本発明はこれらに
限られず、種々の基板の研磨の際に用いることができる
ことは言うまでもない。
In the examples described later, specific examples of applying the present invention to polishing for SOI substrate formation, interlayer flattening polishing, and bare Si mirror polishing are shown, but the present invention is not limited to these, and various substrates can be used. Needless to say, it can be used for polishing.

【0015】[0015]

【作用】上記のように、本発明においては、基板1の被
研磨面2に、研磨液を基板1の被研磨面2の中心部まで
導く研磨液供給用の溝3を形成したので、研磨の際、図
2に示すように、研磨液4を用いて例えばホルダー5に
支持された基板1を研磨パッド6により研磨する場合
も、従来は研磨液を供給しにくかった基板1の被研磨面
2の中心まで十分に研磨液4を供給できる。よって、研
磨均一性が向上し、良好な研磨が達成できる。
As described above, in the present invention, the surface 3 to be polished of the substrate 1 is provided with the groove 3 for supplying the polishing liquid for guiding the polishing liquid to the central portion of the surface 2 to be polished of the substrate 1. At this time, as shown in FIG. 2, even when the polishing pad 6 is used to polish the substrate 1 supported by the holder 5 using the polishing liquid 4, it is difficult to supply the polishing liquid in the prior art. The polishing liquid 4 can be sufficiently supplied to the center of 2. Therefore, polishing uniformity is improved, and good polishing can be achieved.

【0016】[0016]

【実施例】以下本発明の実施例について、詳述する。但
し、当然のことではあるが、本発明は以下の実施例によ
り限定を受けるものではない。
EXAMPLES Examples of the present invention will be described in detail below. However, as a matter of course, the present invention is not limited to the following examples.

【0017】実施例1 この実施例は、本発明を、はり合わせSOI基板の作製
プロセスにおける選択研磨工程に適用したものである。
Example 1 In this example, the present invention is applied to a selective polishing step in a manufacturing process of a bonded SOI substrate.

【0018】一般に、はり合わせSOI基板の作製は、
ウェーハはり合わせ、研削(大まかな研磨)、選
択研磨(精密な研磨)の工程をとるが、本実施例におい
てはこの一連の工程における研削終了後に、スクライブ
ライン上に図1に示すように研磨液供給用の溝3を形成
する。
In general, a bonded SOI substrate is manufactured by
Wafer bonding, grinding (rough polishing), and selective polishing (precision polishing) are performed, but in this embodiment, after completion of the grinding in this series of steps, a polishing liquid is provided on the scribe line as shown in FIG. The groove 3 for supply is formed.

【0019】従来より行われているはり合わせ・研磨技
術によるSOI基板の形成について説明すると次の通り
である。図5(a)に示すように、シリコン基板11
(一般に高平坦度シリコンウェーハを用いる。これを基
板Aとする)の一方のがわの面をフォトリソグラフィー
技術及びエッチング技術等を用いてパターニングし、凹
ー段差を形成する。更にこの凹部段差を有する面にSi
2 膜を形成すること等によって絶縁部12を形成する
(図5(b))。更にの絶縁部12上に接合膜13とし
てポリシリコン膜を形成する(図5(c))。
The formation of the SOI substrate by the conventional bonding / polishing technique will be described below. As shown in FIG. 5A, the silicon substrate 11
(In general, a high flatness silicon wafer is used. This is referred to as a substrate A). One side of the gutter is patterned by using a photolithography technique and an etching technique to form a concave step. Further, Si is formed on the surface having the stepped portion of the recess.
The insulating portion 12 is formed by forming an O 2 film or the like (FIG. 5B). Further, a polysilicon film is formed as the bonding film 13 on the insulating portion 12 (FIG. 5C).

【0020】次に、ポリシリコン膜から成る接合膜13
の表面を平坦化研磨し、高度な平滑な面とする(図5
(d))。
Next, the bonding film 13 made of a polysilicon film.
The surface of is polished and flattened to a highly smooth surface (Fig. 5).
(D)).

【0021】この接合膜13の研磨面に、別の基板14
(これを基板Bとする)を密着させる。密圧着によって
両面は接合し、この結果図6(a)に示すようなはり合
わせ接合構造が得られる。
On the polished surface of the bonding film 13, another substrate 14 is attached.
(This is the substrate B) is brought into close contact. Both surfaces are joined by the tight compression bonding, and as a result, a bonded joint structure as shown in FIG. 6A is obtained.

【0022】次に、側周部の面取り後、基板1の表面
を、絶縁部12が露出する前まで研削する(図6
(b))。
Next, after chamfering the side peripheral portion, the surface of the substrate 1 is ground until the insulating portion 12 is exposed (FIG. 6).
(B)).

【0023】図6(b)は、図6(a)と上下が逆にな
っているが、これは、面取りや研削のため、上下を逆に
して基板11を上側にしたためである。
6B is upside down from FIG. 6A, but this is because the substrate 11 is turned upside down for the purpose of chamfering and grinding, and the substrate 11 is placed on the upper side.

【0024】次いで、選択研磨を行う。ここでは、丁度
絶縁部12が露出するまで、精密な仕上げの研磨で行
う。これにより、図6(c)に示すように、凹凸のある
絶縁部12に囲まれて、この絶縁部12上にシリコン部
分10′(素子形成部となる)が存在する構造が得られ
る。
Next, selective polishing is performed. Here, precise finishing polishing is performed until the insulating portion 12 is just exposed. As a result, as shown in FIG. 6C, a structure is obtained in which the silicon portion 10 ′ (which serves as an element forming portion) is surrounded by the insulating portion 12 having irregularities and is present on the insulating portion 12.

【0025】本実施例は、上記のようなはり合わせ研磨
法によるSOI基板作成技術において、その選択研磨、
即ち図6(b)の構造を研磨して図6(c)の構造を得
るときに本発明を用いて具体化したものである。
In this embodiment, in the SOI substrate manufacturing technique by the above-mentioned laminating and polishing method, the selective polishing,
That is, the present invention is embodied when the structure of FIG. 6 (b) is polished to obtain the structure of FIG. 6 (c).

【0026】本実施例では、図3に示すように、Si基
板11を大まかに研削した後に、接合して一体となって
いるSi基板11、絶縁膜12(SiO2 )、接合膜1
3(Poly−Si)、台となる基板14全体を被研磨
基板1とし、Si基板11の側を被研磨面2としてここ
を精密に研磨する工程に入る前に、研磨液供給用の溝3
を、スクライブラインとなる部分に形成する。
In this embodiment, as shown in FIG. 3, the Si substrate 11 is roughly ground and then joined to form an integral Si substrate 11, an insulating film 12 (SiO 2 ), and a bonding film 1.
3 (Poly-Si), the entire substrate 14 to be the base is used as the substrate 1 to be polished, and the Si substrate 11 side is used as the surface 2 to be polished.
Is formed in the portion that will be the scribe line.

【0027】本実施例においては、図1の平面図に示す
ように、被研磨基板1であるSOI基板形成用半導体ウ
ェーハの被研磨表面2に、研磨液を基板の被研磨面2の
中心部まで導く研磨液供給用の溝3を形成して、研磨を
行う構成とした。
In this embodiment, as shown in the plan view of FIG. 1, a polishing liquid is applied to a surface to be polished 2 of a semiconductor wafer for forming an SOI substrate, which is a substrate to be polished 1, at a central portion of the surface to be polished 2 of the substrate. A groove 3 for supplying a polishing liquid for leading to is formed to perform polishing.

【0028】研磨液供給用の溝3は、基板1の表面(被
研磨面2)に縦横に全体を多数の方形で区切るように形
成されているが、これはデバイス形成の際のスクライブ
ラインとなる部分にこの溝3を形成して、各デバイスチ
ップへの影響を抑制するようにしたためである。
The groove 3 for supplying the polishing liquid is formed on the surface of the substrate 1 (the surface to be polished 2) so as to divide the whole vertically and horizontally into a large number of squares, which serve as scribe lines for device formation. This is because the groove 3 is formed in the portion to be formed so as to suppress the influence on each device chip.

【0029】ここで被研磨液供給用の溝3の形成方法
は、例えば、フォトレジストパターニングによるマスク
形成及びドライエッチングの工程で行うことができる。
Here, the method of forming the groove 3 for supplying the polishing liquid can be performed, for example, in the steps of mask formation by photoresist patterning and dry etching.

【0030】あるいは、溝3の形成方法はこれに限定さ
れず、その他の適宜の手段を採用でき、例えばフォトレ
ジストパターニング後、ウェットエッチングによって形
成してもよい。
Alternatively, the method of forming the groove 3 is not limited to this, and other appropriate means can be adopted, for example, it may be formed by wet etching after photoresist patterning.

【0031】上記被研磨基板1(被研磨ウェーハ)を研
磨することで、図2に示すように、ホルダー5に把持さ
れた被研磨基板1であるウェーハを研磨パッド6により
研磨する場合に、従来では供給しにくかったウェーハの
中心まで十分に研磨液4を供給でき、研磨均一性が向上
する。
By polishing the substrate 1 to be polished (wafer to be polished), as shown in FIG. 2, when a wafer, which is the substrate 1 to be polished, held by a holder 5 is polished by a polishing pad 6, a conventional method is used. Then, the polishing liquid 4 can be sufficiently supplied to the center of the wafer, which was difficult to supply, and the polishing uniformity is improved.

【0032】本実施例において、研磨液供給用の溝3の
深さ、広さは、研磨液4を供給し得るとともに、洗浄に
より研磨液4を除去し得る範囲で、十分浅い方がウェー
ハの強度が高くて望ましく、かつ十分狭い方がチップの
収率が高く望ましい。
In this embodiment, the depth and width of the groove 3 for supplying the polishing liquid is such that the polishing liquid 4 can be supplied and the polishing liquid 4 can be removed by cleaning, and the shallower the wafer High strength is desirable, and sufficiently narrow is desirable because the yield of chips is high.

【0033】即ち本実施例では、ウェーハ当たりのチッ
プ収率の低下を避けるため、溝の広さを必要最小限とす
るように構成した。
That is, in this embodiment, in order to avoid a decrease in the chip yield per wafer, the groove width is set to the minimum necessary.

【0034】また、デバイス作成時に堆積する種々の膜
により、形成した溝3が埋め込まれないよう、溝は十分
に深く、かつかかる埋め込みが生じない程度に広い溝を
形成するようにした。
Further, various films deposited at the time of making the device are formed so that the formed groove 3 is not deeply filled and the groove is wide enough to prevent such filling.

【0035】本実施例において、研磨装置、研磨条件等
は、従来の研磨手段をそのまま用いればよい。
In this embodiment, conventional polishing means may be used as they are as the polishing apparatus, polishing conditions and the like.

【0036】但し、上記溝3の形成領域は、スクライブ
ライン上に限定されず、ウェーハ中心まで研磨液を供給
できる領域であればよい。
However, the region where the groove 3 is formed is not limited to the scribe line and may be any region that can supply the polishing liquid to the center of the wafer.

【0037】本実施例によれば、被研磨基板1であるウ
ェーハの被研磨面2の中心部まで十分に研磨液が供給で
き、研磨均一性が向上する。また、研磨パッド6(クロ
ス)の平坦性を保つことができ、均一性、面粗さを悪化
させない。かつ、被研磨基板1であるウェーハの割れや
かけを誘発することもない。本実施例は、従来の研磨装
置、研磨条件にて対応可能である。また、ウェーハが大
口径化しても、それに伴う研磨均一性の悪化がないとい
う大きな利点をもつ。
According to this embodiment, the polishing liquid can be sufficiently supplied to the central portion of the surface to be polished 2 of the wafer to be polished 1 and the polishing uniformity is improved. Further, the flatness of the polishing pad 6 (cloth) can be maintained, and the uniformity and surface roughness are not deteriorated. Moreover, it does not induce cracking or chipping of the wafer to be polished 1. This embodiment can be applied with a conventional polishing apparatus and polishing conditions. Further, even if the diameter of the wafer is increased, there is a great advantage that polishing uniformity is not deteriorated.

【0038】実施例2 上記実施例1は、はり合わせSOI基板の研磨に本発明
を適用したが、この実施例では、層間平坦化CMP(化
学的機械研磨)に本発明を適用した。
Example 2 In Example 1, the present invention was applied to polishing a bonded SOI substrate, but in this Example, the present invention was applied to interlayer planarization CMP (chemical mechanical polishing).

【0039】本実施例では、下地段差を有するシリコン
ウェーハに平坦化膜としてSiO2系の膜を形成し、こ
れを例えばアルカリ系の化学研磨液を用いてCMPし、
平坦化を行う際、実施例1と同様に研磨液供給用の溝を
形成して、研磨を行った。
In this embodiment, a SiO 2 film is formed as a flattening film on a silicon wafer having an underlying step, and this is CMP using, for example, an alkaline chemical polishing liquid,
At the time of flattening, a groove for supplying a polishing liquid was formed and polishing was performed in the same manner as in Example 1.

【0040】本実施例によっても、十分な被研磨面への
研磨液の供給が達成され、均一な研磨が実現された。
Also in this embodiment, sufficient supply of the polishing liquid to the surface to be polished was achieved, and uniform polishing was realized.

【0041】実施例3 この実施例は、ベアSiウェーハの鏡面研磨に本発明を
適用した例である。
Example 3 This example is an example in which the present invention is applied to mirror polishing a bare Si wafer.

【0042】本実施例では、ベアSiウェーハの被研磨
面に研磨液供給用の溝を形成し、上記各例と同様に研磨
を行った。
In this example, a groove for supplying a polishing liquid was formed on the surface to be polished of a bare Si wafer, and polishing was carried out in the same manner as in each of the above examples.

【0043】本実施例によっても、十分な被研磨面への
研磨液の供給が達成され、均一な鏡面研磨が実現され
た。
Also in this embodiment, sufficient supply of the polishing liquid to the surface to be polished was achieved, and uniform mirror polishing was realized.

【0044】[0044]

【発明の効果】上述したように、本発明によれば、基板
を研磨液を用いて研磨する際、基板の被研磨面の中心部
にまで研磨液を十分に行き渡らせることができ、よって
全面にわたる均一で良好な研磨を実現できる基板の研磨
方法を提供できた。
As described above, according to the present invention, when the substrate is polished with the polishing liquid, the polishing liquid can be sufficiently spread to the central portion of the surface to be polished of the substrate, so that the entire surface can be covered. It was possible to provide a method for polishing a substrate capable of achieving uniform and excellent polishing over a range.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例1の平面図であり、基板の被研磨面への
溝の形成を示す図である。
FIG. 1 is a plan view of Example 1, showing formation of grooves on a surface to be polished of a substrate.

【図2】実施例1の作用説明図である。FIG. 2 is an explanatory view of the operation of the first embodiment.

【図3】実施例1の被研磨基板(SOI基板)の要部拡
大断面図である。
FIG. 3 is an enlarged cross-sectional view of a main part of a substrate to be polished (SOI substrate) of Example 1.

【図4】従来技術及びその問題点を示す図である。FIG. 4 is a diagram showing a conventional technique and its problems.

【図5】背景技術を示す図であり、SOI基板の一般的
な製造プロセスを示す図である(1)。
FIG. 5 is a diagram showing a background art and a diagram showing a general manufacturing process of an SOI substrate (1).

【図6】背景技術を示す図であり、SOI基板の一般的
な製造プロセスを示す図である(2)。
FIG. 6 is a diagram showing a background art and a diagram showing a general manufacturing process of an SOI substrate (2).

【符号の説明】[Explanation of symbols]

1 基板 11 SOI基板形成用Si基板 12 SOI基板形成用絶縁膜(SiO2 ) 13 SOI基板形成用接合膜(Poly−Si) 14 支持基板(Siウェーハ) 2 被研磨面 3 研磨液供給用溝 4 研磨液 5 (ウェーハ)ホルダー 6 研磨パッド1 Substrate 11 Si Substrate Forming Si Substrate 12 SOI Substrate Forming Insulating Film (SiO 2 ) 13 SOI Substrate Forming Bonding Film (Poly-Si) 14 Support Substrate (Si Wafer) 2 Polished Surface 3 Polishing Liquid Supply Groove 4 Polishing liquid 5 (Wafer) holder 6 Polishing pad

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/301 27/12 B ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location H01L 21/301 27/12 B

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】基板を研磨液を用いて研磨する基板の研磨
方法において、 基板の被研磨面に、研磨液を基板の被研磨面の中心部ま
で導く研磨液供給用の溝を形成して、研磨を行うことを
特徴とする基板の研磨方法。
1. A method for polishing a substrate, which comprises polishing a substrate with a polishing liquid, wherein a groove for supplying a polishing liquid is formed on the surface to be polished of the substrate for guiding the polishing liquid to the center of the surface to be polished of the substrate. And a method for polishing a substrate, which comprises performing polishing.
【請求項2】基板が半導体基板形成用の半導体ウェーハ
であることを特徴とする請求項1に記載の基板の研磨方
法。
2. The method for polishing a substrate according to claim 1, wherein the substrate is a semiconductor wafer for forming a semiconductor substrate.
【請求項3】基板が、はり合わせSOI基板形成用の基
板であることを特徴とする請求項1に記載の基板の研磨
方法。
3. The method for polishing a substrate according to claim 1, wherein the substrate is a substrate for forming a bonded SOI substrate.
【請求項4】半導体デバイス製造の際のスクライブライ
ンとなる個所に研磨液供給用の溝を形成したことを特徴
とする請求項2または3に記載の基板の研磨方法。
4. The method for polishing a substrate according to claim 2 or 3, wherein a groove for supplying a polishing liquid is formed at a position which becomes a scribe line at the time of manufacturing a semiconductor device.
JP28775694A 1994-11-22 1994-11-22 Substrate polishing method Pending JPH08148454A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28775694A JPH08148454A (en) 1994-11-22 1994-11-22 Substrate polishing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28775694A JPH08148454A (en) 1994-11-22 1994-11-22 Substrate polishing method

Publications (1)

Publication Number Publication Date
JPH08148454A true JPH08148454A (en) 1996-06-07

Family

ID=17721356

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28775694A Pending JPH08148454A (en) 1994-11-22 1994-11-22 Substrate polishing method

Country Status (1)

Country Link
JP (1) JPH08148454A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019119006A (en) * 2018-01-05 2019-07-22 株式会社ディスコ Processing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019119006A (en) * 2018-01-05 2019-07-22 株式会社ディスコ Processing method

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