JPH08148408A - Exposure method and manufacture of semiconductor integrated circuit device using the same - Google Patents

Abstract

PURPOSE: To eliminate the restriction of a resist material in an exposure process by obviating an unnecessary pattern generated due to the phase difference of lights in the case of transferring an independent linear pattern by using a first mask having a phase shifter by the exposure process with a second mask. CONSTITUTION: A first mask M for forming a resist pattern is provided. Three rectangular light transmission regions T which are extended in parallel are formed on the mask M. A second mask M for forming a resist pattern 14a is provided. A light shielding region S of a square shape is formed on the mask M. A resist pattern 14 is formed by using such first mask and second mask. Thus, after a semiconductor wafer is covered with a positive resist, it is exposed continuously at the timing in the state that the relative positions of the first and second mask M are brought into coincidence.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure method and a semiconductor integrated circuit device manufacturing technique using the same, and more particularly to an exposure method using a phase shift mask that gives a phase difference to exposure light and a semiconductor integrated circuit using the same. The present invention relates to a technique effectively applied to a method for manufacturing a circuit device.

[0002]

2. Description of the Related Art As semiconductor devices are mounted at high density, circuit miniaturization has advanced to a high degree, and the design rules for circuit elements and wirings have entered the submicron range. Therefore, the wavelength of the light used for exposure is the i-line (wavelength 36
5 nm).

However, in a photolithography process for transferring an integrated circuit pattern on a photomask (hereinafter, simply referred to as a mask) onto a semiconductor wafer by using light in such a wavelength range, deterioration of pattern transfer accuracy is a serious problem. Become.

Here, FIG. 22 is a sectional view showing the structure of an ordinary mask not using the phase shift technique, and FIG. 23 is a characteristic diagram showing the light intensity distribution of the light transmitted through the mask.

As shown in FIG. 22, a mask substrate 50, which constitutes a mask that does not require miniaturization, is made of a transparent material such as glass, and has light transmitting regions P1 and P2 on one surface thereof.
And a light blocking area N are formed. Light transmission area P1, P
Reference numeral 2 is a region capable of transmitting light. The light-shielding region N is a region which is covered with the metal film 51 made of chromium or the like and can block the transmission of light.

In the mask having such a structure, since the two lights transmitted through the pair of light transmitting regions P1 and P2 sandwiching the light shielding region N have the same phase, the two lights are
On the semiconductor wafer, they act so as to interfere with each other and strengthen each other at the boundary between these two lights.

Therefore, when the width of the light-shielding region N is narrower than the exposure wavelength, the contrast of the projected image of the pattern on the semiconductor wafer decreases as shown in FIG. 23, and the depth of focus becomes shallow, resulting in a fine pattern. Then, it is understood that the transfer accuracy is significantly lowered, and the exposure cannot be performed in a state where the patterns are well separated.

As means for solving such a problem, attention has been paid to a phase shift technique for preventing the contrast of a projected image from being lowered by manipulating the phase of light passing through a mask.

This system is, for example, as shown in FIG.
A phase shifter whose film thickness is adjusted so that the phases of the two lights immediately after passing through the pair of light transmitting regions P1 and P2 are inverted to one of the pair of light transmitting regions P1 and P2 sandwiching the light shielding region N (for example, This is a method of using a mask having a structure in which a transparent glass film) 52 is provided.

As a result, as shown in FIG. 25, on the semiconductor wafer, the two lights interfere with each other at their boundaries and weaken each other, so that the contrast of the projected images of the patterns is greatly improved, and the mutual patterns are well formed. It becomes possible to perform exposure in the state of being separated. Thus, it can be seen that the phase shift mask is a mask suitable for miniaturization of semiconductor integrated circuits.

Further, for example, Japanese Unexamined Patent Publication No. 4-127150 discloses restrictions on a phase shift mask and a photoresist process. For each manufacturing process of a semiconductor integrated circuit device, a negative photoresist (hereinafter, referred to as a negative photoresist) is used. A method is proposed in which a negative resist) and a positive photoresist (hereinafter simply referred to as positive resist) are used separately.

That is, in the manufacturing process of a semiconductor integrated circuit device, a positive resist having characteristics such as high resolution and little influence of foreign matter has been used as a photoresist (hereinafter simply referred to as resist). When an isolated linear pattern such as a wiring pattern is transferred to a positive resist using the phase shift technique, an unnecessary pattern is originally formed in the area where the pattern should not be formed due to the phase difference of light. Since the problem of being formed occurs,
In this case, a negative resist is used.

On the other hand, such a problem that an unnecessary pattern is formed due to the phase difference of light occurs also when an isolated opening pattern such as a connection hole is transferred to a negative resist. In some cases, a positive type resist is used.

[0014]

However, Japanese Unexamined Patent Application Publication No.
The phase shift technique described in Japanese Patent Publication No. 127150 has a problem of restriction of the photoresist material that a negative resist and a positive resist must be used separately for each manufacturing process of a semiconductor integrated circuit.

It is an object of the present invention to provide a technique capable of eliminating the limitation of the photoresist material in the exposure process using the phase shift technique.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0017]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

That is, in the exposure method of the present invention, a phase shifter provided at a predetermined position in the light transmission region of the mask causes a phase difference in the transmitted light to form a plurality of patterns on the sample at intervals shorter than the exposure wavelength. When transferring, after depositing a positive resist on the sample, a light-shielding region is provided in a region corresponding to at least one set of resist patterns having an interval shorter than the exposure wavelength to be left on the sample, and a part of the periphery thereof is provided. A first mask having a phase shifter for reversing the phase of transmitted light in one of the light transmitting regions sandwiching the light shielding region among the formed light transmitting regions, and at least the light shielding region of the first mask and its surroundings. In a state where the relative position to the second mask having a light shielding region that covers a part of the light transmitting region is matched, the exposure process is performed continuously in terms of time.

Further, in the exposure method of the present invention, a plurality of shadows of the interference of transmitted light at the edge portion of the phase shifter provided at a predetermined position of the light transmission region on the mask are formed on the sample at intervals shorter than the exposure wavelength. When transferring the pattern, the negative shift resist is applied on the sample, and then the phase shifter is arranged to invert the phase of the transmitted light to a region corresponding to the resist pattern having a dimension shorter than the exposure wavelength opened on the sample. Of the phase shifter and a second mask having a light-shielding region that covers a part of the orthogonal region of the edge of the phase shifter are aligned with each other in terms of time. The exposure process is continuously performed.

[0020]

According to the above-described exposure method of the present invention, a positive type resist is formed by using the first mask having a phase shifter by exposing the first mask and the second mask by superposing them separately. Since an unnecessary pattern caused by the phase difference of light when transferring an isolated linear pattern such as a wiring pattern can be eliminated by the exposure process using the second mask, the phase shift technique is used. It is possible to eliminate the restriction on the resist material in the exposure process.

Further, according to the above-described exposure method of the present invention, the first mask and the second mask are separately superposed and exposed, so that the negative mask is formed by using the first mask having the phase shifter. Unnecessary patterns caused by the phase difference of light when transferring an isolated opening pattern such as a connection hole pattern to a resist can be eliminated by the exposure process using the second mask. It is possible to eliminate the restriction of the resist material in the used exposure processing.

[0022]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a flow chart showing an exposure method according to the present invention, FIG. 2 is a plan view showing an example of a circuit pattern to be realized in the embodiment of the present invention, and FIG. 3 is a mask for obtaining the circuit pattern of FIG. 4 is an explanatory view illustrating the processing contents of steps 104 and 114 to 117 in FIG. 1, and FIG. 5 is an explanatory view showing other mask combinations corresponding to the circuit pattern of FIG. 6 is a plan view showing a second circuit pattern example, FIG. 7 is an explanatory view showing a combination of masks for obtaining the circuit pattern of FIG. 6, and FIG. 8 is a general exposure method using a negative photoresist. 9 is an explanatory view for explaining, FIG. 9 is an explanatory view for explaining a normal exposure method using a positive photoresist, and FIG. 10 is for forming a predetermined circuit pattern with the positive photoresist. FIG. 11 is an explanatory view showing a combination of masks, FIG. 11 is an explanatory view showing a combination of masks for forming the circuit pattern of FIG. 2 with a positive photoresist, and FIG. 12 is a sectional view showing a structure of a phase shift mask. 14 is a plan view of an essential part of the phase shift mask of FIG.
15 is an explanatory view showing a combination of masks for forming a predetermined circuit pattern with a negative photoresist, FIG.
16 is an explanatory view showing a combination of masks for forming a predetermined circuit pattern with a negative photoresist, FIG.
Is an explanatory view of the amplitude and intensity of light projected on the surface of a semiconductor wafer through a projection optical system, FIG. 17 is an overall plan view of the phase shift mask of this embodiment, and FIG. 18 is manufacturing of the phase shift mask according to the present invention. FIG. 19 is an explanatory diagram for explaining the method, FIG. 19 is an explanatory diagram for explaining the configuration of the optical system in the reduction projection exposure apparatus to which the present invention is applied, and FIG. 20 is another reduction projection exposure apparatus to which the present invention is applied. 21 is an explanatory view for explaining the configuration of the optical system in FIG. 21, and FIG. 21 is a plan view of the semiconductor wafer for explaining the exposure processing of the present embodiment.

In this embodiment, as shown in FIG.
Exposure is performed by dividing the mask M into two. That is,
Exposure is performed using the first mask M as shown in FIG. 3A and the second mask M as shown in FIG. 3B. Here, a shadow is generated in a portion where the phase of the transmitted light is in the opposite phase in one transmission region of FIG. 3B, and the pattern is formed by overlapping and exposing the portion of FIG. Prevents shredding.

Further, by doing so, it is possible to prevent the pattern fragmentation due to the following reasons. That is, when the mask M having the pattern as shown in FIG. 2 is created by using the phase shift technique as shown in FIG. 24, according to the known technique, the light transmission corresponding to the three patterns X1, X2 and X3 is transmitted. Phase shifters are provided in X1 and X3 of the region T (the white portion in the figure. The shaded portion is the light shielding region S). However, if the width and interval of the pattern are narrow, X1 and X3 are provided.
It is also possible to prevent the phenomenon that the light-shielding portion is not formed and the patterns are short-circuited because the vertical portions in which 2 are close to each other have the same phase.

The light shielding region S of the mask M is formed by depositing the chrome film 2 on the mask substrate 1. Further, on the predetermined light transmitting region T of the mask M, a phase shift film 3 is applied as a phase shifter for shifting the phase of light.

By the way, the use of a mask by such a combination has to rely on an automatic design by a computer because an actual circuit pattern is complicated. The specific example of the processing is shown in the flowchart of FIG.
The exposure method of this embodiment will be described below with reference to FIG. 1 and other drawings.

The following embodiments exemplify a case where at least three continuous patterns are formed close to each other by projection exposure at intervals shorter than the exposure wavelength.

The process of FIG. 1 will be briefly described. First, a photoresist pattern is formed using, for example, silicon (S
i) When forming on a semiconductor wafer made of a single crystal, at least one of the above three patterns is divided at a predetermined interval in the x direction or the y direction, and is grouped including other patterns. Corresponding to this grouping, a phase shift mask for sequentially inverting the phase of light transmitted on the mask at predetermined intervals is formed.

Subsequently, pattern data of an area covering the divided boundary area is created, and a light-shielding mask is formed by the pattern data. By using the light-shielding mask and the phase shift mask, a projected image of a mask pattern is formed on a photoresist film on a semiconductor wafer through a projection optical system of an exposure apparatus without changing their relative positional relationship.

Next, a pattern forming method will be described with reference to the flowchart of FIG.

A pattern of a semiconductor integrated circuit or the like can be represented by a combination of data in which information such as a pattern width W, a length H, a center coordinate (X, Y) of the pattern is formed by combining rectangular figures. (Step 101).

The pattern data of the semiconductor integrated circuit or the like to be combined is superimposed on the figures by these data (in other words, the figures overlap each other).
In the case of, the overlap removal processing (cutout of the transfer area) is performed (step 102).

In the overlap removal processing, for example, a figure formed by pattern data is developed on the memory map and logical sum (OR) processing is performed. In addition, a window is provided in an area including a pattern that is adjacent to the pattern to reduce the processing time of the computer.

Next, sort processing is performed to rearrange the figures in the X and Y directions (step 103). In this sort, the pattern data is grouped and rearranged in a direction having a large area ratio of adjacent patterns (for example, the X-axis direction or the Y-axis direction) at predetermined intervals (for example, wiring pitch of the semiconductor integrated circuit pattern). It is a thing.

Then, at the point where the figures overlap, the process of dividing in the X-axis direction or the Y-axis direction (pattern division) is performed again (step 104). That is, n figures Pi (i
= 1 to n, where n is an integer) (where Xi ≤ X
<Xi + 1 or Yi ≦ Y <Yi + 1).

Next, i is initially set to i = 1 (step 105), and one figure Pi is read (step 106).

Next, the phase shifter forming process is performed on the figures included in one group that has been rearranged. Whether the figure group is an odd number or an even number (i =
The subsequent processing differs depending on 2 m, where m is an integer (step 107).

In the case of an even number, the relative position coordinates of the patterns of the figures in the above group are not changed, and the transmitted light phase of the mask pattern which transmits the figure area determined by this is set to φ = 0 (step 108). .

Here, when the figure in the above group is in contact with the figure of the group adjacent to the figure, the following processing is performed. That is, whether or not the boundaries are in contact can be determined by, for example, whether or not the x coordinate of each figure in the next group becomes a value obtained by adding the wiring pitch to the x coordinate of the figure in the previous group.

The phase of the mask pattern passing through the figure area determined by the figures of the adjacent groups is φ = π.
(180 °), and a diffractive projection image is generated due to the phase difference from the figure in the previous group. Therefore, it is necessary to eliminate the influence of this diffraction projection image. Therefore, pattern data of a figure that covers the boundary portion of the figure is created, and with this pattern data, a light-shielding mask (second
Mask). Using this mask, overlapping exposure is performed on the portion where the diffraction projection image is generated.

If it is determined in step 107 that the figure is an odd number, the phase of the mask pattern that is transmitted through the figure area determined by the figure in the above group without changing the relative position coordinates of the pattern is φ =. π
(Step 109). A specific example of the processing of steps 109 and 108 is the mask M of FIG. 3B, and FIG. 3C shows an example of forming the phase shifter (note that T is in the figure). (Light-transmitting region, S is a light-shielding region, and F is a phase shifter).

When the figure in the above group touches the border of the figure in the adjacent group, pattern data of the figure that covers the boundary part of the figure is created, and this figure is used to form this figure. A light-shielding mask to be transferred is created, and the portion where the above-mentioned diffraction projection image is generated is overlaid and exposed.

When it is determined that the processing for n figures is completed (step 110), mask pattern formation is executed (step 112), and the semiconductor wafer is exposed (step 113). On the other hand, if (i = i + 1) is not satisfied, the data of the next group is read (step 11
1), the position with respect to the X coordinate, Pi + 1 (X) -Pi (X) ≤pW, is determined (step 114), and if Yes, the light-shielding figure Qi + 1 (as shown in FIG. 3A). ΔW, H + Δ
H, X + pW / 2, Y) is created (step 11)
5). On the other hand, if the determination is No, it is considered that no figure has occurred, and the process proceeds to the next step (where Pi is the phase φ = 0 of the figure Pi and Pi + 1 is the phase φ = of the figure Pi + 1).
π, Pi (X) is the X coordinate of the figure Pi, Pi + 1 (X) is the X coordinate of the figure Pi + 1, and pW is the pattern pitch in the X direction).

Further, after the processing of steps 114 and 115, the position relative to the Y coordinate, Pi + 1 (Y) -Pi (Y) ≤pH, is determined (step 116), and as shown in FIG. Light-shielding figure Qi + 1 (W + ΔW, ΔH, X, Y + pH /
2) is created (step 117), and the process proceeds to step 10
The process returns to 6 and the subsequent processes are repeatedly executed.

FIG. 4 illustrates the flow of pattern division (X-direction area division) and light-shielding figure creation processing in step 104. That is, the part where the X direction and the Y direction are connected is divided at the boundary part between the vertical part and the horizontal part,
Then, the area is divided at the middle of the horizontal portion to perform the pattern division. Furthermore, the procedure for creating a light-shielding figure having a light transmission area of Qi + 1 is shown.

Now, the structure of the mask M shown in FIG. 3B will be described. The pattern shown in FIG. 3 is a pattern when the semiconductor integrated circuit pattern is transferred to the negative resist on the semiconductor wafer.

The mask M is a mask for transferring a predetermined semiconductor integrated circuit pattern onto a semiconductor wafer through a reduction projection optical system or the like, for example, a reticle on which an original image of a semiconductor integrated circuit pattern having a size five times the actual size is formed. is there.

In this mask M, for example, a transparent synthetic quartz glass having a refractive index of about 1.47 is used as a base material, and the main surface thereof has a light transmission that is substantially transparent to exposure light. Area T (white area shown) is opaque light-shielding area S
A phase shifter F for inverting the phase of the transmitted light is arranged in one of the light transmission regions T as shown in FIG. 3C while being formed so as to sandwich the (shaded area in the drawing).

In the light transmission region T, the first transmission region and the first transmission region which is close to the first transmission region
At least a second transmissive region in which the phase of the transmitted light is inverted is provided.

Next, FIG. 5 shows another mask combination for obtaining the semiconductor integrated circuit pattern of FIG. 2, and the mask structure will be described. The pattern of FIG. 5 is a pattern used when a semiconductor integrated circuit pattern is transferred to a negative resist on a semiconductor wafer.

In the formation of the phase shifter by the simple repetition method, as described with reference to FIG. 2, when the pattern interval is narrow, a shadow is produced in the horizontal portion and the pattern is cut off.

This embodiment corresponds to the alternative example of FIG. 3, and the horizontal portion is a mask provided with a phase shifter 4 having a narrow width shown in FIG. 5A in a frame shape, and FIG. A mask having a phase shifter 5 so that φ = π, φ = 0, and φ = π is sequentially used from the left in the three columns of light transmitting regions shown in FIG. No pattern exposure is possible. 5C and 5D are cross-sectional views, FIGS. 5E and 5F are amplitude waveforms on the semiconductor wafer, and FIGS. 5G and 5H are semiconductor wafers. 3 shows the light intensity characteristic of the.

As compared with the embodiment of FIG. 3, the size of the effective transfer pattern of FIG. 5A can be reduced and the depth of focus can be increased.

Further, FIG. 6 shows a second circuit pattern example. In this case as well, this is a pattern for transferring the semiconductor integrated circuit pattern to the negative resist on the semiconductor wafer.

When a mask having such a pattern is required, if the pattern interval is small in the conventional phase shifter formation, the light-shielding portion between the patterns in either the horizontal direction or the vertical direction is not formed, resulting in a short circuit. .

Therefore, in such a case, as shown in FIG. 7, when a mask having the sub-phase shifter 6 as shown in FIG. 7A and a mask having the phase shifter 7 as shown in FIG. A desired pattern having a shape as shown in FIG. 6 can be obtained. In FIG. 7A, four sub-phase shifters 6 having a narrow width are provided so as to surround the portion Q of FIG. 6, and this is set as a region of φ = π. As a result,
As compared with the embodiment of FIG. 3, the size of the effective transfer pattern of FIG. 6A can be reduced and the depth of focus can be increased.

Further, in FIG. 7B, there are two light transmission regions T (white portions), one on the left side and two on the left side, and one light transmission region T on one side vertically (white portion). The phase shifter 7 is provided so that φ = π, and the phase shifter 8 is provided so as to surround the lower half of the light transmission region T on the right side, and similarly, the region is φ = π. The other is a region of φ = 0 where no phase shifter is provided. Note that (c) and (d) are masks M
(E) and (f) are amplitude waveforms on the semiconductor wafer, and (g) and (h) show light intensity characteristics on the semiconductor wafer.

The above-mentioned FIG. 2, FIG. 3 (b), FIG. 5 (b),
The mask M having the structure shown in FIGS. 6 and 7B is formed by exposing a negative resist deposited on a semiconductor wafer to an exposure process to form a resist pattern close to or about the exposure wavelength on the semiconductor wafer. It is used for the application to be left on. For example, in the wiring process of a semiconductor integrated circuit, a negative resist is usually used because the exposure resist of the wiring portion is left.

Here, FIGS. 8A to 8C are explanatory views for explaining a method of transferring a wiring pattern to a negative resist using a normal mask.

FIG. 6A is an explanatory diagram during the exposure process. An insulating film 10a is deposited on the semiconductor wafer 9,
A metal film 11 is deposited on the insulating film 10a, and further,
A negative resist 12 is deposited on the metal film 11. The light transmitted through the light transmitting region T of the mask M is reduced by the reduction projection lens 13 and transferred to the negative resist 12 on the semiconductor wafer 9.

FIG. 6B is an explanatory diagram after the wiring pattern and the like on the mask M are transferred to the negative resist 12.
A resist pattern 12a made of a negative resist 12 is formed on the metal film 11.

In the case of a negative type resist, a portion exposed to light is cured and remains as a pattern. Therefore, the light transmission region T on the mask M is a pattern in which the negative resist remains.

FIG. 7C is an explanatory diagram after the metal film 11 is patterned using the patterned resist pattern 12a as an etching mask to form the wiring pattern 11a.

On the other hand, if a positive resist is used, it can be used for the application of forming grooves of the same shape. here,
9A to 9C are explanatory views for explaining a method of forming a connection hole pattern in a positive resist using a normal mask.

FIG. 6A is an explanatory diagram during exposure. The insulating film 10b is deposited on the metal film 11, and the insulating film 10b
A positive resist 14 is deposited on the top. The light transmitted through the light transmitting region T of the mask M is reduced by the reduction projection lens 13
Positive resist 1 reduced on the semiconductor wafer 9 through
4 is to be transferred.

FIG. 9B is an explanatory diagram after the connection hole pattern and the like on the mask M are transferred to the positive type resist 14. A resist pattern 14a made of a positive resist 14 is formed on the insulating film 10b.

In the case of a positive type resist, a portion exposed to light is removed and a portion not exposed to light remains as a pattern. Therefore, the light-shielding region on the mask M is a pattern in which the positive resist remains.

FIG. 6C is an explanatory diagram after the insulating film 10b is patterned by using the patterned resist pattern 14a as an etching mask to form the connection hole 15.

By the way, when an isolated pattern such as a wiring pattern is transferred to a positive resist by using the phase shift technique, an unnecessary pattern is formed in a region where the pattern is not originally formed due to the phase difference of light. Therefore, to form an isolated pattern using the phase shift technique,
Normally, a positive resist is not used, but a negative resist is used.

A so-called lift-off method is used in which a metal film is deposited on the positive resist having the groove pattern formed thereon by a sputtering method or the like, and then the positive resist is removed to remove the metal film other than the groove pattern. A wiring pattern can be formed by using it, but this is not common.

In this embodiment, the exposure area is divided into two, one of which is an exposure area in which a phase shifter is formed, and the other of which is an exposure area for irradiating unnecessary pattern portions with light. It is possible to transfer a resist pattern close to the exposure wavelength or less to a positive resist on a semiconductor wafer. That is, it is possible to eliminate the restriction on whether the resist deposited on the semiconductor wafer is a positive type or a negative type. Hereinafter, a specific example will be described.

FIG. 10 is an explanatory view for explaining a method of leaving a resist pattern, which is close to or less than the exposure wavelength, on the positive resist deposited on the semiconductor wafer by the exposure process. In addition, x1 to x6, y1, y2
Represents position coordinates, and the same position coordinates are shown at the same position.

FIG. 10A is an example of a resist pattern which is actually formed on a positive resist of a semiconductor wafer and is in close proximity. Two rectangular patterns shown in diagonal lines and extending in parallel to each other are positive resist. Is a resist pattern 14a.

FIG. 9B shows an example of the first mask M for forming the resist pattern 14a shown in FIG.
On the mask M, three rectangular light-transmitting regions T extending in parallel to each other are formed, and the lights passing through the light-transmitting regions T on both sides have the same phase and the light-transmitting regions on both sides are formed. The respective lights passing through T and the central light transmitting region T are set so that their phases are opposite to each other. The light-shielding region S sandwiched between the light-transmitting regions T on both sides and the central light-transmitting region T corresponds to the resist pattern 14a shown in (a) with an interval shorter than the exposure wavelength remaining on the semiconductor wafer.

FIG. 7C shows an example of the second mask M for forming the resist pattern 14a shown in FIG.
On the mask M, the light transmission region T and the light shielding region S sandwiched by it in the first mask of (b) are covered, that is, the coordinates (x1, y1), (x6, y1), (x1.
, Y2), (x6, y2) has a rectangular light-shielding region S formed therein. However, the light shielding region S may be formed so as to cover at least a part of the light transmitting regions T on both sides of (b).

In order to form the resist pattern 14a by using the first mask M and the second mask M as described above, after depositing a positive resist on the semiconductor wafer, the first mask M and the second mask M are formed. It suffices to carry out the exposure continuously in time with the relative positions of the two masks M matched.

For convenience of explanation, the same scales are used for the figures (a), (b), and (c). For example 5: 1
When applied to a reticle used for reduction projection exposure, FIGS. 7B and 7C need to be magnified five times as large as FIG. Hereinafter, the same scale is used in the description of the resist pattern and the mask corresponding thereto.

FIG. 11 shows an example of forming the wiring pattern of FIG. 2 using a positive resist. Note that x1 to x8 and y1 to y6 represent position coordinates, and the same position coordinates are shown at the same position.

FIG. 10A is an example of a resist pattern in proximity to be transferred to a positive resist on a semiconductor wafer. Three resist patterns 14a indicated by hatching are arranged on the semiconductor wafer. Of the three resist patterns 14a, the leftmost resist pattern 14a in FIG. 11 extends in the direction orthogonal to the middle position, and then extends again in the direction orthogonal to the arrangement line of the central resist pattern 14a. There is.

FIG. 10B shows an example of the first mask M for forming the resist pattern 14a shown in FIG.
Three light transmitting regions T are formed on the mask M, and two light transmitting regions T on the left side of FIG.
Are set so that the phases of light transmitted in the same region are opposite to each other. Light-blocking area S sandwiched between light-transmissive areas T
Corresponds to the resist pattern 14a shown in (a) with an interval shorter than the exposure wavelength remaining on the semiconductor wafer.

FIG. 7C shows an example of the second mask M for forming the resist pattern 14a shown in FIG.
On the mask M, so as to cover the light transmission region T and the light shielding region S sandwiched by the light transmission region T in the first mask M of (b),
That is, the coordinates (x1, y1), (x8, y1), (x1
, Y6) and (x8, y6), a quadrangular light shielding region S is formed. However, the quadrangular light shielding region S may be formed so as to cover at least part of the light transmitting regions T on both sides.

Then, at a predetermined position of the quadrangular light-shielding region S, that is, a boundary region in which the phase of light is inverted only by the exposure process with the first mask M, an unnecessary pattern remains in the positive resist. A quadrangular minute light-transmitting region T is formed at the closed position. Here, around the minute light transmission region T, as in the case of FIG.
By providing a phase shifter for inverting the phase of the transmitted light, it is possible to deal with a finer pattern.

In order to form the resist pattern 14a by using the first mask M and the second mask M as described above, after depositing a positive resist on the semiconductor wafer, the first mask M and the second mask M are formed. It suffices to carry out the exposure continuously in time with the relative positions of the two masks M matched. This makes it possible to form fine wiring.

Further, in order to transfer the resist pattern for the contact hole to the positive type resist, the exposure process is performed only by using the phase shift mask having the structure shown in FIG. 5A or FIG. 7A. I'm fine.

Alternatively, in order to transfer the resist pattern for the connection hole to the positive type resist, FIG. 12 and FIG.
As shown in FIG.
% Or less of a semi-transparent phase shift film 17 may be deposited, and the exposure process may be performed using a mask M0 having a phase shifter in which an opening pattern 18 having a desired shape and size is formed at a predetermined position. The phase difference of the transmitted light (L2-L1
) Is about 180 degrees.

That is, in this embodiment, the method of FIGS. 10 and 11 and the method of FIGS. 5A and 7A are used.
In the entire exposure process in the manufacturing process of the semiconductor integrated circuit device, by appropriately using the method of (1) and the method of using a conventional ordinary light-shielding mask in the process not using the phase shift technique in the manufacturing process of the semiconductor integrated circuit device. It is possible to form a resist pattern close to an exposure wavelength or less or a resist pattern having a dimension of an exposure wavelength or less using only a positive resist.

On the other hand, when a negative resist is used, as shown in FIG.
Although it is possible to form a line pattern as described above, it is difficult to form a minute connecting hole. This is because when an isolated opening pattern such as a connection hole is transferred to a negative resist by using the phase shift technique, an unnecessary pattern is formed in an area where the pattern is not originally formed due to the phase difference of light. Because it will be.

In this embodiment, the exposure area is divided into two, one of which is an exposure area in which a phase shifter is formed, and the other is an exposure area for irradiating unnecessary pattern portions with light. It is possible to transfer a resist pattern close to the exposure wavelength or less to a negative resist on a semiconductor wafer. That is, it is possible to eliminate the restriction on whether the resist deposited on the semiconductor wafer is a positive type or a negative type. Hereinafter, a specific example will be described.

FIG. 14 shows an example of a method of forming a minute connecting hole by an exposure process using a phase shift technique using a negative resist. In the figure, x1, x2,
y1 and y2 represent the center position coordinates of the figure on the mask M,
The same position coordinates are shown at the same position.

FIG. 9A shows an example of a resist pattern 12a which is transferred to a negative resist on a semiconductor wafer and is closely arranged. Four small white squares are regions for forming connection holes.

FIG. 9B shows an example of the first mask M for forming the resist pattern 12a having an interval shorter than the exposure wavelength shown in FIG. A phase shifter 19a is arranged on the mask M at a position where a connection hole is formed. The phase shifter 19a is configured by contacting the right-angled portions of two right-angled isosceles triangles so that their respective hypotenuses are aligned. That is, the phase shifter 1
9a has two straight edges of ± 45 with respect to the XY axes.
It has an orthogonal region which is inclined at right angles and is orthogonal.

FIG. 9C shows an example of the second mask M for forming the resist pattern 12a shown in FIG.
At the position for forming the connection hole on the mask M,
A quadrangular light-shielding pattern 20 that covers a part of the edge orthogonal region in the phase shifter 19a of the first mask M.
Are formed.

In order to form the resist pattern 12a using the first mask M and the second mask M as described above, a negative resist is deposited on the semiconductor wafer, and then the first mask M and the second mask M are formed. It suffices to carry out the exposure continuously in time with the relative positions of the two masks M matched. This makes it possible to form minute connection holes.

FIG. 15 shows another example of a method of forming minute connection holes by exposure processing using a phase shift technique using a negative resist.

FIG. 10A shows an example of the adjacent resist pattern 12a transferred to the negative resist on the semiconductor wafer. Four small white squares are regions for forming connection holes.

FIG. 9B shows an example of the first mask M for forming the resist pattern 12a having an interval shorter than the exposure wavelength shown in FIG. The broken line indicates the connection hole.

On the mask M, a rectangular phase shifter 1 is formed.
9b is arranged. The phase shifter 19b is formed so that each side thereof is arranged on the diagonal line of the connection hole. However, here, the edge of the phase shifter 19a is
It suffices that it is formed so as to correspond to the diagonal line of the opening pattern of at least two resist patterns 12a in (a).

Here, the reason why at least two diagonal lines are used is that this makes it possible to make the pattern size of the phase shifter somewhat larger than in the case where a phase shifter is provided for each individual aperture pattern. This is because good interference of transmitted light can be obtained between the region with the phase shifter and the region without the phase shifter.

FIG. 10C is an example of the second mask M for forming the resist pattern 12a having an interval shorter than the exposure wavelength shown in FIG. The broken line indicates the connection hole.

On the mask M, there is formed a phase shifter 19c having a side which is orthogonal to one side of the phase shifter 19b shown in (b) at the position of the connection hole. However, here, the edge of the phase shifter 19c is
It may be formed so as to correspond to the diagonal lines of at least two opening patterns of (a).

Here, the reason why there are at least two diagonal lines is that this makes it possible to make the pattern size of the phase shifter somewhat larger than in the case where a phase shifter is provided for each individual resist pattern. This is because good interference of transmitted light can be obtained between the region with the phase shifter and the region without the phase shifter.

Although not shown, (b) of FIG.
An alignment mark pattern is formed around the mask in (c).

In order to form the resist pattern 12a for the connection hole by using the first mask M and the second mask M as described above, a negative resist is deposited on the semiconductor wafer and then the first resist M is formed. It suffices to carry out exposure continuously in time with the relative positions of the mask M and the second mask M being matched. This makes it possible to form minute connection holes.

Further, in order to form a connection hole on a semiconductor wafer on which a semiconductor integrated circuit element is formed, using the masks of FIGS. 14 and 15, the following may be performed, for example. That is, first, a negative resist is applied on an insulating film deposited on a semiconductor wafer, a resist pattern for a connection hole is formed on the insulating film by an exposure process using the mask of FIG. 14 or 15, and then, By etching the insulating film using the resist pattern as an etching mask, a connection hole having a size shorter than the exposure wavelength is formed in the insulating film.

Here, FIG. 16 is an explanatory diagram of the amplitude and intensity of the light projected on the surface of the semiconductor wafer via the projection optical system (optical exposure apparatus).

With the above configuration, as shown in FIG. 16A, the transmitted light is transmitted by the phase shifter F formed in one of the light transmission regions T1 and T2 sandwiching the light shielding region S formed on the mask M. By inverting the phase and utilizing the light interference between them, a pattern closer to the exposure wavelength can be imaged on the resist film on the semiconductor wafer through the optical projection system.

The light L1 immediately after passing through the first light transmitting region T1 of the mask M is inverted from the phase of the light L2 immediately after passing through the second light transmitting region T2 as shown in (b).
The amplitude immediately after passing through the mask M has a rectangular waveform, but the amplitude on the semiconductor wafer has a waveform as shown in (c). Then, in the semiconductor wafer, the two lights interfere with each other in the light-shielding region S, which is the boundary between them, and weaken each other, resulting in a light intensity waveform as shown in (d).

In this embodiment, one light transmission region T1 and the other light transmission region T2 which are adjacent to each other with the light shielding region S interposed therebetween are phase-inverted with each other. Thus, 1 / of the exposure wavelength
By separating them by about 2, the intensities of the transmitted lights can be mutually increased. Therefore, pattern data of an area covering the boundary area of the division is created, a light-shielding mask is formed based on this pattern data, and a shadow portion generated by the projection of the phase shift means is overlaid and exposed.

FIG. 17 shows the overall structure of the mask M of this embodiment. As shown in FIG. 17, an opaque light shielding area S is provided around the transfer areas A1 and A2 used for exposure. Positioning marks B1 and B2 of the mask M and position adjusting marks B3 and B4 of the mask M and the semiconductor wafer which is the sample to be exposed are formed in the light-shielding region S, and the mask M and the semiconductor wafer are positioned by this. It can be exposed together. B5 and B6 are phase shift layer and light shielding layer alignment marks.

By forming the mask M0 having the above-mentioned phase shifter and the mask M on the same glass substrate 16, the exposure light irradiated on the mask surface is shielded by the mask blind of the exposure device at the time of exposure. Thus, the exposure can be performed efficiently. In this respect, the same exposure can be performed by dividing the two glass substrates into two and performing the exposure process twice.

In the conventional method in which the phase difference is simply applied to one of the light transmitting areas sandwiching the light shielding area, there is a restriction on the arrangement of the fine transfer pattern. However, this method does not reduce the execution throughput of exposure, and the restriction is imposed. Can be eliminated. Therefore, it becomes possible to promote automation of arrangement of the phase shift pattern.

Next, the mask forming method of this embodiment and the exposure method using the same will be described. Figure 18 (a)
(F) is an explanatory view for explaining the mask manufacturing method of the present embodiment.

First, the mask material M0 is created. The mask material M0 is a glass substrate 1 made of transparent quartz glass or the like.
Cr on the main surface of No. 6 by using, for example, a sputtering method.
It is created by depositing a metal thin film 21 such as (chrome). An electron beam resist 22a is spin-coated on the main surface of the mask material M0 as shown in FIG.

Next, the mask material M0 is irradiated with an electron beam by using an electron beam drawing apparatus. The electron beam drawing apparatus scans an electron beam by computer control based on pattern information such as graphic information of semiconductor integrated circuit patterns and position coordinates. The pattern data used here corresponds to, for example, the region (φ = π) where the phase of the transmitted light is inverted shown in step 109 of FIG.

At this time, in addition to the semiconductor integrated circuit pattern, as shown in FIG. 17, two alignment mark patterns for light-shielding pattern processing are exposed diagonally on the periphery of the main surface of the mask M. This pattern is a cross mark having a size of about 300 μm.

Next, depending on whether the electron beam resist 22a is a positive type or a negative type, the exposed portion or the unexposed portion thereof is removed by a developing solution, and the exposed Cr film is etched to remove the exposed portion of FIG. As shown in (b), the light shielding pattern 21a is formed. The etching of the Cr film is
For example, wet etching with cerium diammonium nitrate or the like can be used.

The resist on the Cr film is usually removed by etching the glass substrate 16 in the next step. In this case, the resist is removed by oxygen plasma etching or the like, the mask is washed, and the appearance of the mask M is inspected. It is desirable to do. The remaining defects of the minute Cr film found by this visual inspection are removed by, for example, irradiation with laser light. Also, C
The defect of the r film is spot-exposed to the defective portion by using, for example, a negative resist, and developed to leave the resist. In this way, the light-shielding pattern 21a for forming a substantially defect-free phase shift layer can be formed.

Next, as shown in (c) of FIG.
Using the film or the like as a mask, the glass substrate 16 is removed by a predetermined depth by CF ₄ plasma etching or the like. Here, the depth d of the glass substrate 16 is represented by the following equation, where λ is the wavelength of the exposure light and n is the refractive index of the glass substrate 16. Alternatively, it is set so as to satisfy this odd multiple relationship.

D = λ / 2 (n-1) For example, the wavelength of light is 365 nm (i line), the glass substrate 16
Assuming that the refractive index is 1.47, the depth d of the glass substrate 16 may be about 390 nm. In the plasma etching process of CF ₄ , the depth can be controlled by the etching time or the like. By the plasma etching process, with respect to a defect in which a specific location does not have a predetermined depth, the defect site is irradiated by a focused ion beam method or the like, and the glass substrate 16 is etched.

Further, instead of the glass substrate 16, by depositing a transparent film and a light-shielding film having a predetermined film thickness on the glass substrate 16, it is possible to improve the depth processing accuracy.

Next, as shown in FIG.
As shown in FIG. 8D, the Cr film is removed. further,
As shown in (e) of FIG. 18, after a metal thin film 23 such as Cr is deposited on the main surface of the glass substrate 16 by using, for example, a sputtering method, an electron beam is deposited on the metal thin film 23 on the main surface. The resist 22b is spin-coated.

Further, the position of the above-mentioned alignment cross mark is detected by using an electron beam drawing apparatus, the coordinate system of the step pattern formed on the glass substrate 16 is aligned, and the desired pattern is electronically aligned at a predetermined position. Irradiate with rays. Here, the pattern of electron beam irradiation is, for example, a pattern that becomes a light-shielding region S that is a positive / negative reversal region of the light transmission region T (combined region of φ = π and φ = 0) shown in FIG. Regarding the drawing accuracy of electron beam drawing equipment, the pattern superposition is 0.
Since it can be 1 μm or less, this method can be applied to, for example, a mask (reticle) of an exposure apparatus with a reduction rate of 1/5.

In addition to the circuit pattern, the peripheral portion of the transfer area of the glass substrate 16 is exposed with a pattern for alignment marks with the semiconductor wafer. The pattern of this alignment mark is specified by the reduction projection exposure apparatus. Thereafter, depending on whether the electron beam resist 22b is a positive type or a negative type, the exposed portion or the unexposed portion is removed by a developing solution, and the exposed metal thin film 2 is removed.
By etching 3, the light-shielding pattern 23a is formed as shown in FIG.

Finally, the electron beam resist 22b is removed. Then, the appearance of the light shielding pattern 23a is inspected.
In the light-shielding pattern 23a, the remaining defects of the minute Cr film are removed by, for example, irradiating a laser beam, and the defective defects of the Cr film are
For example, by the focused ion beam method, the defect can be repaired by adding the organic gas and irradiating the defective portion to form the light shielding film of the carbon film.

In the above description, the method of inverting the phase of the transmitted light is the method of removing the glass substrate 16 by etching, but a transparent film may be deposited on the glass substrate 16. Examples of this transparent film include spin-on-glass (S
A means such as pin on glass) can be used.

FIG. 19 is a block diagram showing the optical system of a reduction projection type exposure apparatus 24a of this embodiment.

In the exposure device 24a, a beam expander 26, a mirror 27, a half mirror 28 (or a beam splitter), a lens 29, a mirror 30, and an objective lens 31 are arranged on the optical path connecting the light source 25 and the semiconductor wafer 9. It is set up. Further, each of the mirror 32, the lens 33, the mirror 34, and the objective lens 35 is sequentially arranged on the reflection optical path of the half mirror 28.

Then, at the positions of the masks M1 and M2, a mask M provided with a phase shifter as shown in FIGS. 10 and 11 is provided. The light source 25 is, for example, i-line (wavelength 365n
m) is a high pressure mercury lamp that emits light L. Also,
The semiconductor wafer 9 is accurately positioned and set on the X, Y stage 36 prior to exposure. A resist sensitive to light is spin-coated on the main surface of the semiconductor wafer 9.

The light L from the light source 25 is expanded by the beam expander 26, refracted by the mirror 27, and then split into two lights L1 and L2 by the half mirror 28. After that, one of the two lights L1 and L2 (L1) goes straight on and is incident on the mask M1, and the other light (L2) is refracted by the mirror 32.
It is incident on the mask M2.

The light transmitted through the mask M1 is condensed by the lens 29, refracted by the mirror 30, and then exposed on the semiconductor wafer 9 by the objective lens 31. On the other hand, the light L2 on the reflection optical path of the half mirror 28 is refracted by the mirror 32. Further, the light emitted from the mirror 32 passes through the mask M2, is condensed by the lens 33, is refracted by the mirror 34, and is then exposed on the semiconductor wafer 9 by the objective lens 35.

In the exposure device 24a of FIG. 19, an incoherent converter (not shown) may be inserted on the optical axis of the light L1 in order to prevent the interference of the two lights L1 and L2. In addition, transparent glass may be inserted so that the optical path difference between the two lights L1 and L2 is equal to or longer than the coherence length. Further, a shutter may be provided in the latter stage of the half mirror 28 and the mirror 32 so that one of the mask M1 and the mask M2 is exposed and then the other is exposed.

Further, the exposure apparatus 24a has masks M1 and M
2 has a function to change the coherency of the irradiation light to 2 or the irradiation angle, a function to set the irradiation light area to the masks M1 and M2, and a function to move the transfer area of the masks M1 and M2 corresponding to the setting of the irradiation light area. ing. This makes it possible to reduce the error due to the distortion of the reduction projection optical lens and improve the overlay accuracy of the transfer patterns.

FIG. 20 is a block diagram showing the optical system of another reduction projection type exposure apparatus used in this embodiment.

On the optical path connecting the light source 25 of the exposure device 24b and the semiconductor wafer 9, the mirrors 37 and 38 and the shutter 3 are provided.
9, an aperture 40, a shortcut filter 41, a mask blind 42, a condenser lens 43 and a reduction projection lens 44 are provided, and the mask M is positioned in the alignment system. This mask M
Can be moved horizontally by the mask moving table 45. The mask moving table 45 can be moved according to the set value of the irradiation light area.

Then, at the position of the mask M, for example, in FIG.
0, a mask M provided with a phase shifter as shown in FIG. 11 is provided. The light source 25 is a high-pressure mercury lamp that emits light L such as i-line (wavelength 365 nm). Further, the semiconductor wafer 9 is accurately positioned and set on the wafer suction table 46 on the X, Y stage 36 prior to exposure. In addition,
A resist sensitive to light is spin-coated on the main surface of the semiconductor wafer 9.

Also in the exposure device 24b, the function of changing the coherency or the irradiation angle of the irradiation light to the mask M, the function of setting the irradiation light area to the mask M, and the mask M corresponding to the setting of the irradiation light area. It has a transfer area moving function. This makes it possible to reduce the error due to the distortion of the reduction projection optical lens and improve the overlay accuracy of the transfer patterns.

Exposure apparatus 24b and mask M of this embodiment
In order to transfer a predetermined semiconductor integrated circuit pattern onto the semiconductor wafer 9 using, the light L emitted from the light source 25 is first used.
To the mask M. At this time, the mask blind 42 is adjusted so that the light L enters only the first pattern region of the mask M.

The light transmitted through the pattern area becomes a spot light beam via the reduction projection lens 44 and is incident on the main surface of the semiconductor wafer 9 positioned on the wafer suction table 46.

As shown in FIG. 21, the main surface of the semiconductor wafer 9 is divided into a large number of exposure areas E1, E2, E3, ... And the light transmitted through the first pattern area is the first exposure area. It is incident on E1.

Subsequently, the X and Y stages 36 are moved to move the semiconductor wafer 9 in the horizontal direction, and the light transmitted through the first pattern area is incident on the first exposure area E2.

Thereafter, such an operation is repeated to transfer the semiconductor integrated circuit pattern formed in the first pattern area onto the semiconductor wafer 9.

Next, the mask M is moved, the mask blind 42 is adjusted, and the light L emitted from the light source 25 is incident only on the second pattern region of the mask M. The light L transmitted through the pattern area becomes a spot light beam via the reduction projection lens 44 and is incident on the first exposure area E2 on the main surface of the semiconductor wafer 9.

Thereafter, such an operation is repeated to transfer the semiconductor integrated circuit pattern formed in the second pattern area onto the semiconductor wafer 9.

In this way, the patterns formed in the two pattern regions of the same mask M can be easily overlaid and exposed on the same region of the semiconductor wafer 9.

As described above, the following effects can be obtained in this embodiment.

(1) By dividing the exposure area into two areas, one of which is an exposure area where a phase shifter is formed, and the other is an exposure area for irradiating light to an unnecessary pattern portion, a predetermined area is obtained. The semiconductor integrated circuit pattern can be transferred to the positive resist on the semiconductor wafer 9. That is, it is possible to eliminate the restriction as to whether the resist deposited on the semiconductor wafer 9 is a positive type or a negative type. Therefore, it is possible to form the resist pattern using only the positive resist in the entire exposure process in the manufacturing process of the semiconductor integrated circuit device.

(2). By dividing the exposure area into two areas, one of which is an exposure area on which a phase shifter is formed, and the other of which is an exposure area for irradiating unnecessary pattern portions with light, The semiconductor integrated circuit pattern can be transferred to the negative resist on the semiconductor wafer 9. That is, it is possible to eliminate the restriction as to whether the resist deposited on the semiconductor wafer 9 is a positive type or a negative type. Therefore, in the entire exposure process in the manufacturing process of the semiconductor integrated circuit device, the resist pattern can be formed using only the negative resist.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the above embodiment, the mask is 1
Although the case of one sheet and the case of a combination of two sheets are shown, a combination of three or more sheets may be used.

In the above description, the case where the invention made by the present inventor is mainly applied to the exposure process in the manufacturing process of the semiconductor integrated circuit device which is the field of application of the background has been described, but the invention is not limited to this. It is applicable, and can be applied to other exposure methods such as exposure processing in manufacturing liquid crystal substrates and the like.

[0152]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). According to the exposure method of the present invention, the first mask and the second mask are separately superposed and exposed, so that the positive mask is formed using the first mask having the phase shifter. Unnecessary patterns caused by the phase difference of light when transferring an isolated linear pattern such as a wiring pattern to a resist can be eliminated by the exposure process using the second mask. It is possible to eliminate the restriction of the resist material in the used exposure processing.
Therefore, it becomes possible to consistently use the positive resist in all the exposure processes in the manufacturing process of the semiconductor integrated circuit device.

(2). According to the exposure method of the present invention described above,
When an isolated opening pattern such as a connection hole pattern is transferred to a negative resist by using the first mask having a phase shifter by exposing the first mask and the second mask by overlapping and exposing. Unnecessary patterns caused by the light phase difference can be eliminated by the exposure process using the second mask, so that it is possible to eliminate the restriction of the resist material in the exposure process using the phase shift technique. . Therefore, it is possible to consistently use the negative resist in all exposure processes in the manufacturing process of the semiconductor integrated circuit device.

[Brief description of drawings]

FIG. 1 is a flowchart showing an exposure method according to the present invention.

FIG. 2 is a plan view showing an example of a circuit pattern to be realized by the embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a combination of masks for obtaining the circuit pattern of FIG.

FIG. 4 shows steps 104, 114 to 117 in FIG.
It is explanatory drawing which illustrated the processing content of.

FIG. 5 is an explanatory diagram showing another mask combination corresponding to the circuit pattern of FIG. 2;

FIG. 6 is a plan view showing a second circuit pattern example.

FIG. 7 is an explanatory diagram showing a combination of masks for obtaining the circuit pattern of FIG.

FIG. 8 is an explanatory diagram for explaining a normal exposure method using a negative photoresist.

FIG. 9 is an explanatory diagram for explaining a normal exposure method using a positive photoresist.

FIG. 10 is an explanatory diagram showing a combination of masks for forming a predetermined circuit pattern with a positive photoresist.

FIG. 11 is an explanatory diagram showing a mask combination for forming the circuit pattern of FIG. 2 with a positive photoresist.

FIG. 12 is a cross-sectional view showing the structure of a phase shift mask.

13 is a plan view of a main part of the phase shift mask of FIG.

FIG. 14 is an explanatory diagram showing a combination of masks for forming a predetermined circuit pattern with a negative photoresist.

FIG. 15 is an explanatory diagram showing a combination of masks for forming a predetermined circuit pattern with a negative photoresist.

FIG. 16 is an explanatory diagram of the amplitude and intensity of light projected on the surface of a semiconductor wafer via a projection optical system.

FIG. 17 is an overall plan view of the phase shift mask of this example.

FIG. 18 is an explanatory diagram for explaining the manufacturing method of the phase shift mask according to the present invention.

FIG. 19 is an explanatory diagram for explaining a configuration of an optical system in a reduction projection exposure apparatus to which the present invention is applied.

FIG. 20 is an explanatory diagram illustrating a configuration of an optical system in another reduction projection exposure apparatus to which the present invention is applied.

FIG. 21 is a plan view of the semiconductor wafer for explaining the exposure processing of the present embodiment.

FIG. 22 is a cross-sectional view showing the structure of a mask having no phase shift.

23 is a characteristic diagram showing a light intensity distribution of the mask of FIG.

FIG. 24 is a sectional view showing the structure of a conventional phase shift mask.

FIG. 25 is a characteristic diagram showing the light intensity distribution of FIG. 24.

[Explanation of symbols]

 1 Glass Substrate 2 Chromium Film 3 Phase Shift Film 4 Phase Shifter 5 Phase Shifter 6 Sub Phase Shifter 7 Phase Shifter 8 Phase Shifter 9 Semiconductor Wafers 10a, 10b Insulation Film 11 Metal Film 11a Wiring Pattern 12 Negative Photoresist 12a Resist Pattern 13 Reduction projection lens 14 Positive photoresist 14a Resist pattern 15 Connection hole 16 Glass substrate 17 Phase inversion film 18 Opening pattern 19a-19c Phase shifter 20 Light shielding pattern 21 Metal thin film 21a Light shielding pattern 22a, 22b Electron beam resist 23 Metal thin film 23a Light shielding Patterns 24a, 24b Exposure device 25 Light source 26 Beam expander 27 Mirror 28 Half mirror 29 Lens 30 Mirror 31 Objective lens 32 Mirror 33 Lens 34 Mirror 35 Objective lens 36 X, Y stage 37 Mirror 38 Mirror 39 Shutter 40 Aperture 41 Shortcut filter 42 Mask blind 43 Condenser lens 44 Reduction projection lens 45 Mask moving table 46 Wafer suction table 50 Mask substrate 51 Metal film 52 Phase shifter M, M1 Mask S Light-shielding area T light transmitting area P1, P2 light transmitting area N light shielding area

Claims (9)

[Claims] 1. When a plurality of patterns having an interval shorter than an exposure wavelength are transferred onto a sample by causing a phase difference in transmitted light by a phase shifter provided at a predetermined position of a light transmitting region of a mask, the sample is transferred onto the sample. After depositing a positive photoresist on the sample, a light-shielding region is provided in a region corresponding to at least one set of resist patterns with an interval shorter than the exposure wavelength to be left on the sample, and a light-transmitting region formed in a part of the periphery thereof. A first mask having a phase shifter for reversing the phase of transmitted light in one of the light transmission regions sandwiching the light shielding region, and the light transmission region of at least a part of the light shielding region of the first mask and the periphery thereof. A light-shielding region covering the second
The exposure method is characterized in that the exposure process is performed continuously in time while matching the relative position with the mask. 2. The exposure method according to claim 1, wherein light is irradiated to unnecessary pattern positions formed on the positive photoresist due to a phase difference of light during the exposure process using the first mask. The second portion in which a transparent region is formed
An exposure method, which comprises performing an exposure process using the mask of. 3. When transferring a plurality of patterns having an interval shorter than an exposure wavelength onto a sample, a shadow of interference of transmitted light at an edge portion of a phase shifter provided at a predetermined position of a light transmitting region of a mask, After depositing a negative photoresist on the sample, the edges of the phase shifter are orthogonal to each other so as to invert the phase of the transmitted light to the region corresponding to the resist pattern having a dimension shorter than the exposure wavelength opened on the sample. Exposure processing is performed continuously in time with the relative positions of a first mask including a region and a second mask including a light-shielding region that covers a part of an orthogonal region of the edge portion of the phase shifter being matched. An exposure method comprising: 4. When transferring a plurality of patterns having an interval shorter than an exposure wavelength onto a sample, a shadow of interference of transmitted light at an edge portion of a phase shifter provided at a predetermined position of a light transmitting region of a mask, After depositing a negative photoresist on the sample, the transmitted light so that the edge portion is arranged on the diagonal line of the resist pattern in the region corresponding to the resist pattern having a dimension shorter than the exposure wavelength opened on the sample. A first mask provided with a phase shifter for inverting the phase of the resist pattern, and a phase shifter for inverting the phase of transmitted light such that an edge portion is arranged on another diagonal line of the resist pattern in a region corresponding to the resist pattern. The exposure method, wherein the exposure process is performed continuously in time in a state where the relative position to the second mask provided with is matched. 5. The exposure method according to claim 1, wherein an irradiation light region for the mask is set,
An exposure method comprising the step of moving the mask accordingly and shifting the transfer area to transfer the transmitted light of a predetermined pattern on the mask onto the sample. 6. A method of manufacturing a semiconductor integrated circuit device using the exposure method according to claim 1, wherein the sample is a semiconductor wafer and the plurality of patterns are wiring patterns. Manufacturing method of semiconductor integrated circuit device. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein both the size and the interval of the predetermined semiconductor integrated circuit pattern transferred onto the semiconductor wafer are equal to or more than the exposure wavelength, Manufacturing of a semiconductor integrated circuit device, characterized in that the predetermined semiconductor integrated circuit pattern is transferred to a positive photoresist deposited on the semiconductor wafer by using an ordinary mask that does not cause a phase difference in transmitted light. Method. 8. A method of manufacturing a semiconductor integrated circuit device using the exposure method according to claim 3, wherein the sample is a semiconductor wafer, and the plurality of patterns are connection hole patterns. Method for manufacturing semiconductor integrated circuit device. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein in the step in which both the size and the interval of the predetermined semiconductor integrated circuit pattern transferred onto the semiconductor wafer are equal to or more than the exposure wavelength, Manufacturing of a semiconductor integrated circuit device, characterized in that the predetermined semiconductor integrated circuit pattern is transferred to a negative photoresist deposited on the semiconductor wafer by using an ordinary mask that does not cause a phase difference in transmitted light. Method.