JPH08147985A - Associative memory - Google Patents

Abstract

PURPOSE: To simplify the retrieval procedure and to increase the retrieval speed by connecting the inputted reference data with the detection auxiliary data storing plural numbers write-freely and generating the retrieval data. CONSTITUTION: A reference data type signal inputted to a data type signal input terminal is decoded by a decoder of a register specification circuit, and one among channels 1-m consisting of corresponding control data registers is specified. Then, one among N pieces of segment registers write-freely storing plural numbers of the retrieval auxiliary data such as the attribute data and the mask data, etc., and one among N pieces of mask registers are specified by the control data stored in the control data registers of the specified channels 1-m, and the retrieval is performed according to a stored retrieval mode. Thus, a series of retrievals over plural times are performed only by inputting the reference data, and the retrieval procedure is simplified, and the retrieval is accelerated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory word in which each stored data is stored in each of a plurality of memory words, and the reference word input is used to search for a memory word in which a predetermined stored data is stored. Regarding memory.

[0002]

2. Description of the Related Art Conventionally, an associative memory equipped with a search function as described above (Associative Memory)
y, content addressable memory; Content Addr
ESSABLE MEMORY) has been proposed. FIG. 6 is a circuit block diagram showing an example of a conventional associative memory.

In the associative memory 10, a large number of memory words 11_1, 11_2, each of which has m bits as one word, and which are composed of m-bit memory cells arranged in the lateral direction of the drawing.
..., 11_n are provided. Also, this associative memory 1
Reference numeral 0 is provided with a reference data register 12 into which 1-word reference data is input and a mask data register 13 into which mask data for masking the reference data for each bit is stored, and the reference data latched in the reference data register 12 Of all or a predetermined part of the bit pattern not masked by the mask data stored in the mask data register 13 and each memory word 11
, 11_n of the data stored in _1, 11_2, ...
11_2, ..., 11_n corresponding to each of the match lines 14_1, 14_2 ,.
…, Matching lines 14_1, 14_2 corresponding to 11_n
.., 14_n, a coincidence signal of logic "1" is output. Other match lines 14_1, 14_2, ..., 14_n remain at logic '0'.

These matching lines 14_1, 14_2, ...,
The signal output to 14_n corresponds to each match flag register 1
5_1, 15_2, ..., 15_n. Here, as an example, as shown in the figure, the match flag registers 15_1, 15_2, ...
It is assumed that "1", "1", "0", ..., "0", "0" are stored. These match flag registers 15_
The signals stored in 1, 15_2, ..., 15_n are input to the address encoder 16, and from the address encoder 16, a match flag register (here, the match flag register 15_2 and the match flag are stored, in which a signal of logic “1” is stored. The address signal corresponding to the match flag register having the highest priority among the registers 15_3) is output. Here, it is assumed that the younger the subscript, the higher the priority. Therefore, here, the match flag register 1
The memory address corresponding to 5_2 is output. Address signal AD output from this address encoder 16
Are input to the decoder 17 as needed. The decoder 17 decodes the input address signal AD and decodes the word lines 18_1 and 18 provided for the memory words 11_1, 11_2, ..., 11_n, respectively.
Input address signal A of _2, ..., 18_n
The access signal is output to any one word line (here, word line 18_2) corresponding to D. As a result, the data stored in the memory word 11_2 corresponding to the word line 18_2 to which the access signal is output is read to the output register 19.

Next, by changing the signal stored in the match flag register 15_2 to "0", this time the memory word 11_ corresponding to the match flag register 15_3 is changed.
3 addresses can be obtained. FIG. 7 is a functional block diagram of a conventional associative memory. In this associative memory,
Function data FUN_DATA and reference data R
EF_DATA is input. Function data F
UN_DATA is data that defines the function of this associative memory, for example, function data FUN_DAT.
Reference data R input at the same time when A is '01'
EF_DATA means mask data, and the data is stored in the mask data register. Also, for example, the function data FUN_DATA is "10".
, The reference data REF_DAT input at the same time
The reference data REF input by performing the search using A
_DATA is masked by the mask data stored in the mask data register and then supplied to each memory word via the data line drive circuit. When the data stored in the memory word matches the input data, the matching signal of logic "1" is stored in the corresponding matching flag register.

As described above, the associative memory 10 searches the contents (data) stored in a large number of memory words 11_1, 11_2, ..., 11_n by using all or a predetermined part of the reference data and matches them. A memory configured to obtain an address of a memory word having data to be read, and to read the entire data stored in the memory word as needed.

As an application of the associative memory, it has been proposed by the applicant of the present invention to input attribute data together with reference data and perform a search based on both of these data (see Japanese Patent Application No. 5-181447). The concept of this attribute will be described below. FIG. 8 is a memory structure diagram of the associative memory.

A large number of memory words constituting the associative memory are grouped into groups of four, and the first memory word in each group stores, for example, data with "attribute 0" called "name". The second memory word in the set stores, for example, data with "attribute 1" called "date of birth", and so on. Data to which "attribute 2" and "attribute 3" are attached is stored. Here, the upper k bits (for example, 2 bits) of a memory word each consisting of m bits (for example, 16 bits) are defined as an area for storing attribute data representing an attribute, and the remaining m−k bits (for example, 16-2). = 14 bits) is defined as the area in which the original data with these attributes is to be stored, and both the attribute and the data are stored in each memory word. In searching, both the attribute and the data are searched. For example, if a search is performed for both "attribute 0" and data "A", the data shown in the uppermost row in FIG. 8 will be searched.

FIG. 9 is a block diagram of an associative memory for further explaining the above concept. Note that this associative memory is basically the same as the associative memory shown in FIG. 6 only in a slightly different way of drawing for convenience of description, but some of the blocks unnecessary for the description are omitted. Has been done. Further, the same blocks as the blocks of the associative memory shown in FIG. 6 are given the same numbers as those given in FIG.

Each memory word 11_ consisting of m bits
Attribute data is stored in the upper 2 bits of 1, 11_2, ..., 11_n, and data with each attribute is stored in the remaining m-2 bits. In the search, the upper 2 bits of the reference data register 12 are set as the attribute data register 12_1 in which the search attribute data is stored, and the remaining portion of the reference data register 12 (data register 12_
2) is a reference data register in the conventional meaning described with reference to FIG. 6, and the reference data register 12 stores the attribute data and the reference data in the conventional meaning to perform a search. As a result, the desired stored data with the attribute represented by the attribute data used for the search is searched. That is, a search for the same stored data having different attributes is excluded.

The attribute data may be fixedly stored.

[0012]

When a search is performed using an associative memory, the search purpose may be achieved by performing a series of multiple continuous searches while changing mask data and attribute data. However, in order to perform such a search by using the above-mentioned associative memory, the search is performed a plurality of times while sequentially changing the mask data, or the reference data with the corresponding attribute bit is always input and searched. Therefore, there is a problem that the search procedure is complicated and the search speed during the series of searches is reduced accordingly.

In view of the above circumstances, it is an object of the present invention to provide an associative memory in which the search procedure is simplified and the search speed is improved.

[0014]

In a first associative memory of the present invention that achieves the above object, each stored data is stored in each of a plurality of memory words, reference data is input, and the input reference is input. In an associative memory that searches for a memory word in which predetermined stored data is stored using data, (1) for generating search data to be compared with each stored data by combining with input reference data A plurality of search auxiliary data registers which store each search auxiliary data in a writable manner (2) A plurality of control data registers which store the control data designating any one of the plurality of search auxiliary data registers in a writable manner (3) ) One or a plurality of signal input terminals for inputting a signal indicating the type of input reference data (4) Indicates the type of input reference data Register designating circuit for designating the control data register corresponding to the input reference data based on the signal (5) the input reference data and the control data stored in the control data register designated by the register designating circuit It is characterized by comprising a search data generating circuit for generating search data to be compared with each stored data by combining the search auxiliary data stored in the search auxiliary data register designated by.

In the first associative memory of the present invention,
The plurality of control data registers form a plurality of control data register groups each including one or a plurality of control data registers, and the register designating circuit indicates a type of reference data input to the signal input terminal. One of the plurality of control data register groups is designated based on a signal, and any one of the designated control data register groups is controlled based on the number of searches by inputting reference data. It is preferable to specify a data register.

In the second associative memory of the present invention which achieves the above object, each stored data is stored in each of a plurality of memory words, reference data is input, and the input reference data is used. In an associative memory for searching a memory word in which predetermined stored data is stored, (1) each search auxiliary data for generating search data to be compared with each stored data by combining with input reference data A plurality of search auxiliary data registers that store writably (2) A plurality of control data registers that writably store control data that specifies one of the plurality of search auxiliary data registers (3) A plurality of controls Designated data register for rewritably storing data for designating one of the data registers (4) Input reference data One or a plurality of signal input terminals for inputting a signal indicating the type of data (5) Validating either the data stored in the designated data register or the signal indicating the type of reference data input to the signal input terminal A flag register for rewritably storing a flag indicating whether or not (6) indicates the type of the data stored in the designated data register or the reference data input to the signal input terminal according to the flag stored in the flag register. A register designating circuit that designates any one of the plurality of control data registers based on a signal (7) Input reference data and control data stored in the control data register designated by the register designating circuit By combining the search auxiliary data stored in the search auxiliary data register specified by It is characterized in that it comprises a search data generating circuit for generating a search data to be compared with the data.

Here, in the second associative memory of the present invention, each of the plurality of control data registers is 1
A plurality of control data registers consisting of one or a plurality of control data registers, and the register designating circuit,
In accordance with the flag stored in the flag register, based on the data stored in the designated data register or the signal representing the type of reference data input to the signal input terminal, the plurality of control data register groups It is preferable to specify any one of them, and also to specify any one of the control data registers in the specified control data register group based on the number of searches by inputting reference data.

Further, in the first associative memory and the second associative memory of the present invention, when a control data register group is formed, a sequence reset for resetting the number of searches for designating the control data register for the first time. It is preferable to have a configuration including a reset terminal for inputting a signal.

[0019]

In the first associative memory of the present invention, a plurality of search auxiliary data such as the mask data and the attribute data described above are stored in a writable manner, and when searching, the reference data and the type of the reference data are stored. Since it can be inputted from the signal input terminal whether or not it is the (configuration), the procedure of switching the reference data search procedure having a different configuration can be simplified and the speed can be improved. Further, during the series of searches, for example, the trouble of rewriting the mask data is unnecessary, the procedure for the search is simplified, and the search speed at the time of performing the series of searches can be improved.

The second associative memory of the present invention, like the above-mentioned first associative memory, stores a plurality of search auxiliary data such as the above-mentioned mask data and attribute data in a freely writable manner, and makes reference data when searching. Along with this, the type (configuration) of the reference data can be input as a signal, but the point different from the first associative memory is that the data for specifying the control data register can be rewritten. And a flag register for designating the search procedure by a signal indicating the type of reference data input to the signal input terminal, or by designating the search procedure by the data stored in the designated data register. Due to the provision of the signal input terminal, if different types of reference data are input continuously, Search procedure increased simplification and speed switching is achieved by specifying the search procedure. on the other hand,
By storing the data specifying the search procedure in the specified data register and specifying the search procedure by the specified data register by the register specifying circuit, it is stored in the associative memory by another system that does not belong to the reference data type, for example, attribute data. It is possible to simplify the procedure for performing a search for managing the stored data.

When performing a series of searches consisting of a plurality of searches, the search is performed using the first mask data and the first attribute data, and then the same as above. In many cases, the search pattern can be typified in advance, such as using the first mask data and performing a search using the second attribute data different from the above. Therefore, in the present invention, by adopting the concept of the control data register group described above, instead of sequentially designating different control data registers, a series of signals can be obtained by sequentially inputting a signal representing the type designating the type together with the reference data. A search is performed, or a series of searches are performed by only once inputting the channel designation data of the control register group and then sequentially inputting the reference data, and the search procedure is further simplified.

Further, in the case where the control data register group is configured, if the number of searches is automatically reset for the first time, for example, a search may be performed at a timing when search is not necessary. By providing the reset terminal of (1), it is possible to reset only when necessary after the end of the previous search and start a new search.

[0023]

Embodiments of the present invention will be described below. Here, first, an embodiment of the second associative memory of the present invention will be described, and then differences between the first associative memory of the present invention and the second associative memory will be described. Figure 1
2 is a functional block diagram of an embodiment of the second associative memory of the present invention, FIG. 2 is a block diagram of an embodiment of a system using the second associative memory of the present invention, and FIG. 3 is a diagram of the system shown in FIG. FIG. 5 is a diagram showing an example of a data structure of reference data sent on a reference data input bus.

In each of a large number of memory words forming this associative memory, both segment data corresponding to the above-mentioned attribute data and normal data are stored. Further, this associative memory is provided with N segment registers which are an example of the search auxiliary data register according to the present invention, and N mask registers which are another example of the search auxiliary data register according to the present invention. It is equipped.

Any of these segment registers,
Alternatively, when writing segment data or mask data to one of the mask registers, the data A to be written is input and the function data F is input.
By specifying the register to be written by UN_DATA (see FIG. 7) and further inputting the WRITE signal, the desired data A is written in the desired register.

Further, the associative memory is provided with a plurality of channels (control data register group referred to in the present invention) including a plurality of control data registers each storing control data. The control data stored in each control data register is for designating one of the segment registers and one of the mask registers at the time of search.

When writing each control data into each control data register, the data A to be written is input, the channel to be written is designated, and the WRITE signal is input. Then, the data A becomes the control data
It is stored in the lowest-numbered control data register of the free control data registers of the specified channel.
For example, after initialization, when channel 1 is designated for the first time, control data is stored in the control data register (1) of channel 1, and when channel 1 is designated for the second time, channel 1 ( The control data is stored in the control data register of 2).

Further, the associative memory has a register designation indicating whether the reference data type signal input from the data type signal input terminal is valid or the data stored in the designated data register is valid. A register designation selection flag register for storing the selection flag is provided. In the search, first, the data shown in FIG. 3 sent on the reference data input bus shown in FIG. 2 is taken in by the data taking-in circuit (see FIG. 2). The data acquisition circuit may be one commonly used in network equipment. Then, the data indicating the data type of the protocol portion of the fetched data is input to the data type signal input terminal of the associative memory, and the WRITE signal instructing the search using the reference data A is input. Register specification selection flag If the register stores a flag that specifies the register by the reference data type signal input from the data type signal input terminal,
The input reference data type signal is decoded by the decoder of the register designating circuit and designates one of the plurality of channels. Here, it is assumed that the channel 1 is designated. Then, the control data stored in the control data register (1) of channel 1 designates one of the N segment registers and one of the N mask registers. The control data stored in the control data register (1) of the channel 1 designates, for example, the segment register # 2 of the N segment registers and, for example, the mask register # of the N mask registers. If the control data specifies 3,
The input data A is masked by the mask register stored in the mask register # 3, search data including both the data generated thereby and the segment data stored in the segment register # 2, and each memory. A match comparison is performed with each stored data stored in the word.

Next, when the reference data B following the previous search by the reference data A is input to the reference data input bus shown in FIG. 2, this time it is stored in the control data register (2) of channel 1. The control data specifies one of the N segment registers and one of the N mask registers. For example, when the control data stored in the control data register (2) of channel 1 specifies the segment register # 1 and the mask register # 1, the mask stored in the mask register # 1 for the input data B The data is masked and the search data consisting of both the data generated by this and the segment data stored in the segment register # 1 is compared with the stored data stored in each memory word. Be seen.

Further, the data stored in the associative memory is managed from a local bus (a bus for individually accessing each associative memory) which is a system completely different from the reference data input bus, and the data is stored in the associative memory. A search is also performed when performing management and the like. In the search, the data designating the channel for the search from the local bus is stored in advance in the designated data register, and the designated data register is used to designate the register in the register designation selection flag register of the register designation circuit. Store the flag. As a result, one of the plurality of channels is designated by the output of the designated data register. Here, it is assumed that the channel m is designated.

When the reference data A is input from the local bus, the control data stored in the control data register (1) of the channel m causes one of the N segment registers and the N mask registers to be selected. One of them is designated. The control data stored in the control data register (1) of the channel designates, for example, the segment register # 2 of the N segment registers, and, for example, the mask register # 3 of the N mask registers. If the control data specifies, the input data A is masked by the mask register stored in the mask register # 3, and the generated data and the segment stored in the segment register # 2 are masked. Matching comparison is performed between the search data composed of both data and each stored data stored in each memory word.

Next, without changing the data stored in the designated data register, when new data B is input as reference data and a search is instructed, this time it is stored in the control data register (2) of channel m. The control data being specified specifies one of the N segment registers and one of the N mask registers. For example, when the control data stored in the control data register (2) of the channel m specifies the segment register # 1 and the mask register # 1, the mask stored in the mask register # 1 for the input data B The data is masked, and the search data consisting of both the data generated thereby and the segment data stored in the segment register # 1 is compared with each stored data stored in each memory word. .

As described above, in the associative memory shown in FIG. 1 and the system shown in FIG. 2, each channel stores a plurality of control data for designating the segment register and the mask register, that is, each channel. Store each search mode, and search for channels
By specifying the reference data type input to the data type signal input terminal or the data stored in the specified data register, the search is performed according to the search mode stored in the specified channel. .
Therefore, a series of searches are performed only by inputting reference data, so that the search procedure is simplified and the series of searches is performed at high speed.

In the associative memory shown in FIG. 1, m search modes can be stored at the same time, and the search modes can be rewritten, so that an associative memory having a large degree of freedom can be realized. . Further, by providing the data type signal input terminal for inputting the signal indicating the type of reference data, the procedure of channel switching depending on the type of reference data is simplified and the search operation as the system is performed at high speed. Furthermore, not only the data type signal input terminal, but also the channel can be specified from the register (specified data register) that stores the data that specifies the specific channel. It is possible to freely perform a search from a completely different system, for example, management for data stored in the associative memory, and the procedure for managing the associative memory is simplified.

It is assumed that, for example, m-bit parallel data as shown in FIG. 3 is sequentially input in the arrow direction. The series of data sets is referred to as a data packet here. At the beginning of each data packet, a protocol indicating the procedure of data communication, the type of the data, etc. is arranged, and in the present associative memory, data is searched for the part of the protocol. When the data search of the protocol portion of a certain data packet is completed, the channel used for the data search (for example, channel 1; see FIGS. 1 and 2) is the last control data register constituting the channel 1. It is in the specified state and, therefore, before the next search using that channel 1, the first control data register comprising that channel 1 must be reset to be specified. However, in the case of handling the data as shown in FIG. 3, if the search of the protocol part of a certain data packet is automatically reset, the search operation is performed up to the part of the data bucket following the protocol. It will be. Therefore, as shown in FIG. 1, the reset signal is inputted from the outside, and the reset signal is reset at the end time of a data packet or the input start time of the next data packet, whereby the above inconvenience can be avoided.

In the above embodiment, both the segment register and the mask register are designated by the control data, but only the segment register may be designated, or only the mask register is designated. May be designated, and as the search auxiliary data register according to the present invention, a register for storing search auxiliary data for assisting the search other than the segment data and the mask data may be provided.

FIG. 4 is a functional block diagram of an embodiment of the first associative memory of the present invention, and FIG. 5 is a block diagram of an example of a system constituted by this associative memory. The difference from the second associative memory of FIGS. 1 and 2 is that the channel is specified only by the input of a signal indicating the type of reference data. Therefore, the individual management procedure of each associative memory in the system is not simplified, but a series of search procedures are simplified and speeded up, the flexibility of the associative memory is improved, and the channel switching procedure according to the type of reference data is improved. Simplification and speedup can be realized.

[0038]

As described above, according to the present invention,
Designates control data registers by providing multiple search auxiliary registers such as segment registers and mask registers, multiple control data registers, and signal input terminals for designating control data registers for search. Since it is possible to select, the degree of freedom of search is improved, the search procedure is simplified, the search speed is improved, and the search procedure switching means is simplified and speeded up. .

Further, according to the second associative memory of the present invention, since the designated data register and the flag register are further provided, the management procedure of the data stored in the associative memory can be simplified and speeded up.

[Brief description of drawings]

FIG. 1 is a functional block diagram of an embodiment of a second associative memory of the present invention.

FIG. 2 is a configuration diagram of an example of a system configured by a second associative memory of the present invention.

FIG. 3 is a diagram showing an example of a data structure handled by an associative memory.

FIG. 4 is a functional block diagram of an embodiment of a first associative memory of the present invention.

FIG. 5 is a configuration diagram of an example of a system including a first associative memory according to the present invention.

FIG. 6 is a circuit block diagram showing an example of a conventional associative memory.

FIG. 7 is a functional block diagram of a conventional associative memory.

FIG. 8 is a memory structure diagram of an associative memory.

FIG. 9 is a block diagram of an associative memory.

[Description of Codes] 10 Associative Memory 11_1, 11_2, ..., 11_n Memory Word 12 Reference Data Register 13 Mask Register 16 Encoder 17 Decoder

Claims (5)

[Claims] 1. Storage data is stored in each of a plurality of memory words, reference data is input, and the input reference data is used to search for a memory word in which predetermined storage data is stored. In the associative memory, a plurality of search auxiliary data registers for writably storing each search auxiliary data for generating search data to be compared with each stored data by combining with the input reference data; One of the auxiliary data registers
A plurality of control data registers for freely storing control data designating one of them, one or a plurality of signal input terminals for inputting a signal representing the type of reference data to be input, and the signal input terminals A register designating circuit that designates the control data register corresponding to the input reference data based on a signal representing the type of reference data, the input reference data, and the control data register designated by the register designating circuit. And a search data generation circuit that generates search data to be compared with each stored data by combining the search auxiliary data stored in the search auxiliary data register specified by the stored control data. Characteristic associative memory. 2. A reference input to the signal input terminal, wherein the plurality of control data registers constitute a plurality of control data register groups each including one or a plurality of control data registers. One of the plurality of control data register groups is designated based on a signal representing the type of data, and the designated control data register group is designated based on the number of times of search by inputting reference data. 2. The associative memory according to claim 1, wherein any one of the control data registers is designated. 3. A storage word is stored in each of a plurality of memory words, reference data is input, and the input reference data is used to search for a memory word in which predetermined storage data is stored. In the associative memory, a plurality of search auxiliary data registers for writably storing each search auxiliary data for generating search data to be compared with each stored data by combining with the input reference data; A plurality of control data registers for rewritably storing control data designating any one of the data registers, and a data for designating any one of the plurality of control data registers rewritably A designated data register and one or more signal inputs for inputting a signal representing the type of each reference data to be input. A terminal, a flag register that rewritably stores a flag indicating which of the data stored in the designated data register and the signal representing the type of reference data input to the signal input terminal is valid, Of the plurality of control data registers based on the data stored in the designated data register or the signal indicating the type of the reference data input to the signal input terminal according to the flag stored in the flag register. Stored in the search auxiliary data register designated by the register designating circuit that designates any one of the above, input reference data, and control data stored in the control data register designated by the register designating circuit. By combining with the search assistance data, the search data that is compared with the stored data is generated. An associative memory having a search data generation circuit. 4. The plurality of control data registers constitute a plurality of control data register groups each including one or a plurality of control data registers, and the register designating circuit responds to a flag stored in the flag register. One of the plurality of control data register groups is designated based on the data stored in the designated data register or a signal indicating the type of reference data input to the signal input terminal. 4. The associative memory according to claim 3, wherein any one of the control data register groups designated is designated based on the number of times of the search by inputting reference data. . 5. The associative memory according to claim 2, further comprising a reset terminal for inputting a sequence reset signal for initially resetting the number of searches for designating the control data register.